MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 3346 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 3344 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 1366 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 3570 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0