MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 3256 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 3254 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 1276 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 3480 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0