MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 3366 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 3364 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 1386 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 3590 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0