MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 3372 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 3370 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 1392 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 3596 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0