MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 3266 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 3264 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 1286 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 3490 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10