MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 3400 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 3398 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 1420 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 3624 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0