MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 3402 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 3400 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 1422 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 3626 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0