MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 3404 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 3402 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 1424 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 3628 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0