MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 3412 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 3410 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 1432 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 3636 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0