MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 3268 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 3266 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 1288 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 3492 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0