MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 3422 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 3420 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 1442 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 3646 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0