MC_REGISTERS_TABLE_72__data_3_value_6_MASK 3423 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
MC_REGISTERS_TABLE_72__data_3_value_6_MASK 3421 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
MC_REGISTERS_TABLE_72__data_3_value_6_MASK 1443 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
MC_REGISTERS_TABLE_72__data_3_value_6_MASK 3647 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff