MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 3432 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 3430 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 1452 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 3656 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0