MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 3274 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 3272 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 1294 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 3498 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10