MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 3282 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 3280 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 1302 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 3506 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10