mii_wr            971 drivers/net/ethernet/dec/tulip/de4x5.c static void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
mii_wr           2771 drivers/net/ethernet/dec/tulip/de4x5.c 		    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           2784 drivers/net/ethernet/dec/tulip/de4x5.c 		    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           2803 drivers/net/ethernet/dec/tulip/de4x5.c 		mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           2973 drivers/net/ethernet/dec/tulip/de4x5.c 		    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           2986 drivers/net/ethernet/dec/tulip/de4x5.c 		mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           3311 drivers/net/ethernet/dec/tulip/de4x5.c 	        mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr           5021 drivers/net/ethernet/dec/tulip/de4x5.c 	    mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
mii_wr            925 drivers/net/ethernet/dec/tulip/de4x5.h       mii_wr(MII_CR_10|(lp->fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
mii_wr            947 drivers/net/ethernet/dec/tulip/de4x5.h         mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
mii_wr            954 drivers/net/ethernet/dec/tulip/de4x5.h       mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
mii_wr            975 drivers/net/ethernet/dec/tulip/de4x5.h     mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
mii_wr            259 drivers/net/ethernet/xircom/xirc2ps_cs.c static void mii_wr(unsigned int ioaddr, u_char phyaddr, u_char phyreg,
mii_wr           1443 drivers/net/ethernet/xircom/xirc2ps_cs.c 	mii_wr(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in,
mii_wr           1656 drivers/net/ethernet/xircom/xirc2ps_cs.c     mii_wr(ioaddr,  0, 0, control, 16);
mii_wr           1682 drivers/net/ethernet/xircom/xirc2ps_cs.c 		mii_wr(ioaddr,  0, 0, control, 16);