pll_info 76 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info; pll_info 84 drivers/clk/ingenic/cgu.c pll_info = &clk_info->pll; pll_info 87 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 90 drivers/clk/ingenic/cgu.c m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); pll_info 91 drivers/clk/ingenic/cgu.c m += pll_info->m_offset; pll_info 92 drivers/clk/ingenic/cgu.c n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); pll_info 93 drivers/clk/ingenic/cgu.c n += pll_info->n_offset; pll_info 94 drivers/clk/ingenic/cgu.c od_enc = ctl >> pll_info->od_shift; pll_info 95 drivers/clk/ingenic/cgu.c od_enc &= GENMASK(pll_info->od_bits - 1, 0); pll_info 96 drivers/clk/ingenic/cgu.c bypass = !pll_info->no_bypass_bit && pll_info 97 drivers/clk/ingenic/cgu.c !!(ctl & BIT(pll_info->bypass_bit)); pll_info 102 drivers/clk/ingenic/cgu.c for (od = 0; od < pll_info->od_max; od++) { pll_info 103 drivers/clk/ingenic/cgu.c if (pll_info->od_encoding[od] == od_enc) pll_info 106 drivers/clk/ingenic/cgu.c BUG_ON(od == pll_info->od_max); pll_info 117 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info; pll_info 120 drivers/clk/ingenic/cgu.c pll_info = &clk_info->pll; pll_info 129 drivers/clk/ingenic/cgu.c n = max_t(unsigned, n, pll_info->n_offset); pll_info 133 drivers/clk/ingenic/cgu.c m = max_t(unsigned, m, pll_info->m_offset); pll_info 174 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll_info 186 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 188 drivers/clk/ingenic/cgu.c ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); pll_info 189 drivers/clk/ingenic/cgu.c ctl |= (m - pll_info->m_offset) << pll_info->m_shift; pll_info 191 drivers/clk/ingenic/cgu.c ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); pll_info 192 drivers/clk/ingenic/cgu.c ctl |= (n - pll_info->n_offset) << pll_info->n_shift; pll_info 194 drivers/clk/ingenic/cgu.c ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); pll_info 195 drivers/clk/ingenic/cgu.c ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; pll_info 197 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); pll_info 208 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll_info 215 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 217 drivers/clk/ingenic/cgu.c ctl &= ~BIT(pll_info->bypass_bit); pll_info 218 drivers/clk/ingenic/cgu.c ctl |= BIT(pll_info->enable_bit); pll_info 220 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); pll_info 224 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 225 drivers/clk/ingenic/cgu.c if (ctl & BIT(pll_info->stable_bit)) pll_info 243 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll_info 248 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 250 drivers/clk/ingenic/cgu.c ctl &= ~BIT(pll_info->enable_bit); pll_info 252 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); pll_info 261 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll_info 266 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); pll_info 269 drivers/clk/ingenic/cgu.c return !!(ctl & BIT(pll_info->enable_bit)); pll_info 437 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.crystal_frequency = pll_info 439 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_input_pxl_clk_pll_frequency = pll_info 441 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_input_pxl_clk_pll_frequency = pll_info 443 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_output_pxl_clk_pll_frequency = pll_info 445 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_output_pxl_clk_pll_frequency = pll_info 488 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.crystal_frequency = pll_info 490 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_input_pxl_clk_pll_frequency = pll_info 492 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_input_pxl_clk_pll_frequency = pll_info 494 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_output_pxl_clk_pll_frequency = pll_info 496 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_output_pxl_clk_pll_frequency = pll_info 574 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.crystal_frequency = pll_info 576 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_input_pxl_clk_pll_frequency = pll_info 578 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_input_pxl_clk_pll_frequency = pll_info 580 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.min_output_pxl_clk_pll_frequency = pll_info 582 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->pll_info.max_output_pxl_clk_pll_frequency = pll_info 1191 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; pll_info 1194 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c if (info->pll_info.crystal_frequency == 0) pll_info 1195 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->pll_info.crystal_frequency = 27000; pll_info 1264 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; pll_info 1266 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c if (info->pll_info.crystal_frequency == 0) { pll_info 1268 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->pll_info.crystal_frequency = 27000; pll_info 1270 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->pll_info.crystal_frequency = 100000; pll_info 191 drivers/gpu/drm/amd/display/dc/core/dc_resource.c dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; pll_info 759 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c const struct audio_pll_info *pll_info, pll_info 774 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c pll_info->dp_dto_source_clock_in_khz * 10; pll_info 781 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c const struct audio_pll_info *pll_info) pll_info 817 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c src_sel = pll_info->dto_source - DTO_SOURCE_ID0; pll_info 839 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c pll_info, pll_info 153 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct audio_pll_info *pll_info); pll_info 1249 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; pll_info 1251 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fw_info->pll_info.min_output_pxl_clk_pll_frequency; pll_info 1253 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fw_info->pll_info.max_output_pxl_clk_pll_frequency; pll_info 1260 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fw_info->pll_info.max_input_pxl_clk_pll_frequency; pll_info 1267 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fw_info->pll_info.min_input_pxl_clk_pll_frequency; pll_info 1376 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; pll_info 625 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1; pll_info 1174 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->pll_info.dp_dto_source_clock_in_khz = pll_info 1179 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->pll_info.feed_back_divider = pll_info 1182 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->pll_info.dto_source = pll_info 1187 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->pll_info.ss_enabled = true; pll_info 1189 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c audio_output->pll_info.ss_percentage = pll_info 1994 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &audio_output.pll_info); pll_info 2022 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &audio_output.pll_info); pll_info 1218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; pll_info 1224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, pll_info 51 drivers/gpu/drm/amd/display/dc/inc/hw/audio.h const struct audio_pll_info *pll_info); pll_info 99 drivers/gpu/drm/amd/display/include/audio_types.h struct audio_pll_info pll_info; pll_info 165 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h } pll_info; pll_info 735 drivers/gpu/drm/radeon/radeon_combios.c uint16_t pll_info; pll_info 743 drivers/gpu/drm/radeon/radeon_combios.c pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); pll_info 744 drivers/gpu/drm/radeon/radeon_combios.c if (pll_info) { pll_info 745 drivers/gpu/drm/radeon/radeon_combios.c rev = RBIOS8(pll_info); pll_info 748 drivers/gpu/drm/radeon/radeon_combios.c p1pll->reference_freq = RBIOS16(pll_info + 0xe); pll_info 749 drivers/gpu/drm/radeon/radeon_combios.c p1pll->reference_div = RBIOS16(pll_info + 0x10); pll_info 750 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_out_min = RBIOS32(pll_info + 0x12); pll_info 751 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_out_max = RBIOS32(pll_info + 0x16); pll_info 756 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_min = RBIOS32(pll_info + 0x36); pll_info 757 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); pll_info 765 drivers/gpu/drm/radeon/radeon_combios.c spll->reference_freq = RBIOS16(pll_info + 0x1a); pll_info 766 drivers/gpu/drm/radeon/radeon_combios.c spll->reference_div = RBIOS16(pll_info + 0x1c); pll_info 767 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_out_min = RBIOS32(pll_info + 0x1e); pll_info 768 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_out_max = RBIOS32(pll_info + 0x22); pll_info 771 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_min = RBIOS32(pll_info + 0x48); pll_info 772 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_max = RBIOS32(pll_info + 0x4c); pll_info 780 drivers/gpu/drm/radeon/radeon_combios.c mpll->reference_freq = RBIOS16(pll_info + 0x26); pll_info 781 drivers/gpu/drm/radeon/radeon_combios.c mpll->reference_div = RBIOS16(pll_info + 0x28); pll_info 782 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_out_min = RBIOS32(pll_info + 0x2a); pll_info 783 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_out_max = RBIOS32(pll_info + 0x2e); pll_info 786 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_min = RBIOS32(pll_info + 0x5a); pll_info 787 drivers/gpu/drm/radeon/radeon_combios.c mpll->pll_in_max = RBIOS32(pll_info + 0x5e); pll_info 795 drivers/gpu/drm/radeon/radeon_combios.c sclk = RBIOS16(pll_info + 0xa); pll_info 796 drivers/gpu/drm/radeon/radeon_combios.c mclk = RBIOS16(pll_info + 0x8); pll_info 805 drivers/gpu/drm/radeon/radeon_combios.c if (RBIOS32(pll_info + 0x16)) pll_info 806 drivers/gpu/drm/radeon/radeon_combios.c rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); pll_info 191 drivers/gpu/drm/rcar-du/rcar_lvds.c unsigned long target, struct pll_info *pll, pll_info 324 drivers/gpu/drm/rcar-du/rcar_lvds.c struct pll_info pll = { .diff = (unsigned long)-1 }; pll_info 138 drivers/video/fbdev/aty/atyfb.h struct pll_info pll_limits; pll_info 342 drivers/video/fbdev/aty/radeonfb.h struct pll_info pll;