si_write_smc_soft_register 1844 drivers/gpu/drm/amd/amdgpu/si_dpm.c static int si_write_smc_soft_register(struct amdgpu_device *adev,
si_write_smc_soft_register 2824 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
si_write_smc_soft_register 3829 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
si_write_smc_soft_register 4107 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
si_write_smc_soft_register 4123 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
si_write_smc_soft_register 4124 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
si_write_smc_soft_register 4125 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
si_write_smc_soft_register 4126 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
si_write_smc_soft_register 4519 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
si_write_smc_soft_register 4521 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
si_write_smc_soft_register 4523 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
si_write_smc_soft_register 4562 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
si_write_smc_soft_register 5136 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
si_write_smc_soft_register 5202 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
si_write_smc_soft_register 5234 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
si_write_smc_soft_register 5714 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev,
si_write_smc_soft_register 5798 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if (si_write_smc_soft_register(adev,
si_write_smc_soft_register 5803 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if (si_write_smc_soft_register(adev,
si_write_smc_soft_register 5808 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if (si_write_smc_soft_register(adev,
si_write_smc_soft_register 6115 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
si_write_smc_soft_register 6385 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
si_write_smc_soft_register 1753 drivers/gpu/drm/radeon/si_dpm.c static int si_write_smc_soft_register(struct radeon_device *rdev,
si_write_smc_soft_register 2725 drivers/gpu/drm/radeon/si_dpm.c 	ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
si_write_smc_soft_register 3370 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
si_write_smc_soft_register 3647 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
si_write_smc_soft_register 3664 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
si_write_smc_soft_register 3665 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
si_write_smc_soft_register 3666 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
si_write_smc_soft_register 3667 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
si_write_smc_soft_register 4057 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
si_write_smc_soft_register 4059 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
si_write_smc_soft_register 4061 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
si_write_smc_soft_register 4100 drivers/gpu/drm/radeon/si_dpm.c 				si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
si_write_smc_soft_register 4673 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
si_write_smc_soft_register 4740 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
si_write_smc_soft_register 4772 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
si_write_smc_soft_register 5252 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev,
si_write_smc_soft_register 5338 drivers/gpu/drm/radeon/si_dpm.c 	if (si_write_smc_soft_register(rdev,
si_write_smc_soft_register 5343 drivers/gpu/drm/radeon/si_dpm.c 	if (si_write_smc_soft_register(rdev,
si_write_smc_soft_register 5348 drivers/gpu/drm/radeon/si_dpm.c 	if (si_write_smc_soft_register(rdev,
si_write_smc_soft_register 5661 drivers/gpu/drm/radeon/si_dpm.c 	si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
si_write_smc_soft_register 5927 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);