upper_32_bits 277 arch/arc/kernel/perf_event.c write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value)); upper_32_bits 382 arch/arc/kernel/perf_event.c upper_32_bits(arc_pmu->max_period)); upper_32_bits 711 arch/arc/mm/cache.c write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end)); upper_32_bits 716 arch/arc/mm/cache.c write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr)); upper_32_bits 119 arch/arm/include/asm/arch_gicv3.h write_sysreg(upper_32_bits(val), a32hi);\ upper_32_bits 2067 arch/arm64/kernel/cpufeature.c return upper_32_bits(elf_hwcap); upper_32_bits 1519 arch/arm64/kernel/insn.c if (upper_32_bits(imm)) upper_32_bits 454 arch/arm64/kernel/perf_event.c armv8pmu_write_evcntr(idx, upper_32_bits(value)); upper_32_bits 666 arch/arm64/kernel/traps.c pt_regs_write_reg(regs, rt2, upper_32_bits(val)); upper_32_bits 225 arch/arm64/kvm/sys_regs.c val = ((u64)upper_32_bits(val) << 32) | upper_32_bits 2160 arch/arm64/kvm/sys_regs.c vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); upper_32_bits 25 arch/powerpc/include/asm/ppc-pci.h #define BUID_HI(buid) upper_32_bits(buid) upper_32_bits 176 arch/powerpc/mm/nohash/book3e_hugetlbpage.c mtspr(SPRN_MAS7, upper_32_bits(mas7_3)); upper_32_bits 69 arch/powerpc/platforms/4xx/hsta_msi.c msg.address_hi = upper_32_bits(addr); upper_32_bits 167 arch/powerpc/platforms/4xx/msi.c msi->msi_addr_hi = upper_32_bits(msi_phys); upper_32_bits 172 arch/powerpc/platforms/4xx/msi.c mtdcri(SDR0, *sdr_addr, upper_32_bits(res.start)); /*HIGH addr */ upper_32_bits 107 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4); upper_32_bits 159 arch/powerpc/sysdev/fsl_msi.c msg->address_hi = upper_32_bits(address); upper_32_bits 466 arch/sh/drivers/pci/pcie-sh7786.c pci_write_reg(chan, upper_32_bits(res->start), upper_32_bits 92 arch/x86/include/asm/mshyperv.h u32 input_address_hi = upper_32_bits(input_address); upper_32_bits 94 arch/x86/include/asm/mshyperv.h u32 output_address_hi = upper_32_bits(output_address); upper_32_bits 127 arch/x86/include/asm/mshyperv.h u32 input1_hi = upper_32_bits(input1); upper_32_bits 160 arch/x86/include/asm/mshyperv.h u32 input1_hi = upper_32_bits(input1); upper_32_bits 162 arch/x86/include/asm/mshyperv.h u32 input2_hi = upper_32_bits(input2); upper_32_bits 858 arch/x86/kvm/svm.c high = upper_32_bits(val); upper_32_bits 2867 arch/x86/kvm/svm.c high = upper_32_bits(value); upper_32_bits 775 drivers/block/rsxx/dma.c iowrite32(upper_32_bits(ctrl->status.dma_addr), upper_32_bits 780 drivers/block/rsxx/dma.c iowrite32(upper_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_HI); upper_32_bits 1052 drivers/char/agp/intel-gtt.c upper_32_bits(intel_private.ifp_resource.start)); upper_32_bits 102 drivers/clocksource/arm_global_timer.c writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1); upper_32_bits 191 drivers/crypto/caam/desc_constr.h *(++offset) = cpu_to_caam32(upper_32_bits(data)); upper_32_bits 193 drivers/crypto/caam/desc_constr.h *offset = cpu_to_caam32(upper_32_bits(data)); upper_32_bits 178 drivers/crypto/caam/regs.h (u64)cpu_to_caam32(upper_32_bits(value))); upper_32_bits 187 drivers/crypto/caam/regs.h (u64)caam32_to_cpu(upper_32_bits(value))); upper_32_bits 223 drivers/crypto/ccp/ccp-dev-v3.c cr[5] = upper_32_bits(op->u.sha.msg_bits); upper_32_bits 397 drivers/crypto/ccp/ccp-dev-v5.c CCP5_CMD_SHA_HI(&desc) = upper_32_bits(op->u.sha.msg_bits); upper_32_bits 563 drivers/crypto/ccp/ccp-dev.h return upper_32_bits(info->address + info->offset) & 0x0000ffff; upper_32_bits 164 drivers/crypto/ccp/psp-dev.c phys_msb = data ? upper_32_bits(__psp_pa(data)) : 0; upper_32_bits 176 drivers/crypto/hisilicon/qm.c (qc)->base_h = upper_32_bits(base); \ upper_32_bits 358 drivers/crypto/hisilicon/qm.c mailbox.base_h = upper_32_bits(dma_addr); upper_32_bits 697 drivers/crypto/hisilicon/qm.c writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H); upper_32_bits 1589 drivers/crypto/hisilicon/qm.c eqc->base_h = upper_32_bits(qm->eqe_dma); upper_32_bits 1610 drivers/crypto/hisilicon/qm.c aeqc->base_h = upper_32_bits(qm->aeqe_dma); upper_32_bits 139 drivers/crypto/hisilicon/sec/sec_algs.c req->cipher_key_addr_hi = upper_32_bits(ctx->pkey); upper_32_bits 676 drivers/crypto/hisilicon/sec/sec_algs.c req->data_addr_hi = upper_32_bits(el->dma_in); upper_32_bits 688 drivers/crypto/hisilicon/sec/sec_algs.c req->cipher_destin_addr_hi = upper_32_bits(el->dma_out); upper_32_bits 693 drivers/crypto/hisilicon/sec/sec_algs.c req->cipher_destin_addr_hi = upper_32_bits(el->dma_in); upper_32_bits 784 drivers/crypto/hisilicon/sec/sec_algs.c el->req.cipher_iv_addr_hi = upper_32_bits(sec_req->dma_iv); upper_32_bits 580 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(upper_32_bits(addr), queue->regs + SEC_Q_BASE_HADDR_REG); upper_32_bits 586 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(upper_32_bits(addr), upper_32_bits 594 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(upper_32_bits(addr), upper_32_bits 105 drivers/crypto/hisilicon/zip/zip_crypto.c sqe->source_addr_h = upper_32_bits(s_addr); upper_32_bits 107 drivers/crypto/hisilicon/zip/zip_crypto.c sqe->dest_addr_h = upper_32_bits(d_addr); upper_32_bits 479 drivers/crypto/inside-secure/safexcel.c writel(upper_32_bits(priv->ring[i].cdr.base_dma), upper_32_bits 527 drivers/crypto/inside-secure/safexcel.c writel(upper_32_bits(priv->ring[i].rdr.base_dma), upper_32_bits 134 drivers/crypto/inside-secure/safexcel_ring.c cdesc->data_hi = upper_32_bits(data); upper_32_bits 152 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.context_hi = upper_32_bits(context); upper_32_bits 185 drivers/crypto/inside-secure/safexcel_ring.c rdesc->data_hi = upper_32_bits(data); upper_32_bits 53 drivers/crypto/talitos.c ptr->eptr = upper_32_bits(dma_addr); upper_32_bits 314 drivers/crypto/talitos.c upper_32_bits(request->dma_desc)); upper_32_bits 75 drivers/dma/acpi-dma.c si->mmio_base_high != upper_32_bits(mem) || upper_32_bits 271 drivers/dma/altera-msgdma.c desc->read_addr_hi = upper_32_bits(src); upper_32_bits 272 drivers/dma/altera-msgdma.c desc->write_addr_hi = upper_32_bits(dst); upper_32_bits 74 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); upper_32_bits 217 drivers/dma/dw-edma/dw-edma-v0-core.c SET_LL(&lli[i].sar_high, upper_32_bits(child->sar)); upper_32_bits 220 drivers/dma/dw-edma/dw-edma-v0-core.c SET_LL(&lli[i].dar_high, upper_32_bits(child->dar)); upper_32_bits 233 drivers/dma/dw-edma/dw-edma-v0-core.c SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr)); upper_32_bits 263 drivers/dma/dw-edma/dw-edma-v0-core.c upper_32_bits(chunk->ll_region.paddr)); upper_32_bits 227 drivers/dma/fsl-qdma.c ccdf->addr_hi = upper_32_bits(addr); upper_32_bits 247 drivers/dma/fsl_raid.c cf[index].addr_high = upper_32_bits(addr); upper_32_bits 261 drivers/dma/fsl_raid.c desc->hwdesc.lbea32 = upper_32_bits(paddr); upper_32_bits 695 drivers/dma/ioat/dma.c writel(upper_32_bits(ioat_chan->completion_dma), upper_32_bits 209 drivers/dma/mv_xor_v2.c upper_32_bits(src) & 0xFFFF; upper_32_bits 216 drivers/dma/mv_xor_v2.c (upper_32_bits(src) & 0xFFFF) << 16; upper_32_bits 409 drivers/dma/mv_xor_v2.c upper_32_bits(src) & 0xFFFF; upper_32_bits 414 drivers/dma/mv_xor_v2.c upper_32_bits(dest) & 0xFFFF; upper_32_bits 473 drivers/dma/mv_xor_v2.c upper_32_bits(dest) & 0xFFFF; upper_32_bits 636 drivers/dma/mv_xor_v2.c writel(upper_32_bits(xor_dev->hw_desq), upper_32_bits 623 drivers/dma/qcom/hidma_ll.c tre_local[HIDMA_TRE_SRC_HI_IDX] = upper_32_bits(src); upper_32_bits 625 drivers/dma/qcom/hidma_ll.c tre_local[HIDMA_TRE_DEST_HI_IDX] = upper_32_bits(dest); upper_32_bits 668 drivers/dma/qcom/hidma_ll.c writel(upper_32_bits(addr), lldev->trca + HIDMA_TRCA_RING_HIGH_REG); upper_32_bits 673 drivers/dma/qcom/hidma_ll.c writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG); upper_32_bits 832 drivers/dma/sprd-dma.c hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) & upper_32_bits 542 drivers/dma/xilinx/xilinx_dma.c hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + upper_32_bits 918 drivers/dma/xilinx/xilinx_dma.c upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * upper_32_bits 1680 drivers/dma/xilinx/xilinx_dma.c hw->buf_addr_msb = upper_32_bits(xt->dst_start); upper_32_bits 1687 drivers/dma/xilinx/xilinx_dma.c hw->buf_addr_msb = upper_32_bits(xt->src_start); upper_32_bits 1747 drivers/dma/xilinx/xilinx_dma.c hw->src_addr_msb = upper_32_bits(dma_src); upper_32_bits 1748 drivers/dma/xilinx/xilinx_dma.c hw->dest_addr_msb = upper_32_bits(dma_dst); upper_32_bits 91 drivers/firmware/xilinx/zynqmp.c ret_payload[1] = upper_32_bits(res.a0); upper_32_bits 93 drivers/firmware/xilinx/zynqmp.c ret_payload[3] = upper_32_bits(res.a1); upper_32_bits 121 drivers/firmware/xilinx/zynqmp.c ret_payload[1] = upper_32_bits(res.a0); upper_32_bits 123 drivers/firmware/xilinx/zynqmp.c ret_payload[3] = upper_32_bits(res.a1); upper_32_bits 400 drivers/firmware/xilinx/zynqmp.c upper_32_bits(rate), upper_32_bits 559 drivers/firmware/xilinx/zynqmp.c upper_32_bits(address), size, flags, NULL); upper_32_bits 179 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c upper_32_bits(data64)); upper_32_bits 431 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c upper_32_bits(guessed_wptr)); upper_32_bits 435 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c upper_32_bits((uint64_t)wptr)); upper_32_bits 537 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c upper_32_bits(data64)); upper_32_bits 607 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c high = upper_32_bits(queue_address >> 8); upper_32_bits 935 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 938 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); upper_32_bits 513 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c high = upper_32_bits(queue_address >> 8); upper_32_bits 506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c high = upper_32_bits(queue_address >> 8); upper_32_bits 332 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c upper_32_bits(guessed_wptr)); upper_32_bits 336 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c upper_32_bits((uintptr_t)wptr)); upper_32_bits 436 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c upper_32_bits(data64)); upper_32_bits 503 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c high = upper_32_bits(queue_address >> 8); upper_32_bits 200 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); upper_32_bits 209 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); upper_32_bits 308 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); upper_32_bits 312 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); upper_32_bits 397 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); upper_32_bits 401 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); upper_32_bits 582 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); upper_32_bits 586 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); upper_32_bits 1007 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); upper_32_bits 30 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h WREG32((reg) + 1, upper_32_bits(v)); \ upper_32_bits 831 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c upper_32_bits(start)); upper_32_bits 480 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 658 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr)); upper_32_bits 1043 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1061 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 593 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 646 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 698 drivers/gpu/drm/amd/amdgpu/atom.c ctx->ctx->divmul[1] = upper_32_bits(val64); upper_32_bits 819 drivers/gpu/drm/amd/amdgpu/atom.c ctx->ctx->divmul[1] = upper_32_bits(val64); upper_32_bits 137 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); upper_32_bits 235 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); upper_32_bits 283 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 291 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 292 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 478 drivers/gpu/drm/amd/amdgpu/cik_sdma.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 636 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 689 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 739 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 741 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 764 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 768 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 792 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 794 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 796 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 843 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 1322 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); upper_32_bits 1324 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 1344 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 139 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); upper_32_bits 252 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c upper_32_bits(crtc_base)); upper_32_bits 2009 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c upper_32_bits(fb_location)); upper_32_bits 2011 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c upper_32_bits(fb_location)); upper_32_bits 2300 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c upper_32_bits(amdgpu_crtc->cursor_addr)); upper_32_bits 270 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c upper_32_bits(crtc_base)); upper_32_bits 2051 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c upper_32_bits(fb_location)); upper_32_bits 2053 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c upper_32_bits(fb_location)); upper_32_bits 2379 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c upper_32_bits(amdgpu_crtc->cursor_addr)); upper_32_bits 204 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c upper_32_bits(crtc_base)); upper_32_bits 1947 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c upper_32_bits(fb_location)); upper_32_bits 1949 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c upper_32_bits(fb_location)); upper_32_bits 2190 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c upper_32_bits(amdgpu_crtc->cursor_addr)); upper_32_bits 197 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c upper_32_bits(crtc_base)); upper_32_bits 1921 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c upper_32_bits(fb_location)); upper_32_bits 1923 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c upper_32_bits(fb_location)); upper_32_bits 2201 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c upper_32_bits(amdgpu_crtc->cursor_addr)); upper_32_bits 263 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ upper_32_bits 292 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); upper_32_bits 294 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); upper_32_bits 315 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); upper_32_bits 340 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); upper_32_bits 342 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); upper_32_bits 2223 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); upper_32_bits 2275 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(addr)); upper_32_bits 2312 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(addr)); upper_32_bits 2349 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(addr)); upper_32_bits 2386 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(addr)); upper_32_bits 2525 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); upper_32_bits 2594 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); upper_32_bits 2663 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); upper_32_bits 2842 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); upper_32_bits 2847 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & upper_32_bits 2854 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 2861 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 2879 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); upper_32_bits 2883 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & upper_32_bits 2889 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 2896 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 2985 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); upper_32_bits 3032 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); upper_32_bits 3060 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 3066 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 3071 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 3277 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); upper_32_bits 3314 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); upper_32_bits 3324 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 3345 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 3350 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 4389 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); upper_32_bits 4485 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 4520 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 4556 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 4558 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 4569 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c upper_32_bits(addr), seq, 0xffffffff, 4); upper_32_bits 4598 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 4659 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); upper_32_bits 4737 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(csa_addr + upper_32_bits 4761 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); upper_32_bits 4771 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(csa_addr + upper_32_bits 4802 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + upper_32_bits 1856 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 1860 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 1890 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 2126 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 2212 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 2231 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 2318 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 2419 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); upper_32_bits 2196 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 2199 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(seq - 1)); upper_32_bits 2208 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 2211 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 2238 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 2240 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 2285 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 2319 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 2637 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 2647 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 2889 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); upper_32_bits 2955 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); upper_32_bits 2964 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 2991 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 2997 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 3222 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 3887 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); upper_32_bits 898 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ib.ptr[3] = upper_32_bits(gpu_addr); upper_32_bits 1610 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); upper_32_bits 1636 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); upper_32_bits 1662 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); upper_32_bits 4324 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 4328 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); upper_32_bits 4334 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 4405 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ upper_32_bits 4426 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); upper_32_bits 4428 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); upper_32_bits 4473 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr upper_32_bits 4477 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); upper_32_bits 4496 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); upper_32_bits 4506 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 4527 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 4532 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 6143 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 6177 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 6197 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 6200 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(seq - 1)); upper_32_bits 6211 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 6214 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 6229 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 6389 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 6391 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 6405 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 6464 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); upper_32_bits 6497 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + upper_32_bits 7227 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr)); upper_32_bits 7244 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr); upper_32_bits 7249 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr); upper_32_bits 7260 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, upper_32_bits(de_payload_addr)); upper_32_bits 901 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ib.ptr[3] = upper_32_bits(gpu_addr); upper_32_bits 2104 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); upper_32_bits 2112 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); upper_32_bits 2120 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); upper_32_bits 3225 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); upper_32_bits 3230 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); upper_32_bits 3234 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); upper_32_bits 3241 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 3311 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); upper_32_bits 3374 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ upper_32_bits 3398 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); upper_32_bits 3400 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); upper_32_bits 3433 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c upper_32_bits(ring->mqd_gpu_addr upper_32_bits 3438 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); upper_32_bits 3475 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); upper_32_bits 3485 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 3506 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 3511 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 4322 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); upper_32_bits 4350 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); upper_32_bits 4978 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); upper_32_bits 5040 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 5075 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 5107 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 5109 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 5120 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c lower_32_bits(addr), upper_32_bits(addr), upper_32_bits 5279 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 5314 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); upper_32_bits 5327 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); upper_32_bits 5336 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); upper_32_bits 5385 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); upper_32_bits 5417 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + upper_32_bits 49 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c offset * vmid, upper_32_bits(page_table_base)); upper_32_bits 247 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 58 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c upper_32_bits(value)); upper_32_bits 235 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 394 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c upper_32_bits(pd_addr)); upper_32_bits 593 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c upper_32_bits(pd_addr)); upper_32_bits 139 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); upper_32_bits 255 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c upper_32_bits(adev->mes.ucode_fw_gpu_addr)); upper_32_bits 264 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c upper_32_bits(adev->mes.data_fw_gpu_addr)); upper_32_bits 69 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c offset * vmid, upper_32_bits(page_table_base)); upper_32_bits 279 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 42 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c upper_32_bits(value)); upper_32_bits 225 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 73 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c upper_32_bits(value)); upper_32_bits 331 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c upper_32_bits(adev->vm_manager.max_pfn - 1)); upper_32_bits 146 drivers/gpu/drm/amd/amdgpu/navi10_ih.c upper_32_bits(ih->wptr_addr) & 0xFFFF); upper_32_bits 137 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c upper_32_bits(adev->doorbell.base)); upper_32_bits 107 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c upper_32_bits(adev->doorbell.base)); upper_32_bits 170 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c upper_32_bits(adev->doorbell.base)); upper_32_bits 133 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 226 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); upper_32_bits 228 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); upper_32_bits 448 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 467 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 546 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); upper_32_bits 548 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); upper_32_bits 251 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 270 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 376 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); upper_32_bits 378 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); upper_32_bits 316 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 337 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); upper_32_bits 452 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); upper_32_bits 454 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); upper_32_bits 264 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 315 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 323 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 324 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 456 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 571 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 624 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 678 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 680 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 703 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 707 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 731 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 733 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 735 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 782 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 1210 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); upper_32_bits 1212 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 1232 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 438 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 489 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 497 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 498 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 695 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 721 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 843 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 896 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 949 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 951 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 974 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 978 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 1002 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1004 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 1006 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 1053 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 1648 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); upper_32_bits 1650 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 1670 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 600 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 613 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 617 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 668 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(wptr)); upper_32_bits 707 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 779 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 789 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 790 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 1006 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 1042 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 1096 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 1133 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 1396 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 1449 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 1504 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 1506 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1531 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1535 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 1560 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1562 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 1564 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 1609 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(addr) & 0xffffffff, upper_32_bits 2470 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); upper_32_bits 2472 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 2492 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 238 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); upper_32_bits 334 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 337 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); upper_32_bits 348 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 352 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); upper_32_bits 411 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 414 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); upper_32_bits 467 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 478 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 479 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 662 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(wptr_gpu_addr)); upper_32_bits 673 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); upper_32_bits 914 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 981 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 1041 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 1043 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1068 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1072 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 1097 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 1099 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 1101 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 1149 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); upper_32_bits 1689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); upper_32_bits 1691 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 1711 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); upper_32_bits 76 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); upper_32_bits 98 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); upper_32_bits 105 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); upper_32_bits 106 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, upper_32_bits(seq)); upper_32_bits 159 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); upper_32_bits 225 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); upper_32_bits 276 drivers/gpu/drm/amd/amdgpu/si_dma.c ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; upper_32_bits 324 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 325 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; upper_32_bits 347 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 350 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 388 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 390 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(flags); upper_32_bits 392 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 429 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ upper_32_bits 784 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; upper_32_bits 785 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; upper_32_bits 807 drivers/gpu/drm/amd/amdgpu/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; upper_32_bits 83 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); upper_32_bits 139 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); upper_32_bits 354 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | upper_32_bits 456 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 262 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c upper_32_bits(adev->uvd.inst->gpu_addr)); upper_32_bits 407 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 413 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 473 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 535 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 231 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 294 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 588 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c upper_32_bits(adev->uvd.inst->gpu_addr)); upper_32_bits 824 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 830 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 845 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 852 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 906 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 933 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1004 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1027 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1065 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1093 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 239 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 301 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ib->ptr[ib->length_dw++] = upper_32_bits(addr); upper_32_bits 674 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr)); upper_32_bits 685 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); upper_32_bits 692 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); upper_32_bits 721 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); upper_32_bits 816 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr)); upper_32_bits 828 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); upper_32_bits 835 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); upper_32_bits 902 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); upper_32_bits 1075 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 1081 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1097 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 1104 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 1170 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 1202 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1307 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1331 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 247 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 254 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 284 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 291 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 298 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); upper_32_bits 844 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 867 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 164 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr)); upper_32_bits 236 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 345 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); upper_32_bits 353 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); upper_32_bits 361 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr)); upper_32_bits 959 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 970 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 311 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr)); upper_32_bits 323 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset)); upper_32_bits 331 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); upper_32_bits 381 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); upper_32_bits 393 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); upper_32_bits 404 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), upper_32_bits 917 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 923 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 941 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 948 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 956 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); upper_32_bits 1090 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 1096 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1262 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 1269 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 1328 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1492 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 1533 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1658 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1686 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1830 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1854 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1903 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1915 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); upper_32_bits 2042 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c val = upper_32_bits(ring->gpu_addr); upper_32_bits 380 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr)); upper_32_bits 392 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset)); upper_32_bits 400 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); upper_32_bits 439 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); upper_32_bits 460 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); upper_32_bits 480 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); upper_32_bits 718 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1034 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c (upper_32_bits(ring->gpu_addr) >> 2)); upper_32_bits 1040 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1198 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c upper_32_bits(ring->gpu_addr)); upper_32_bits 1211 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 1218 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 1363 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 1370 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 1556 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 1594 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1733 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1761 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1906 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(addr)); upper_32_bits 1957 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 1969 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); upper_32_bits 397 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c upper_32_bits(adev->vcn.inst[i].gpu_addr)); upper_32_bits 408 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); upper_32_bits 416 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); upper_32_bits 664 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c upper_32_bits(ring->gpu_addr)); upper_32_bits 859 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c upper_32_bits(ring->gpu_addr)); upper_32_bits 871 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 878 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 265 drivers/gpu/drm/amd/amdgpu/vega10_ih.c upper_32_bits(ih->wptr_addr) & 0xFFFF); upper_32_bits 872 drivers/gpu/drm/amd/amdkfd/kfd_crat.c sub_type_hdr->length_high = upper_32_bits(mem_in_bytes); upper_32_bits 1054 drivers/gpu/drm/amd/amdkfd/kfd_crat.c sub_type_hdr->length_high = upper_32_bits(size); upper_32_bits 97 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c upper_32_bits(qpd->tba_addr >> 8); upper_32_bits 99 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); upper_32_bits 103 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); upper_32_bits 108 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c upper_32_bits(vm_page_table_base_addr); upper_32_bits 146 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->ib_base_hi = upper_32_bits(ib); upper_32_bits 198 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c upper_32_bits(q->gart_mqd_addr); upper_32_bits 204 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c upper_32_bits((uint64_t)q->properties.write_ptr); upper_32_bits 293 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->addr_hi = upper_32_bits((uint64_t)fence_address); upper_32_bits 295 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->data_hi = upper_32_bits((uint64_t)fence_value); upper_32_bits 325 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c packet->address_hi = upper_32_bits(gpu_addr); upper_32_bits 94 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8); upper_32_bits 96 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); upper_32_bits 99 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); upper_32_bits 104 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c upper_32_bits(vm_page_table_base_addr); upper_32_bits 142 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->ib_base_hi = upper_32_bits(ib); upper_32_bits 167 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->gws_mask_hi = upper_32_bits(res->gws_mask); upper_32_bits 170 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->queue_mask_hi = upper_32_bits(res->queue_mask); upper_32_bits 231 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c upper_32_bits(q->gart_mqd_addr); upper_32_bits 237 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c upper_32_bits((uint64_t)q->properties.write_ptr); upper_32_bits 336 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->addr_hi = upper_32_bits((uint64_t)fence_address); upper_32_bits 338 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->data_hi = upper_32_bits((uint64_t)fence_value); upper_32_bits 366 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c packet->address_hi = upper_32_bits(gpu_addr); upper_32_bits 110 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); upper_32_bits 149 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->bitfields3.ib_base_hi = upper_32_bits(ib); upper_32_bits 174 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->gws_mask_hi = upper_32_bits(res->gws_mask); upper_32_bits 177 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->queue_mask_hi = upper_32_bits(res->queue_mask); upper_32_bits 229 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c upper_32_bits(q->gart_mqd_addr); upper_32_bits 235 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c upper_32_bits((uint64_t)q->properties.write_ptr); upper_32_bits 323 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->addr_hi = upper_32_bits((uint64_t)fence_address); upper_32_bits 325 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->data_hi = upper_32_bits((uint64_t)fence_value); upper_32_bits 353 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c packet->address_hi = upper_32_bits(gpu_addr); upper_32_bits 116 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_mqd_base_addr_hi = upper_32_bits(addr); upper_32_bits 207 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); upper_32_bits 209 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 248 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); upper_32_bits 250 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 330 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); upper_32_bits 332 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 128 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_mqd_base_addr_hi = upper_32_bits(addr); upper_32_bits 148 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c upper_32_bits(q->ctx_save_restore_area_address); upper_32_bits 188 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); upper_32_bits 191 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 193 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); upper_32_bits 215 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c upper_32_bits(q->eop_ring_buffer_address >> 8); upper_32_bits 362 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); upper_32_bits 364 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 147 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_mqd_base_addr_hi = upper_32_bits(addr); upper_32_bits 169 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c upper_32_bits(q->ctx_save_restore_area_address); upper_32_bits 206 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); upper_32_bits 209 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 211 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); upper_32_bits 235 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c upper_32_bits(q->eop_ring_buffer_address >> 8); upper_32_bits 380 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); upper_32_bits 382 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 116 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_mqd_base_addr_hi = upper_32_bits(addr); upper_32_bits 130 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); upper_32_bits 132 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); upper_32_bits 143 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c upper_32_bits(q->ctx_save_restore_area_address); upper_32_bits 184 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); upper_32_bits 187 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 189 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); upper_32_bits 216 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c upper_32_bits(q->eop_ring_buffer_address >> 8); upper_32_bits 361 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); upper_32_bits 363 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); upper_32_bits 1085 drivers/gpu/drm/amd/amdkfd/kfd_topology.c buf[6] = upper_32_bits(local_mem_size); upper_32_bits 2757 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c address->grph.meta_addr.high_part = upper_32_bits(dcc_address); upper_32_bits 2792 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c address->grph.addr.high_part = upper_32_bits(afb->address); upper_32_bits 2816 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c upper_32_bits(afb->address); upper_32_bits 2820 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c upper_32_bits(chroma_addr); upper_32_bits 5456 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c attributes.address.high_part = upper_32_bits(address); upper_32_bits 161 drivers/gpu/drm/amd/powerplay/amd_powerplay.c upper_32_bits((unsigned long)cpu_ptr), upper_32_bits 163 drivers/gpu/drm/amd/powerplay/amd_powerplay.c upper_32_bits(gpu_addr), upper_32_bits 451 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c upper_32_bits(table->mc_address)); upper_32_bits 688 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_high = (uint32_t)upper_32_bits(address); upper_32_bits 703 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_high = (uint32_t)upper_32_bits(address); upper_32_bits 824 drivers/gpu/drm/amd/powerplay/smu_v11_0.c upper_32_bits(tool_table->mc_address)); upper_32_bits 131 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits 166 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits 319 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c entry->image_addr_high = upper_32_bits(info.mc_addr); upper_32_bits 358 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c upper_32_bits(smu_data->smu_buffer.mc_addr)); upper_32_bits 426 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr)); upper_32_bits 212 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c reg_data = upper_32_bits(info.mc_addr) & upper_32_bits 352 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c task->addr.high = upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr); upper_32_bits 389 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c task->addr.high = upper_32_bits(smu8_smu->driver_buffer[i].mc_addr); upper_32_bits 617 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr)); upper_32_bits 644 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr)); upper_32_bits 678 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c upper_32_bits(smu8_smu->toc_buffer.mc_addr)); upper_32_bits 52 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits 86 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); upper_32_bits 138 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); upper_32_bits 55 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, upper_32_bits 100 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, upper_32_bits 194 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr))) upper_32_bits 178 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0, upper_32_bits 224 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0, upper_32_bits 252 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0, upper_32_bits 278 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0, upper_32_bits 368 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr)); upper_32_bits 386 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c upper_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr))) == 0, upper_32_bits 28 drivers/gpu/drm/arm/display/include/malidp_io.h writel(upper_32_bits(v), (base + (offset >> 2) + 1)); upper_32_bits 225 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_P1_PTR_HIGH, upper_32_bits(addr)); upper_32_bits 524 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); upper_32_bits 529 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); upper_32_bits 861 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); upper_32_bits 866 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); upper_32_bits 746 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4); upper_32_bits 104 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c entry |= (upper_32_bits(paddr) & 0xff) << 4; upper_32_bits 198 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c upper_32_bits(context->global->v2.pta_dma)); upper_32_bits 207 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c upper_32_bits(context->global->bad_page_dma)) | upper_32_bits 209 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c upper_32_bits(context->global->bad_page_dma))); upper_32_bits 1003 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = upper_32_bits(pd_daddr); upper_32_bits 1021 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = upper_32_bits(pd_daddr); upper_32_bits 1056 drivers/gpu/drm/i915/gem/i915_gem_context.c if (upper_32_bits(args->value)) upper_32_bits 1124 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = upper_32_bits(offset); upper_32_bits 1293 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *batch++ = upper_32_bits(addr); upper_32_bits 1300 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *batch++ = upper_32_bits(addr); upper_32_bits 1301 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *batch++ = upper_32_bits(target_offset); upper_32_bits 1305 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *batch++ = upper_32_bits(addr); upper_32_bits 1307 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *batch++ = upper_32_bits(target_offset); upper_32_bits 61 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c *cmd++ = upper_32_bits(offset); upper_32_bits 245 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c *cmd++ = upper_32_bits(dst_offset); upper_32_bits 249 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c *cmd++ = upper_32_bits(src_offset); upper_32_bits 256 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c *cmd++ = upper_32_bits(dst_offset); upper_32_bits 260 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c *cmd++ = upper_32_bits(src_offset); upper_32_bits 215 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); upper_32_bits 601 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *cmd++ = upper_32_bits(vma->node.start); upper_32_bits 1160 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c upper_32_bits(offset), lower_32_bits(offset)); upper_32_bits 1190 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *cmd++ = upper_32_bits(offset); upper_32_bits 1281 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *cmd++ = upper_32_bits(offset); upper_32_bits 1444 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c upper_32_bits(offset), upper_32_bits 69 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c *cmd++ = upper_32_bits(offset); upper_32_bits 1227 drivers/gpu/drm/i915/gt/intel_engine_cs.c upper_32_bits(addr), lower_32_bits(addr)); upper_32_bits 1230 drivers/gpu/drm/i915/gt/intel_engine_cs.c upper_32_bits(addr), lower_32_bits(addr)); upper_32_bits 1238 drivers/gpu/drm/i915/gt/intel_engine_cs.c upper_32_bits(addr), lower_32_bits(addr)); upper_32_bits 1329 drivers/gpu/drm/i915/gt/intel_engine_cs.c rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, upper_32_bits 153 drivers/gpu/drm/i915/gt/intel_gt.c upper_32_bits(fault_addr), upper_32_bits 702 drivers/gpu/drm/i915/gt/intel_lrc.c writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); upper_32_bits 704 drivers/gpu/drm/i915/gt/intel_lrc.c writel(upper_32_bits(desc), execlists->submit_reg); upper_32_bits 1939 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = upper_32_bits(pd_daddr); upper_32_bits 2694 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = upper_32_bits(offset); upper_32_bits 2716 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = upper_32_bits(offset); upper_32_bits 52 drivers/gpu/drm/i915/gt/intel_lrc_reg.h (reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \ upper_32_bits 59 drivers/gpu/drm/i915/gt/intel_lrc_reg.h (reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \ upper_32_bits 104 drivers/gpu/drm/i915/gt/intel_renderstate.c s = upper_32_bits(r); upper_32_bits 193 drivers/gpu/drm/i915/gt/selftest_hangcheck.c *batch++ = upper_32_bits(hws_address(hws, rq)); upper_32_bits 203 drivers/gpu/drm/i915/gt/selftest_hangcheck.c *batch++ = upper_32_bits(vma->node.start); upper_32_bits 513 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = upper_32_bits(addr); upper_32_bits 526 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = upper_32_bits(addr + sizeof(u32) * idx); upper_32_bits 539 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = upper_32_bits(addr + sizeof(u32) * idx); upper_32_bits 548 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = upper_32_bits(addr); upper_32_bits 795 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = upper_32_bits(offset); upper_32_bits 404 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c GEM_BUG_ON(upper_32_bits(node->start)); upper_32_bits 405 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c GEM_BUG_ON(upper_32_bits(node->start + node->size - 1)); upper_32_bits 456 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000); upper_32_bits 458 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset)); upper_32_bits 150 drivers/gpu/drm/i915/gvt/aperture_gm.c I915_WRITE(fence_reg_hi, upper_32_bits(value)); upper_32_bits 196 drivers/gpu/drm/i915/i915_drv.c upper_32_bits(dev_priv->mch_res.start)); upper_32_bits 113 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); upper_32_bits 847 drivers/gpu/drm/i915/i915_gem_gtt.c I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); upper_32_bits 856 drivers/gpu/drm/i915/i915_gem_gtt.c I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); upper_32_bits 2920 drivers/gpu/drm/i915/i915_gem_gtt.c I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); upper_32_bits 2956 drivers/gpu/drm/i915/i915_gem_gtt.c I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); upper_32_bits 505 drivers/gpu/drm/i915/i915_gpu_error.c upper_32_bits(start), lower_32_bits(start), upper_32_bits 506 drivers/gpu/drm/i915/i915_gpu_error.c upper_32_bits(end), lower_32_bits(end)); upper_32_bits 515 drivers/gpu/drm/i915/i915_gpu_error.c err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), upper_32_bits 573 drivers/gpu/drm/i915/i915_gpu_error.c upper_32_bits(obj->gtt_offset), upper_32_bits 751 drivers/gpu/drm/i915/i915_gpu_error.c upper_32_bits(obj->gtt_offset), upper_32_bits 1296 drivers/gpu/drm/i915/i915_perf.c upper_32_bits(ce->lrc_desc); upper_32_bits 1307 drivers/gpu/drm/i915/i915_perf.c stream->specific_ctx_id = upper_32_bits(ce->lrc_desc); upper_32_bits 624 drivers/gpu/drm/i915/i915_vma.c if (upper_32_bits(end - 1) && upper_32_bits 218 drivers/gpu/drm/i915/i915_vma.h GEM_BUG_ON(upper_32_bits(vma->node.start)); upper_32_bits 219 drivers/gpu/drm/i915/i915_vma.h GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); upper_32_bits 49 drivers/gpu/drm/i915/selftests/i915_random.h return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro)); upper_32_bits 794 drivers/gpu/drm/i915/selftests/i915_request.c *cmd++ = upper_32_bits(vma->node.start); upper_32_bits 137 drivers/gpu/drm/i915/selftests/igt_spinner.c *batch++ = upper_32_bits(hws_address(hws, rq)); upper_32_bits 144 drivers/gpu/drm/i915/selftests/igt_spinner.c *batch++ = upper_32_bits(vma->node.start); upper_32_bits 12 drivers/gpu/drm/lib/drm_random.c return upper_32_bits((u64)prandom_u32_state(state) * ep_ro); upper_32_bits 131 drivers/gpu/drm/msm/adreno/a5xx_gpu.c OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); upper_32_bits 157 drivers/gpu/drm/msm/adreno/a5xx_gpu.c OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); upper_32_bits 191 drivers/gpu/drm/msm/adreno/a5xx_gpu.c OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); upper_32_bits 384 drivers/gpu/drm/msm/adreno/a5xx_gpu.c OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id])); upper_32_bits 236 drivers/gpu/drm/msm/adreno/a5xx_power.c OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); upper_32_bits 79 drivers/gpu/drm/msm/adreno/a6xx_gpu.c OUT_RING(ring, upper_32_bits(iova)); upper_32_bits 122 drivers/gpu/drm/msm/adreno/a6xx_gpu.c OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); upper_32_bits 144 drivers/gpu/drm/msm/adreno/a6xx_gpu.c OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); upper_32_bits 363 drivers/gpu/drm/msm/adreno/adreno_gpu.h adreno_gpu_write(gpu, hi, upper_32_bits(data)); upper_32_bits 260 drivers/gpu/drm/msm/msm_gpu.h msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); upper_32_bits 84 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h nvkm_wo32((o), __a + 4, upper_32_bits(__d)); \ upper_32_bits 22 drivers/gpu/drm/nouveau/include/nvkm/core/os.h iowrite32_native(upper_32_bits(_v), &_p[1]); \ upper_32_bits 758 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); upper_32_bits 760 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); upper_32_bits 801 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(src_offset)); upper_32_bits 803 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(dst_offset)); upper_32_bits 839 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(dst_offset)); upper_32_bits 842 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(src_offset)); upper_32_bits 878 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(src_offset)); upper_32_bits 880 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(dst_offset)); upper_32_bits 905 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); upper_32_bits 907 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); upper_32_bits 924 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); upper_32_bits 926 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); upper_32_bits 1000 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(src_offset)); upper_32_bits 1001 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, upper_32_bits(dst_offset)); upper_32_bits 94 drivers/gpu/drm/nouveau/nouveau_dma.c nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); upper_32_bits 459 drivers/gpu/drm/nouveau/nouveau_dmem.c OUT_RING (chan, upper_32_bits(src_addr)); upper_32_bits 461 drivers/gpu/drm/nouveau/nouveau_dmem.c OUT_RING (chan, upper_32_bits(dst_addr)); upper_32_bits 243 drivers/gpu/drm/nouveau/nv50_fbcon.c OUT_RING(chan, upper_32_bits(fb->vma->addr)); upper_32_bits 252 drivers/gpu/drm/nouveau/nv50_fbcon.c OUT_RING(chan, upper_32_bits(fb->vma->addr)); upper_32_bits 40 drivers/gpu/drm/nouveau/nv84_fence.c OUT_RING (chan, upper_32_bits(virtual)); upper_32_bits 58 drivers/gpu/drm/nouveau/nv84_fence.c OUT_RING (chan, upper_32_bits(virtual)); upper_32_bits 243 drivers/gpu/drm/nouveau/nvc0_fbcon.c OUT_RING (chan, upper_32_bits(fb->vma->addr)); upper_32_bits 254 drivers/gpu/drm/nouveau/nvc0_fbcon.c OUT_RING (chan, upper_32_bits(fb->vma->addr)); upper_32_bits 37 drivers/gpu/drm/nouveau/nvc0_fence.c OUT_RING (chan, upper_32_bits(virtual)); upper_32_bits 53 drivers/gpu/drm/nouveau/nvc0_fence.c OUT_RING (chan, upper_32_bits(virtual)); upper_32_bits 179 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push)); upper_32_bits 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push)); upper_32_bits 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | upper_32_bits 55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c upper_32_bits(dmaobj->base.start)); upper_32_bits 52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start)); upper_32_bits 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit)); upper_32_bits 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | upper_32_bits 55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c upper_32_bits(dmaobj->base.start)); upper_32_bits 151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | upper_32_bits 152 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c upper_32_bits(start)); upper_32_bits 120 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | upper_32_bits 121 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c upper_32_bits(start)); upper_32_bits 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); upper_32_bits 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); upper_32_bits 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); upper_32_bits 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); upper_32_bits 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); upper_32_bits 117 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); upper_32_bits 275 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); upper_32_bits 279 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | upper_32_bits 135 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u32 datahi = upper_32_bits(addr); upper_32_bits 310 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); upper_32_bits 314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | upper_32_bits 103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(inst, 0x214, upper_32_bits(addr)); upper_32_bits 204 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem)); upper_32_bits 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) | upper_32_bits 218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd)); upper_32_bits 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); upper_32_bits 40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); upper_32_bits 42 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); upper_32_bits 40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr)); upper_32_bits 1513 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wo32(inst, 0x0214, upper_32_bits(ctx->addr + CB_RESERVED)); upper_32_bits 344 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr)); upper_32_bits 49 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset)); upper_32_bits 353 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c cmd.wpr_hi = upper_32_bits(queue->wpr_addr); upper_32_bits 159 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | upper_32_bits 160 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c upper_32_bits(start)); upper_32_bits 195 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | upper_32_bits 196 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c upper_32_bits(start)); upper_32_bits 46 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c nvkm_wr32(device, 0x002a74, upper_32_bits(buffer->addr)); upper_32_bits 99 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_wr32(device, 0x100e28 + foff, upper_32_bits(buffer->addr)); upper_32_bits 54 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_wr32(device, 0xb83004 + foff, upper_32_bits(buffer->addr)); upper_32_bits 462 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c nvkm_wr32(device, 0x100cec, upper_32_bits(addr)); upper_32_bits 57 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c nvkm_wo32(inst, 0x29c, upper_32_bits(mask)); upper_32_bits 90 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c desc->code_dma_base1 = upper_32_bits(addr_code); upper_32_bits 95 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c desc->data_dma_base1 = upper_32_bits(addr_data); upper_32_bits 1158 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c desc->code_dma_base1 = upper_32_bits(addr_code); upper_32_bits 1163 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c desc->data_dma_base1 = upper_32_bits(addr_data); upper_32_bits 1166 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c desc->overlay_dma_base1 = upper_32_bits(addr_code); upper_32_bits 59 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h ret.hi = upper_32_bits(u); upper_32_bits 32 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c u32 hi = upper_32_bits(time); upper_32_bits 1397 drivers/gpu/drm/radeon/atombios_crtc.c upper_32_bits(fb_location)); upper_32_bits 1399 drivers/gpu/drm/radeon/atombios_crtc.c upper_32_bits(fb_location)); upper_32_bits 1613 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); upper_32_bits 1614 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); upper_32_bits 1616 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); upper_32_bits 1617 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); upper_32_bits 3569 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | upper_32_bits 3581 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); upper_32_bits 3609 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(addr)); upper_32_bits 3635 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); upper_32_bits 3697 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(src_offset)); upper_32_bits 3699 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(dst_offset)); upper_32_bits 3758 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); upper_32_bits 3769 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 4097 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); upper_32_bits 4110 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); upper_32_bits 4555 drivers/gpu/drm/radeon/cik.c WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); upper_32_bits 4656 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); upper_32_bits 4667 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); upper_32_bits 4695 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 4707 drivers/gpu/drm/radeon/cik.c upper_32_bits(wb_gpu_addr) & 0xffff; upper_32_bits 6633 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); upper_32_bits 6995 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); upper_32_bits 146 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); upper_32_bits 156 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); upper_32_bits 209 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(addr)); upper_32_bits 238 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(addr)); upper_32_bits 401 drivers/gpu/drm/radeon/cik_sdma.c upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); upper_32_bits 615 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(src_offset)); upper_32_bits 617 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(dst_offset)); upper_32_bits 671 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(gpu_addr)); upper_32_bits 729 drivers/gpu/drm/radeon/cik_sdma.c ib.ptr[2] = upper_32_bits(gpu_addr); upper_32_bits 818 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(src); upper_32_bits 820 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 859 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 872 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 912 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe); upper_32_bits 916 drivers/gpu/drm/radeon/cik_sdma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 1427 drivers/gpu/drm/radeon/evergreen.c upper_32_bits(crtc_base)); upper_32_bits 2770 drivers/gpu/drm/radeon/evergreen.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 2772 drivers/gpu/drm/radeon/evergreen.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 2780 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); upper_32_bits 2949 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); upper_32_bits 2960 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); upper_32_bits 3104 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); upper_32_bits 4287 drivers/gpu/drm/radeon/evergreen.c dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); upper_32_bits 4294 drivers/gpu/drm/radeon/evergreen.c data = upper_32_bits(reg_list_mc_addr); upper_32_bits 1824 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 1870 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] = upper_32_bits(offset) & 0xff; upper_32_bits 1905 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] = upper_32_bits(offset) & 0xff; upper_32_bits 1933 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2026 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; upper_32_bits 2106 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2167 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 2205 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] = upper_32_bits(offset) & 0xff; upper_32_bits 2253 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2275 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 2297 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 2427 drivers/gpu/drm/radeon/evergreen_cs.c (upper_32_bits(offset64) & 0xff); upper_32_bits 2507 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2526 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] = upper_32_bits(offset) & 0xff; upper_32_bits 2555 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] = upper_32_bits(offset) & 0xff; upper_32_bits 2580 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2607 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] = upper_32_bits(offset) & 0xff; upper_32_bits 2656 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2841 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2885 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2886 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2901 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2907 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2944 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2945 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2956 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2958 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2994 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2995 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; upper_32_bits 2996 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3034 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3050 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 3054 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3096 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3112 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 3118 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3183 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 3205 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; upper_32_bits 49 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); upper_32_bits 79 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); upper_32_bits 90 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); upper_32_bits 143 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); upper_32_bits 144 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); upper_32_bits 1420 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); upper_32_bits 1450 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); upper_32_bits 1704 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); upper_32_bits 135 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); upper_32_bits 146 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); upper_32_bits 223 drivers/gpu/drm/radeon/ni_dma.c upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); upper_32_bits 331 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 332 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; upper_32_bits 371 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 383 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 423 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 427 drivers/gpu/drm/radeon/ni_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 3859 drivers/gpu/drm/radeon/r100.c upper_32_bits(rdev->mc.agp_base) & 0xff); upper_32_bits 110 drivers/gpu/drm/radeon/r300.c ((upper_32_bits(addr) & 0xff) << 24); upper_32_bits 1348 drivers/gpu/drm/radeon/r300.c upper_32_bits(rdev->mc.agp_base) & 0xff); upper_32_bits 157 drivers/gpu/drm/radeon/r520.c S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); upper_32_bits 2749 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); upper_32_bits 2888 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); upper_32_bits 2938 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); upper_32_bits 2998 drivers/gpu/drm/radeon/r600.c tmp = upper_32_bits(src_offset) & 0xff; upper_32_bits 3005 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); upper_32_bits 3384 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); upper_32_bits 3395 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); upper_32_bits 3722 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); upper_32_bits 1678 drivers/gpu/drm/radeon/r600_cs.c ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 1719 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] = upper_32_bits(offset) & 0xff; upper_32_bits 1771 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 1815 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 1845 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] = upper_32_bits(offset) & 0xff; upper_32_bits 1883 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 1905 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); upper_32_bits 2012 drivers/gpu/drm/radeon/r600_cs.c (upper_32_bits(offset64) & 0xff); upper_32_bits 2154 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2173 drivers/gpu/drm/radeon/r600_cs.c ib[idx+4] = upper_32_bits(offset) & 0xff; upper_32_bits 2202 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] = upper_32_bits(offset) & 0xff; upper_32_bits 2227 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] = upper_32_bits(offset) & 0xff; upper_32_bits 2251 drivers/gpu/drm/radeon/r600_cs.c ib[idx+4] = upper_32_bits(offset) & 0xff; upper_32_bits 2418 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2450 drivers/gpu/drm/radeon/r600_cs.c ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2456 drivers/gpu/drm/radeon/r600_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2472 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; upper_32_bits 2473 drivers/gpu/drm/radeon/r600_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2483 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; upper_32_bits 2484 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; upper_32_bits 2517 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; upper_32_bits 144 drivers/gpu/drm/radeon/r600_dma.c upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); upper_32_bits 256 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); upper_32_bits 296 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); upper_32_bits 323 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 361 drivers/gpu/drm/radeon/r600_dma.c ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; upper_32_bits 416 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); upper_32_bits 427 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); upper_32_bits 479 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | upper_32_bits 480 drivers/gpu/drm/radeon/r600_dma.c (upper_32_bits(src_offset) & 0xff))); upper_32_bits 525 drivers/gpu/drm/radeon/r600_dpm.c WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask)); upper_32_bits 100 drivers/gpu/drm/radeon/radeon_cursor.c upper_32_bits(radeon_crtc->cursor_addr)); upper_32_bits 111 drivers/gpu/drm/radeon/radeon_cursor.c upper_32_bits(radeon_crtc->cursor_addr)); upper_32_bits 114 drivers/gpu/drm/radeon/radeon_cursor.c upper_32_bits(radeon_crtc->cursor_addr)); upper_32_bits 383 drivers/gpu/drm/radeon/radeon_vce.c ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy)); upper_32_bits 437 drivers/gpu/drm/radeon/radeon_vce.c ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy)); upper_32_bits 724 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr))); upper_32_bits 743 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr))); upper_32_bits 167 drivers/gpu/drm/radeon/rs400.c tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; upper_32_bits 225 drivers/gpu/drm/radeon/rs400.c ((upper_32_bits(addr) & 0xff) << 4); upper_32_bits 390 drivers/gpu/drm/radeon/rv515.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 392 drivers/gpu/drm/radeon/rv515.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 395 drivers/gpu/drm/radeon/rv515.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 397 drivers/gpu/drm/radeon/rv515.c upper_32_bits(rdev->mc.vram_start)); upper_32_bits 494 drivers/gpu/drm/radeon/rv515.c S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); upper_32_bits 822 drivers/gpu/drm/radeon/rv770.c WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); upper_32_bits 823 drivers/gpu/drm/radeon/rv770.c WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); upper_32_bits 825 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); upper_32_bits 826 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); upper_32_bits 77 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); upper_32_bits 78 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); upper_32_bits 3396 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); upper_32_bits 3429 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); upper_32_bits 3442 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); upper_32_bits 3683 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); upper_32_bits 3714 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); upper_32_bits 3738 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); upper_32_bits 6023 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); upper_32_bits 83 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 84 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; upper_32_bits 122 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 134 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 174 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; upper_32_bits 178 drivers/gpu/drm/radeon/si_dma.c ib->ptr[ib->length_dw++] = upper_32_bits(value); upper_32_bits 266 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); upper_32_bits 267 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); upper_32_bits 364 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | upper_32_bits 50 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, upper_32_bits(addr) & 0xff); upper_32_bits 301 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); upper_32_bits 308 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); upper_32_bits 478 drivers/gpu/drm/tegra/hub.c tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI); upper_32_bits 306 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c val = upper_32_bits(header->handle); upper_32_bits 61 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); upper_32_bits 69 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); upper_32_bits 109 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); upper_32_bits 113 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); upper_32_bits 64 drivers/gpu/host1x/hw/channel_hw.c op3 = upper_32_bits(addr); upper_32_bits 583 drivers/i2c/busses/i2c-ismt.c desc->dptr_high = upper_32_bits(dma_addr); upper_32_bits 12 drivers/infiniband/hw/efa/efa_com_cmd.c *addr_high = upper_32_bits(addr); upper_32_bits 888 drivers/infiniband/hw/hns/hns_roce_hw_v2.c upper_32_bits(dma)); upper_32_bits 896 drivers/infiniband/hw/hns/hns_roce_hw_v2.c upper_32_bits(dma)); upper_32_bits 2234 drivers/infiniband/hw/hns/hns_roce_hw_v2.c upper_32_bits(mr->pbl_ba >> 3)); upper_32_bits 2253 drivers/infiniband/hw/hns/hns_roce_hw_v2.c V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); upper_32_bits 2257 drivers/infiniband/hw/hns/hns_roce_hw_v2.c V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); upper_32_bits 2309 drivers/infiniband/hw/hns/hns_roce_hw_v2.c mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); upper_32_bits 2312 drivers/infiniband/hw/hns/hns_roce_hw_v2.c mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); upper_32_bits 2356 drivers/infiniband/hw/hns/hns_roce_hw_v2.c mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); upper_32_bits 2358 drivers/infiniband/hw/hns/hns_roce_hw_v2.c mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); upper_32_bits 2401 drivers/infiniband/hw/hns/hns_roce_hw_v2.c upper_32_bits(mr->pbl_ba >> 3)); upper_32_bits 397 drivers/infiniband/hw/ocrdma/ocrdma_hw.c q_pa[i].hi = (u32) upper_32_bits(host_pa); upper_32_bits 1303 drivers/infiniband/hw/ocrdma/ocrdma_hw.c mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa); upper_32_bits 1351 drivers/infiniband/hw/ocrdma/ocrdma_hw.c mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa); upper_32_bits 1696 drivers/infiniband/hw/ocrdma/ocrdma_hw.c pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa)); upper_32_bits 1700 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa); upper_32_bits 1990 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->totlen_high = upper_32_bits(hwmr->len); upper_32_bits 1992 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo); upper_32_bits 1994 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va); upper_32_bits 1998 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa); upper_32_bits 2030 drivers/infiniband/hw/ocrdma/ocrdma_hw.c upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa); upper_32_bits 2901 drivers/infiniband/hw/ocrdma/ocrdma_hw.c mqe_sge->pa_hi = (u32) upper_32_bits(pa); upper_32_bits 616 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr); upper_32_bits 841 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c pbe->pa_hi = cpu_to_le32(upper_32_bits(pg_addr)); upper_32_bits 1914 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c sge[i].addr_hi = upper_32_bits(sg_list[i].addr); upper_32_bits 2003 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr); upper_32_bits 2023 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr); upper_32_bits 2066 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c fast_reg->va_hi = upper_32_bits(mr->ibmr.iova); upper_32_bits 2068 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c fast_reg->fbo_hi = upper_32_bits(fbo); upper_32_bits 2078 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr)); upper_32_bits 637 drivers/infiniband/hw/qedr/verbs.c pbe->hi = cpu_to_le32(upper_32_bits(pg_addr)); upper_32_bits 757 drivers/infiniband/hw/qedr/verbs.c params->cq_handle_hi = upper_32_bits((uintptr_t)cq); upper_32_bits 1523 drivers/infiniband/hw/qedr/verbs.c params->qp_handle_async_hi = upper_32_bits((uintptr_t) qp); upper_32_bits 1845 drivers/infiniband/hw/qedr/verbs.c in_params.qp_handle_hi = upper_32_bits((uintptr_t) qp); upper_32_bits 2815 drivers/infiniband/hw/qedr/verbs.c pbe->hi = cpu_to_le32((u32)upper_32_bits(addr)); upper_32_bits 3083 drivers/infiniband/hw/qedr/verbs.c fwqe1->addr.hi = upper_32_bits(mr->ibmr.iova); upper_32_bits 3105 drivers/infiniband/hw/qedr/verbs.c fwqe2->pbl_addr.hi = upper_32_bits(mr->info.pbl_table->pa); upper_32_bits 883 drivers/iommu/amd_iommu.c cmd->data[1] = upper_32_bits(paddr); upper_32_bits 918 drivers/iommu/amd_iommu.c cmd->data[3] = upper_32_bits(address); upper_32_bits 951 drivers/iommu/amd_iommu.c cmd->data[3] = upper_32_bits(address); upper_32_bits 967 drivers/iommu/amd_iommu.c cmd->data[3] = upper_32_bits(address); upper_32_bits 989 drivers/iommu/amd_iommu.c cmd->data[3] = upper_32_bits(address); upper_32_bits 1216 drivers/iommu/dma-iommu.c msg->address_hi = upper_32_bits(msi_page->iova); upper_32_bits 680 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->ppbah, upper_32_bits(ppaact_phys)); upper_32_bits 683 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->pplah, upper_32_bits(ppaact_phys)); upper_32_bits 686 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->spbah, upper_32_bits(spaact_phys)); upper_32_bits 689 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->splah, upper_32_bits(spaact_phys)); upper_32_bits 692 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->obah, upper_32_bits(omt_phys)); upper_32_bits 695 drivers/iommu/fsl_pamu.c out_be32(&pamu_regs->olah, upper_32_bits(omt_phys)); upper_32_bits 947 drivers/iommu/fsl_pamu.c law[i].lawbarh = upper_32_bits(phys); upper_32_bits 722 drivers/iommu/io-pgtable-arm-v7s.c if (WARN_ON(upper_32_bits(iova))) upper_32_bits 629 drivers/iommu/mtk_iommu.c upper_32_bits(data->protect_base); upper_32_bits 99 drivers/irqchip/irq-alpine-msi.c msg->address_hi = upper_32_bits(msg_addr); upper_32_bits 213 drivers/irqchip/irq-armada-370-xp.c msg->address_hi = upper_32_bits(msi_doorbell_addr); upper_32_bits 112 drivers/irqchip/irq-gic-v2m.c msg->address_hi = upper_32_bits(addr); upper_32_bits 1195 drivers/irqchip/irq-gic-v3-its.c msg->address_hi = upper_32_bits(addr); upper_32_bits 147 drivers/irqchip/irq-gic-v3-mbi.c msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); upper_32_bits 207 drivers/irqchip/irq-gic-v3-mbi.c msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); upper_32_bits 89 drivers/irqchip/irq-ls-scfg-msi.c msg->address_hi = upper_32_bits(msi_data->msiir_addr); upper_32_bits 64 drivers/irqchip/irq-mvebu-gicp.c msg[0].address_hi = upper_32_bits(setspi); upper_32_bits 67 drivers/irqchip/irq-mvebu-gicp.c msg[1].address_hi = upper_32_bits(clrspi); upper_32_bits 64 drivers/irqchip/irq-mvebu-odmi.c msg->address_hi = upper_32_bits(addr); upper_32_bits 146 drivers/irqchip/irq-mvebu-sei.c msg->address_hi = upper_32_bits(set); upper_32_bits 531 drivers/mailbox/bcm-pdc-mailbox.c rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 559 drivers/mailbox/bcm-pdc-mailbox.c txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 1040 drivers/mailbox/bcm-pdc-mailbox.c iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), upper_32_bits 1045 drivers/mailbox/bcm-pdc-mailbox.c iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), upper_32_bits 54 drivers/media/pci/pt3/pt3_dma.c iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), upper_32_bits 185 drivers/media/pci/pt3/pt3_dma.c d->next_h = upper_32_bits(desc_addr); upper_32_bits 191 drivers/media/pci/pt3/pt3_dma.c d->addr_h = upper_32_bits(data_addr); upper_32_bits 196 drivers/media/pci/pt3/pt3_dma.c d->next_h = upper_32_bits(desc_addr); upper_32_bits 205 drivers/media/pci/pt3/pt3_dma.c d->next_h = upper_32_bits(desc_addr); upper_32_bits 263 drivers/media/platform/qcom/venus/hfi_cmds.c pkt->time_stamp_hi = upper_32_bits(in_frame->timestamp); upper_32_bits 288 drivers/media/platform/qcom/venus/hfi_cmds.c pkt->time_stamp_hi = upper_32_bits(in_frame->timestamp); upper_32_bits 1077 drivers/message/fusion/mptbase.c (upper_32_bits(dma_addr)); upper_32_bits 1099 drivers/message/fusion/mptbase.c tmp = (u32)(upper_32_bits(dma_addr)); upper_32_bits 1162 drivers/message/fusion/mptbase.c tmp = (u32)(upper_32_bits(dma_addr)); upper_32_bits 773 drivers/misc/habanalabs/goya/goya.c mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); upper_32_bits 775 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 780 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 783 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); upper_32_bits 820 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 833 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr)); upper_32_bits 1021 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); upper_32_bits 1024 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); upper_32_bits 1029 drivers/misc/habanalabs/goya/goya.c upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR)); upper_32_bits 1499 drivers/misc/habanalabs/goya/goya.c mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); upper_32_bits 1501 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 1506 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 1512 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr)); upper_32_bits 1549 drivers/misc/habanalabs/goya/goya.c mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); upper_32_bits 1551 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 1556 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 1590 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 1610 drivers/misc/habanalabs/goya/goya.c mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); upper_32_bits 1612 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 1617 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 1622 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr)); upper_32_bits 1659 drivers/misc/habanalabs/goya/goya.c mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); upper_32_bits 1661 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 1666 drivers/misc/habanalabs/goya/goya.c upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); upper_32_bits 1700 drivers/misc/habanalabs/goya/goya.c so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); upper_32_bits 2247 drivers/misc/habanalabs/goya/goya.c upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); upper_32_bits 257 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); upper_32_bits 258 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); upper_32_bits 433 drivers/misc/habanalabs/goya/goya_coresight.c upper_32_bits(input->buffer_address)); upper_32_bits 505 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0)); upper_32_bits 507 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0)); upper_32_bits 509 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1)); upper_32_bits 511 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1)); upper_32_bits 2289 drivers/misc/habanalabs/goya/goya_security.c u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); upper_32_bits 226 drivers/misc/habanalabs/pci.c rc |= hl_pci_iatu_write(hdev, offset + 0x18, upper_32_bits(addr)); upper_32_bits 265 drivers/misc/habanalabs/pci.c rc |= hl_pci_iatu_write(hdev, 0x118, upper_32_bits(sram_base_address)); upper_32_bits 283 drivers/misc/habanalabs/pci.c upper_32_bits(host_phys_base_address)); upper_32_bits 287 drivers/misc/habanalabs/pci.c rc |= hl_pci_iatu_write(hdev, 0x020, upper_32_bits(host_phys_end_addr)); upper_32_bits 310 drivers/misc/mei/hbm.c req.dma_dscr[i].addr_hi = upper_32_bits(paddr); upper_32_bits 1228 drivers/misc/mei/hw-txe.c u32 hi32 = upper_32_bits(addr); upper_32_bits 370 drivers/misc/pci_endpoint_test.c upper_32_bits(src_phys_addr)); upper_32_bits 395 drivers/misc/pci_endpoint_test.c upper_32_bits(dst_phys_addr)); upper_32_bits 471 drivers/misc/pci_endpoint_test.c upper_32_bits(phys_addr)); upper_32_bits 534 drivers/misc/pci_endpoint_test.c upper_32_bits(phys_addr)); upper_32_bits 265 drivers/mmc/host/cqhci.c cqhci_writel(cq_host, upper_32_bits(cq_host->desc_dma_base), upper_32_bits 644 drivers/mmc/host/mtk-sd.c bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) upper_32_bits 673 drivers/mmc/host/mtk-sd.c upper_32_bits(dma->gpd_addr) & 0xf); upper_32_bits 1639 drivers/mmc/host/mtk-sd.c gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; upper_32_bits 1644 drivers/mmc/host/mtk-sd.c gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; upper_32_bits 1651 drivers/mmc/host/mtk-sd.c bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; upper_32_bits 674 drivers/mmc/host/sdhci.c dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 823 drivers/mmc/host/sdhci.c sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); upper_32_bits 3642 drivers/mmc/host/sdhci.c host->caps1 &= ~upper_32_bits(dt_caps_mask); upper_32_bits 3643 drivers/mmc/host/sdhci.c host->caps1 |= upper_32_bits(dt_caps); upper_32_bits 285 drivers/mmc/host/uniphier-sd.c writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); upper_32_bits 1648 drivers/mtd/nand/raw/brcmnand/brcmnand.c desc->next_desc_ext = upper_32_bits(next_desc); upper_32_bits 1656 drivers/mtd/nand/raw/brcmnand/brcmnand.c desc->dram_addr_ext = upper_32_bits(buf); upper_32_bits 1660 drivers/mtd/nand/raw/brcmnand/brcmnand.c desc->flash_addr_ext = upper_32_bits(addr); upper_32_bits 1676 drivers/mtd/nand/raw/brcmnand/brcmnand.c flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc)); upper_32_bits 609 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1); upper_32_bits 570 drivers/mtd/nand/raw/denali.c denali->host_write(denali, mode, upper_32_bits(dma_addr)); upper_32_bits 206 drivers/net/dsa/b53/b53_mmap.c hi = upper_32_bits(value); upper_32_bits 154 drivers/net/dsa/bcm_sf2.h reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \ upper_32_bits 1553 drivers/net/ethernet/agere/et131x.c writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi); upper_32_bits 1559 drivers/net/ethernet/agere/et131x.c writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi); upper_32_bits 1605 drivers/net/ethernet/agere/et131x.c writel(upper_32_bits(fbr->ring_physaddr), base_hi); upper_32_bits 1646 drivers/net/ethernet/agere/et131x.c writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi); upper_32_bits 1653 drivers/net/ethernet/agere/et131x.c writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi); upper_32_bits 1966 drivers/net/ethernet/agere/et131x.c fbr->bus_high[k] = upper_32_bits(fbr_physaddr); upper_32_bits 2468 drivers/net/ethernet/agere/et131x.c desc[frag].addr_hi = upper_32_bits(dma_addr); upper_32_bits 2477 drivers/net/ethernet/agere/et131x.c desc[frag].addr_hi = upper_32_bits(dma_addr); upper_32_bits 2487 drivers/net/ethernet/agere/et131x.c desc[frag].addr_hi = upper_32_bits(dma_addr); upper_32_bits 2498 drivers/net/ethernet/agere/et131x.c desc[frag].addr_hi = upper_32_bits(dma_addr); upper_32_bits 331 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_MCASTHIGH, upper_32_bits(mcmask)); upper_32_bits 1440 drivers/net/ethernet/alacritech/slicoss.c desc->paddrh = cpu_to_le32(upper_32_bits(paddr)); upper_32_bits 113 drivers/net/ethernet/altera/altera_msgdma.c csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc, upper_32_bits 168 drivers/net/ethernet/altera/altera_msgdma.c csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc, upper_32_bits 1398 drivers/net/ethernet/altera/altera_tse_main.c if (upper_32_bits(priv->rxdescmem_busaddr)) { upper_32_bits 1404 drivers/net/ethernet/altera/altera_tse_main.c if (upper_32_bits(priv->txdescmem_busaddr)) { upper_32_bits 104 drivers/net/ethernet/amazon/ena/ena_com.c ena_addr->mem_addr_high = (u16)upper_32_bits(addr); upper_32_bits 1431 drivers/net/ethernet/amd/xgbe/xgbe-dev.c upper_32_bits(rdata->rdesc_dma)); upper_32_bits 1468 drivers/net/ethernet/amd/xgbe/xgbe-dev.c rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); upper_32_bits 1470 drivers/net/ethernet/amd/xgbe/xgbe-dev.c rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); upper_32_bits 1510 drivers/net/ethernet/amd/xgbe/xgbe-dev.c upper_32_bits(rdata->rdesc_dma)); upper_32_bits 1777 drivers/net/ethernet/amd/xgbe/xgbe-dev.c rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); upper_32_bits 1839 drivers/net/ethernet/amd/xgbe/xgbe-dev.c rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); upper_32_bits 101 drivers/net/ethernet/apm/xgene-v2/main.c upper_32_bits(dma_addr))); upper_32_bits 208 drivers/net/ethernet/apm/xgene-v2/main.c upper_32_bits(dma_addr))); upper_32_bits 28 drivers/net/ethernet/apm/xgene-v2/ring.c dma_h = upper_32_bits(next_dma); upper_32_bits 40 drivers/net/ethernet/apm/xgene-v2/ring.c xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); upper_32_bits 52 drivers/net/ethernet/apm/xgene-v2/ring.c xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); upper_32_bits 110 drivers/net/ethernet/broadcom/bcmsysport.c writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK, upper_32_bits 1329 drivers/net/ethernet/broadcom/bcmsysport.c len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; upper_32_bits 126 drivers/net/ethernet/broadcom/bgmac.c dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); upper_32_bits 392 drivers/net/ethernet/broadcom/bgmac.c dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); upper_32_bits 699 drivers/net/ethernet/broadcom/bgmac.c upper_32_bits(ring->dma_base)); upper_32_bits 717 drivers/net/ethernet/broadcom/bgmac.c upper_32_bits(ring->dma_base)); upper_32_bits 115 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); upper_32_bits 56 drivers/net/ethernet/brocade/bna/bfa_ioc.h dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa)); upper_32_bits 699 drivers/net/ethernet/cadence/macb_main.c desc_64->addrh = upper_32_bits(addr); upper_32_bits 818 drivers/net/ethernet/cadence/macb_main.c queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); upper_32_bits 1330 drivers/net/ethernet/cadence/macb_main.c upper_32_bits(queue->rx_ring_dma)); upper_32_bits 1336 drivers/net/ethernet/cadence/macb_main.c upper_32_bits(queue->tx_ring_dma)); upper_32_bits 2271 drivers/net/ethernet/cadence/macb_main.c queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma)); upper_32_bits 2276 drivers/net/ethernet/cadence/macb_main.c queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); upper_32_bits 678 drivers/net/ethernet/emulex/benet/be_cmds.c val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; upper_32_bits 787 drivers/net/ethernet/emulex/benet/be_cmds.c wrb->tag1 = upper_32_bits(addr); upper_32_bits 809 drivers/net/ethernet/emulex/benet/be_cmds.c sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); upper_32_bits 825 drivers/net/ethernet/emulex/benet/be_cmds.c pages[i].hi = cpu_to_le32(upper_32_bits(dma)); upper_32_bits 2380 drivers/net/ethernet/emulex/benet/be_cmds.c req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + upper_32_bits 2512 drivers/net/ethernet/emulex/benet/be_cmds.c req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); upper_32_bits 771 drivers/net/ethernet/emulex/benet/be_main.c wrb->frag_pa_hi = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 2628 drivers/net/ethernet/emulex/benet/be_main.c rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr)); upper_32_bits 981 drivers/net/ethernet/freescale/enetc/enetc.c enetc_wr(hw, ENETC_SICBDRBAR1, upper_32_bits(cbdr->bd_dma_base)); upper_32_bits 1112 drivers/net/ethernet/freescale/enetc/enetc.c upper_32_bits(tx_ring->bd_dma_base)); upper_32_bits 1146 drivers/net/ethernet/freescale/enetc/enetc.c upper_32_bits(rx_ring->bd_dma_base)); upper_32_bits 141 drivers/net/ethernet/freescale/enetc/enetc_cbdr.c cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align)); upper_32_bits 185 drivers/net/ethernet/freescale/enetc/enetc_cbdr.c cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align)); upper_32_bits 87 drivers/net/ethernet/freescale/enetc/enetc_msg.c val = upper_32_bits(msg->dma); upper_32_bits 23 drivers/net/ethernet/freescale/enetc/enetc_vf.c enetc_wr(hw, ENETC_VSIMSGSNDAR1, upper_32_bits(msg->dma)); upper_32_bits 112 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c upper_32_bits(dma)); upper_32_bits 123 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c upper_32_bits(dma)); upper_32_bits 57 drivers/net/ethernet/huawei/hinic/hinic_common.c sge->hi_addr = upper_32_bits(addr); upper_32_bits 482 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = upper_32_bits(chain->wb_status_paddr); upper_32_bits 514 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c val = upper_32_bits(chain->head_cell_paddr); upper_32_bits 599 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val = upper_32_bits(eq->dma_addr[pg]); upper_32_bits 108 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c wq_page_pfn_hi = upper_32_bits(wq_page_pfn); upper_32_bits 112 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c wq_block_pfn_hi = upper_32_bits(wq_block_pfn); upper_32_bits 165 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c wq_page_pfn_hi = upper_32_bits(wq_page_pfn); upper_32_bits 169 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c wq_block_pfn_hi = upper_32_bits(wq_block_pfn); upper_32_bits 197 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c rq_ctxt->pi_paddr_hi = upper_32_bits(rq->pi_dma_addr); upper_32_bits 161 drivers/net/ethernet/intel/i40e/i40e_adminq.c cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 282 drivers/net/ethernet/intel/i40e/i40e_adminq.c wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); upper_32_bits 311 drivers/net/ethernet/intel/i40e/i40e_adminq.c wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); upper_32_bits 773 drivers/net/ethernet/intel/i40e/i40e_adminq.c cpu_to_le32(upper_32_bits(details->cookie)); upper_32_bits 834 drivers/net/ethernet/intel/i40e/i40e_adminq.c cpu_to_le32(upper_32_bits(dma_buff->pa)); upper_32_bits 1015 drivers/net/ethernet/intel/i40e/i40e_adminq.c desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 102 drivers/net/ethernet/intel/i40e/i40e_hmc.h val1 = (u32)(upper_32_bits(pa)); \ upper_32_bits 147 drivers/net/ethernet/intel/iavf/iavf_adminq.c cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 269 drivers/net/ethernet/intel/iavf/iavf_adminq.c wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); upper_32_bits 298 drivers/net/ethernet/intel/iavf/iavf_adminq.c wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); upper_32_bits 675 drivers/net/ethernet/intel/iavf/iavf_adminq.c cpu_to_le32(upper_32_bits(details->cookie)); upper_32_bits 736 drivers/net/ethernet/intel/iavf/iavf_adminq.c cpu_to_le32(upper_32_bits(dma_buff->pa)); upper_32_bits 916 drivers/net/ethernet/intel/iavf/iavf_adminq.c desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 184 drivers/net/ethernet/intel/ice/ice_controlq.c cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 263 drivers/net/ethernet/intel/ice/ice_controlq.c wr32(hw, ring->bah, upper_32_bits(ring->desc_buf.pa)); upper_32_bits 931 drivers/net/ethernet/intel/ice/ice_controlq.c cpu_to_le32(upper_32_bits(dma_buf->pa)); upper_32_bits 1102 drivers/net/ethernet/intel/ice/ice_controlq.c desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); upper_32_bits 671 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= upper_32_bits(buf_dma_addr) & upper_32_bits 675 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (upper_32_bits(buf_phys_addr) upper_32_bits 948 drivers/net/ethernet/marvell/skge.c rd->dma_hi = upper_32_bits(map); upper_32_bits 2555 drivers/net/ethernet/marvell/skge.c if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) { upper_32_bits 2759 drivers/net/ethernet/marvell/skge.c td->dma_hi = upper_32_bits(map); upper_32_bits 2799 drivers/net/ethernet/marvell/skge.c tf->dma_hi = upper_32_bits(map); upper_32_bits 1092 drivers/net/ethernet/marvell/sky2.c sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); upper_32_bits 1183 drivers/net/ethernet/marvell/sky2.c le->addr = cpu_to_le32(upper_32_bits(map)); upper_32_bits 1853 drivers/net/ethernet/marvell/sky2.c upper = upper_32_bits(mapping); upper_32_bits 1943 drivers/net/ethernet/marvell/sky2.c upper = upper_32_bits(mapping); upper_32_bits 1657 drivers/net/ethernet/mellanox/mlxsw/pci.c mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); upper_32_bits 1662 drivers/net/ethernet/mellanox/mlxsw/pci.c mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); upper_32_bits 1865 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, upper_32_bits 122 drivers/net/ethernet/netronome/nfp/nfp_net.h __d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \ upper_32_bits 137 drivers/net/ethernet/ni/nixge.c (bd)->field##_hi = upper_32_bits((addr)); \ upper_32_bits 218 drivers/net/ethernet/ni/nixge.c writel(upper_32_bits(addr), priv->dma_regs + offset + 4); upper_32_bits 650 drivers/net/ethernet/qlogic/qed/qed_hw.c cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); upper_32_bits 655 drivers/net/ethernet/qlogic/qed/qed_hw.c cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); upper_32_bits 668 drivers/net/ethernet/qlogic/qed/qed_hw.c cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); upper_32_bits 673 drivers/net/ethernet/qlogic/qed/qed_hw.c cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); upper_32_bits 733 drivers/net/ethernet/qlogic/qed/qed_hw.c cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); upper_32_bits 1339 drivers/net/ethernet/qlogic/qed/qed_int.c upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); upper_32_bits 108 drivers/net/ethernet/qlogic/qed/qed_vf.c upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys), upper_32_bits 119 drivers/net/ethernet/qlogic/qed/qed_vf.c upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys)); upper_32_bits 448 drivers/net/ethernet/qlogic/qede/qede.h (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \ upper_32_bits 89 drivers/net/ethernet/qlogic/qede/qede_fp.c rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping)); upper_32_bits 513 drivers/net/ethernet/qlogic/qede/qede_fp.c rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping)); upper_32_bits 305 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(upper_32_bits(adpt->tx_q.tpd.dma_addr), upper_32_bits 315 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(upper_32_bits(adpt->rx_q.rfd.dma_addr), upper_32_bits 852 drivers/net/ethernet/qualcomm/emac/emac-mac.c *hw_rfd = upper_32_bits(addr); upper_32_bits 1360 drivers/net/ethernet/qualcomm/emac/emac-mac.c TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr)); upper_32_bits 1381 drivers/net/ethernet/qualcomm/emac/emac-mac.c TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr)); upper_32_bits 1401 drivers/net/ethernet/qualcomm/emac/emac-mac.c TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr)); upper_32_bits 66 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(upper_32_bits(dma_tx), upper_32_bits 71 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(upper_32_bits(dma_rx), upper_32_bits 617 drivers/net/ethernet/socionext/netsec.c de->data_buf_addr_up = upper_32_bits(desc->dma_addr); upper_32_bits 796 drivers/net/ethernet/socionext/netsec.c de->data_buf_addr_up = upper_32_bits(desc->dma_addr); upper_32_bits 1408 drivers/net/ethernet/socionext/netsec.c upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); upper_32_bits 1413 drivers/net/ethernet/socionext/netsec.c upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); upper_32_bits 342 drivers/net/ethernet/socionext/sni_ave.c upper_32_bits(paddr)); upper_32_bits 250 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c p->des1 = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 299 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c p->des3 = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 57 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); upper_32_bits 74 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); upper_32_bits 828 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c dma_desc->desc1 = cpu_to_le32(upper_32_bits(desc_data->skb_dma)); upper_32_bits 929 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c cpu_to_le32(upper_32_bits(desc_data->skb_dma)); upper_32_bits 1076 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(upper_32_bits(desc_data->dma_desc_addr), upper_32_bits 1113 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c dma_desc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); upper_32_bits 1115 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c dma_desc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); upper_32_bits 1160 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(upper_32_bits(desc_data->dma_desc_addr), upper_32_bits 220 drivers/net/ethernet/ti/tlan.c tag->buffer[8].address = upper_32_bits(addr); upper_32_bits 221 drivers/net/thunderbolt.c hdr->route_hi = upper_32_bits(route); upper_32_bits 241 drivers/net/wireless/ath/ath10k/ce.c u32 addr_hi = upper_32_bits(addr) & CE_DESC_ADDR_HI_MASK; upper_32_bits 346 drivers/net/wireless/ath/ath10k/ce.c u32 addr_hi = upper_32_bits(addr) & CE_DESC_ADDR_HI_MASK; upper_32_bits 594 drivers/net/wireless/ath/ath10k/ce.c flags |= upper_32_bits(buffer) & CE_DESC_ADDR_HI_MASK; upper_32_bits 2012 drivers/net/wireless/ath/ath10k/ce.c (upper_32_bits(ce->paddr_rri) & upper_32_bits 1619 drivers/net/wireless/ath/ath10k/htt_tx.c __cpu_to_le16(upper_32_bits(skb_cb->paddr)); upper_32_bits 1629 drivers/net/wireless/ath/ath10k/htt_tx.c __cpu_to_le16(upper_32_bits(skb_cb->paddr)); upper_32_bits 176 drivers/net/wireless/ath/wil6210/pmc.c cpu_to_le16((u16)upper_32_bits(pmc->descriptors[i].pa)); upper_32_bits 45 drivers/net/wireless/ath/wil6210/txrx.h addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); upper_32_bits 586 drivers/net/wireless/ath/wil6210/txrx_edma.h addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); upper_32_bits 587 drivers/net/wireless/ath/wil6210/txrx_edma.h *addr_high_high = cpu_to_le16((u16)(upper_32_bits(pa) >> 16)); upper_32_bits 51 drivers/net/wireless/broadcom/b43/dma.c addr = upper_32_bits(dmaaddr); upper_32_bits 61 drivers/net/wireless/broadcom/b43/dma.c addr = upper_32_bits(dmaaddr); upper_32_bits 660 drivers/net/wireless/intel/iwlwifi/iwl-fh.h return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF; upper_32_bits 121 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_trans_write32(trans, ofs + 4, upper_32_bits(val)); upper_32_bits 1241 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rx_high = upper_32_bits(tsf); upper_32_bits 256 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size); upper_32_bits 1043 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size); upper_32_bits 1052 drivers/ntb/ntb_transport.c ntb_peer_spad_write(ndev, PIDX, spad, upper_32_bits(size)); upper_32_bits 286 drivers/ntb/test/ntb_perf.c upper_32_bits(data)); upper_32_bits 379 drivers/ntb/test/ntb_perf.c upper_32_bits(data)); upper_32_bits 2712 drivers/nvme/host/core.c c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset)); upper_32_bits 1861 drivers/nvme/host/pci.c c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 350 drivers/of/address.c upper_32_bits(range->cpu_addr)) { upper_32_bits 182 drivers/pci/controller/dwc/pci-keystone.c msg->address_hi = upper_32_bits(msi_target); upper_32_bits 424 drivers/pci/controller/dwc/pci-keystone.c upper_32_bits(start)); upper_32_bits 157 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); upper_32_bits 133 drivers/pci/controller/dwc/pcie-designware-host.c msg->address_hi = upper_32_bits(msi_target); upper_32_bits 313 drivers/pci/controller/dwc/pcie-designware-host.c upper_32_bits(msi_target)); upper_32_bits 250 drivers/pci/controller/dwc/pcie-designware.c upper_32_bits(cpu_addr)); upper_32_bits 256 drivers/pci/controller/dwc/pcie-designware.c upper_32_bits(pci_addr)); upper_32_bits 296 drivers/pci/controller/dwc/pcie-designware.c upper_32_bits(cpu_addr)); upper_32_bits 302 drivers/pci/controller/dwc/pcie-designware.c upper_32_bits(pci_addr)); upper_32_bits 345 drivers/pci/controller/dwc/pcie-designware.c upper_32_bits(cpu_addr)); upper_32_bits 393 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); upper_32_bits 675 drivers/pci/controller/pci-aardvark.c msg->address_hi = upper_32_bits(msi_msg); upper_32_bits 797 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, upper_32_bits(msi_msg_phys), upper_32_bits 1706 drivers/pci/controller/pci-tegra.c msg.address_hi = upper_32_bits(msi->phys); upper_32_bits 148 drivers/pci/controller/pci-xgene-msi.c msg->address_hi = upper_32_bits(target_addr); upper_32_bits 302 drivers/pci/controller/pci-xgene.c val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); upper_32_bits 306 drivers/pci/controller/pci-xgene.c val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); upper_32_bits 392 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); upper_32_bits 394 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); upper_32_bits 396 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); upper_32_bits 404 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); upper_32_bits 458 drivers/pci/controller/pci-xgene.c upper_32_bits(pim) | EN_COHERENCY); upper_32_bits 460 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); upper_32_bits 517 drivers/pci/controller/pci-xgene.c writel(upper_32_bits(cpu_addr), bar_addr + 0x4); upper_32_bits 527 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); upper_32_bits 529 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); upper_32_bits 97 drivers/pci/controller/pcie-altera-msi.c msg->address_hi = upper_32_bits(addr); upper_32_bits 123 drivers/pci/controller/pcie-cadence-ep.c addr1 = upper_32_bits(bar_phys); upper_32_bits 163 drivers/pci/controller/pcie-cadence-host.c addr1 = upper_32_bits(cpu_addr); upper_32_bits 28 drivers/pci/controller/pcie-cadence.c addr1 = upper_32_bits(pci_addr); upper_32_bits 79 drivers/pci/controller/pcie-cadence.c addr1 = upper_32_bits(cpu_addr); upper_32_bits 106 drivers/pci/controller/pcie-cadence.c addr1 = upper_32_bits(cpu_addr); upper_32_bits 231 drivers/pci/controller/pcie-iproc-msi.c msg->address_hi = upper_32_bits(addr); upper_32_bits 389 drivers/pci/controller/pcie-iproc-msi.c upper_32_bits(addr)); upper_32_bits 399 drivers/pci/controller/pcie-iproc-msi.c upper_32_bits(addr)); upper_32_bits 888 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); upper_32_bits 892 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); upper_32_bits 1094 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); upper_32_bits 1109 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(axi_addr), upper_32_bits 1328 drivers/pci/controller/pcie-iproc.c upper_32_bits(msi_addr)); upper_32_bits 725 drivers/pci/controller/pcie-mediatek.c val = upper_32_bits(mem->start); upper_32_bits 486 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(size64), upper_32_bits 491 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), upper_32_bits 496 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), upper_32_bits 527 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(size64), upper_32_bits 537 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), upper_32_bits 542 drivers/pci/controller/pcie-mobiveil.c mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), upper_32_bits 575 drivers/pci/controller/pcie-mobiveil.c writel_relaxed(upper_32_bits(msg_addr), upper_32_bits 739 drivers/pci/controller/pcie-mobiveil.c msg->address_hi = upper_32_bits(addr); upper_32_bits 360 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); upper_32_bits 946 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR); upper_32_bits 1066 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), upper_32_bits 1068 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), upper_32_bits 86 drivers/pci/controller/pcie-rockchip-ep.c addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); upper_32_bits 114 drivers/pci/controller/pcie-rockchip-ep.c addr1 = upper_32_bits(cpu_addr); upper_32_bits 212 drivers/pci/controller/pcie-rockchip-ep.c addr1 = upper_32_bits(bar_phys); upper_32_bits 92 drivers/pci/controller/pcie-tango.c msg->address_hi = upper_32_bits(pcie->msi_doorbell); upper_32_bits 460 drivers/pci/controller/pcie-xilinx-nwl.c msg->address_hi = upper_32_bits(msi_addr); upper_32_bits 627 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); upper_32_bits 674 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), upper_32_bits 712 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), upper_32_bits 643 drivers/pci/controller/vmd.c upper_bits = upper_32_bits(res->end); upper_32_bits 656 drivers/pci/controller/vmd.c upper_bits = upper_32_bits(res->end); upper_32_bits 433 drivers/pci/endpoint/pci-epc-core.c (upper_32_bits(epf_bar->size) && upper_32_bits 140 drivers/pci/endpoint/pci-epf-core.c epf->bar[bar].flags |= upper_32_bits(size) ? upper_32_bits 649 drivers/pci/setup-bus.c bu = upper_32_bits(region.start); upper_32_bits 650 drivers/pci/setup-bus.c lu = upper_32_bits(region.end); upper_32_bits 770 drivers/perf/xgene_pmu.c cnt_hi = upper_32_bits(val); upper_32_bits 816 drivers/platform/goldfish/goldfish_pipe.c writel(upper_32_bits(paddr), porth); upper_32_bits 553 drivers/platform/x86/dcdbas.c if (upper_32_bits(eps->smm_comm_buff_addr + 8)) { upper_32_bits 1709 drivers/scsi/aacraid/aachba.c sg64->sg[0].addr[1] = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 131 drivers/scsi/aacraid/comminit.c upper_32_bits(addr)); upper_32_bits 201 drivers/scsi/aacraid/comminit.c cpu_to_le32(upper_32_bits(dev->host_rrq_pa)); upper_32_bits 213 drivers/scsi/aacraid/comminit.c cpu_to_le32(upper_32_bits(dev->host_rrq_pa)); upper_32_bits 402 drivers/scsi/aacraid/src.c upper_32_bits(dev->init_pa), upper_32_bits 552 drivers/scsi/aacraid/src.c upper_32_bits(address) & 0xffffffff); upper_32_bits 568 drivers/scsi/aacraid/src.c WARN_ON(upper_32_bits(address) != 0L); upper_32_bits 595 drivers/scsi/aacraid/src.c upper_32_bits(address) & 0xffffffff); upper_32_bits 733 drivers/scsi/arcmsr/arcmsr_hba.c curr_phy_upper32 = upper_32_bits(dma_coherent_handle); upper_32_bits 753 drivers/scsi/arcmsr/arcmsr_hba.c if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) { upper_32_bits 1821 drivers/scsi/arcmsr/arcmsr_hba.c writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high); upper_32_bits 1835 drivers/scsi/arcmsr/arcmsr_hba.c pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr); upper_32_bits 3780 drivers/scsi/arcmsr/arcmsr_hba.c cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle); upper_32_bits 649 drivers/scsi/be2iscsi/be_cmds.c val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; upper_32_bits 703 drivers/scsi/be2iscsi/be_cmds.c pages[i].hi = cpu_to_le32(upper_32_bits(dma)); upper_32_bits 1284 drivers/scsi/be2iscsi/be_cmds.c sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma)); upper_32_bits 2100 drivers/scsi/be2iscsi/be_main.c upper_32_bits(addr)); upper_32_bits 2115 drivers/scsi/be2iscsi/be_main.c upper_32_bits(addr)); upper_32_bits 2158 drivers/scsi/be2iscsi/be_main.c upper_32_bits(addr)); upper_32_bits 2303 drivers/scsi/be2iscsi/be_main.c upper_32_bits(io_task->mtask_addr)); upper_32_bits 2335 drivers/scsi/be2iscsi/be_main.c upper_32_bits(io_task->mtask_addr)); upper_32_bits 88 drivers/scsi/be2iscsi/be_mgmt.c mcc_sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); upper_32_bits 197 drivers/scsi/be2iscsi/be_mgmt.c sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); upper_32_bits 243 drivers/scsi/be2iscsi/be_mgmt.c sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); upper_32_bits 1033 drivers/scsi/be2iscsi/be_mgmt.c sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); upper_32_bits 1544 drivers/scsi/be2iscsi/be_mgmt.c sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma)); upper_32_bits 157 drivers/scsi/dpt_i2o.c return upper_32_bits(addr); upper_32_bits 391 drivers/scsi/esas2r/esas2r_init.c upper_32_bits(bus_addr), upper_32_bits 1072 drivers/scsi/esas2r/esas2r_init.c upper_32_bits(ppaddr)); upper_32_bits 1077 drivers/scsi/esas2r/esas2r_init.c upper_32_bits(ppaddr)); upper_32_bits 1083 drivers/scsi/esas2r/esas2r_init.c upper_32_bits(ppaddr)); upper_32_bits 701 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c upper_32_bits(hisi_hba->cmd_hdr_dma[i])); upper_32_bits 714 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c upper_32_bits(hisi_hba->complete_hdr_dma[i])); upper_32_bits 729 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c upper_32_bits(hisi_hba->itct_dma)); upper_32_bits 736 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c upper_32_bits(hisi_hba->iost_dma)); upper_32_bits 743 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c upper_32_bits(hisi_hba->breakpoint_dma)); upper_32_bits 1269 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->cmd_hdr_dma[i])); upper_32_bits 1279 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->complete_hdr_dma[i])); upper_32_bits 1293 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->itct_dma)); upper_32_bits 1300 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->iost_dma)); upper_32_bits 1307 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->breakpoint_dma)); upper_32_bits 1314 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->sata_breakpoint_dma)); upper_32_bits 1321 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c upper_32_bits(hisi_hba->initial_fis_dma)); upper_32_bits 638 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->cmd_hdr_dma[i])); upper_32_bits 648 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->complete_hdr_dma[i])); upper_32_bits 662 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->itct_dma)); upper_32_bits 669 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->iost_dma)); upper_32_bits 676 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->breakpoint_dma)); upper_32_bits 683 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->sata_breakpoint_dma)); upper_32_bits 690 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c upper_32_bits(hisi_hba->initial_fis_dma)); upper_32_bits 1805 drivers/scsi/ips.c cpu_to_le32(upper_32_bits(busaddr)); upper_32_bits 2306 drivers/scsi/isci/host.c writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper); upper_32_bits 2309 drivers/scsi/isci/host.c writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper); upper_32_bits 2312 drivers/scsi/isci/host.c writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper); upper_32_bits 2322 drivers/scsi/isci/host.c writel(upper_32_bits(ihost->uf_control.headers.physical_address), upper_32_bits 2327 drivers/scsi/isci/host.c writel(upper_32_bits(ihost->uf_control.address_table.physical_address), upper_32_bits 135 drivers/scsi/isci/remote_node_context.c rnc->ssp.remote_sas_address_hi = upper_32_bits(sas_addr); upper_32_bits 108 drivers/scsi/isci/request.c e->address_upper = upper_32_bits(sg_dma_address(sg)); upper_32_bits 142 drivers/scsi/isci/request.c upper_32_bits(dma_addr); upper_32_bits 161 drivers/scsi/isci/request.c scu_sg->A.address_upper = upper_32_bits(dma_addr); upper_32_bits 265 drivers/scsi/isci/request.c task_context->command_iu_upper = upper_32_bits(dma_addr); upper_32_bits 274 drivers/scsi/isci/request.c task_context->response_iu_upper = upper_32_bits(dma_addr); upper_32_bits 553 drivers/scsi/isci/request.c task_context->command_iu_upper = upper_32_bits(dma_addr); upper_32_bits 3295 drivers/scsi/isci/request.c task_context->command_iu_upper = upper_32_bits(sg_dma_address(sg)); upper_32_bits 172 drivers/scsi/isci/unsolicited_frame_control.c upper_32_bits(uf_control->address_table.array[frame_get]) == 0 && upper_32_bits 841 drivers/scsi/megaraid/megaraid_sas_base.c writel(upper_32_bits(frame_phys_addr), upper_32_bits 1190 drivers/scsi/megaraid/megaraid_sas_base.c cpu_to_le32(upper_32_bits(cmd_to_abort->frame_phys_addr)); upper_32_bits 1458 drivers/scsi/megaraid/megaraid_sas_base.c cpu_to_le32(upper_32_bits(cmd->sense_phys_addr)); upper_32_bits 5393 drivers/scsi/megaraid/megaraid_sas_base.c cpu_to_le32(upper_32_bits(initq_info_h)); upper_32_bits 164 drivers/scsi/megaraid/megaraid_sas_fusion.c if (upper_32_bits(start_addr) != upper_32_bits(end_addr)) { upper_32_bits 1112 drivers/scsi/megaraid/megaraid_sas_fusion.c IOCInitMessage->SenseBufferAddressHigh = cpu_to_le32(upper_32_bits(fusion->sense_phys_addr)); upper_32_bits 1167 drivers/scsi/megaraid/megaraid_sas_fusion.c init_frame->system_info_hi = cpu_to_le32(upper_32_bits(instance->system_info_h)); upper_32_bits 1171 drivers/scsi/megaraid/megaraid_sas_fusion.c cpu_to_le32(upper_32_bits(ioc_init_handle)); upper_32_bits 1193 drivers/scsi/megaraid/megaraid_sas_fusion.c req_desc.u.high = cpu_to_le32(upper_32_bits(cmd->frame_phys_addr)); upper_32_bits 4816 drivers/scsi/mpt3sas/mpt3sas_base.c if (upper_32_bits(reply_pool_start_address) == upper_32_bits 4817 drivers/scsi/mpt3sas/mpt3sas_base.c upper_32_bits(reply_pool_end_address)) upper_32_bits 211 drivers/scsi/mvumi.c m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr)); upper_32_bits 243 drivers/scsi/mvumi.c m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(phy_addr)); upper_32_bits 875 drivers/scsi/mvumi.c hs_page4->ib_baseaddr_h = upper_32_bits(mhba->ib_list_phys); upper_32_bits 878 drivers/scsi/mvumi.c hs_page4->ob_baseaddr_h = upper_32_bits(mhba->ob_list_phys); upper_32_bits 1123 drivers/scsi/mvumi.c iowrite32(upper_32_bits(mhba->handshake_page_phys), upper_32_bits 1181 drivers/scsi/mvumi.c iowrite32(upper_32_bits(mhba->ib_shadow_phys), upper_32_bits 1191 drivers/scsi/mvumi.c iowrite32(upper_32_bits(mhba->ob_shadow_phys), upper_32_bits 1852 drivers/scsi/mvumi.c cpu_to_le32(upper_32_bits(cmd->frame_phys)); upper_32_bits 4341 drivers/scsi/pm8001/pm8001_hwi.c ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); upper_32_bits 4346 drivers/scsi/pm8001/pm8001_hwi.c ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 4414 drivers/scsi/pm8001/pm8001_hwi.c sata_cmd.addr_high = upper_32_bits(phys_addr); upper_32_bits 4419 drivers/scsi/pm8001/pm8001_hwi.c sata_cmd.addr_high = upper_32_bits(dma_addr); upper_32_bits 4940 drivers/scsi/pm8001/pm8001_hwi.c cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); upper_32_bits 128 drivers/scsi/pm8001/pm8001_sas.c *pphys_addr_hi = upper_32_bits(phys_align); upper_32_bits 4103 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(phys_addr)); upper_32_bits 4110 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 4117 drivers/scsi/pm8001/pm80xx_hwi.c end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); upper_32_bits 4134 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(phys_addr)); upper_32_bits 4163 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(phys_addr)); upper_32_bits 4169 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(dma_addr)); upper_32_bits 4176 drivers/scsi/pm8001/pm80xx_hwi.c end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); upper_32_bits 4193 drivers/scsi/pm8001/pm80xx_hwi.c cpu_to_le32(upper_32_bits(phys_addr)); upper_32_bits 4282 drivers/scsi/pm8001/pm80xx_hwi.c sata_cmd.enc_addr_high = upper_32_bits(phys_addr); upper_32_bits 4287 drivers/scsi/pm8001/pm80xx_hwi.c sata_cmd.enc_addr_high = upper_32_bits(dma_addr); upper_32_bits 4294 drivers/scsi/pm8001/pm80xx_hwi.c end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); upper_32_bits 4311 drivers/scsi/pm8001/pm80xx_hwi.c upper_32_bits(phys_addr); upper_32_bits 4348 drivers/scsi/pm8001/pm80xx_hwi.c sata_cmd.addr_high = upper_32_bits(phys_addr); upper_32_bits 4353 drivers/scsi/pm8001/pm80xx_hwi.c sata_cmd.addr_high = upper_32_bits(dma_addr); upper_32_bits 4360 drivers/scsi/pm8001/pm80xx_hwi.c end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); upper_32_bits 4377 drivers/scsi/pm8001/pm80xx_hwi.c upper_32_bits(phys_addr); upper_32_bits 1756 drivers/scsi/qla1280.c mb[7] = upper_32_bits(ha->request_dma) & 0xffff; upper_32_bits 1757 drivers/scsi/qla1280.c mb[6] = upper_32_bits(ha->request_dma) >> 16; upper_32_bits 1776 drivers/scsi/qla1280.c mb[7] = upper_32_bits(p_tbuf) & 0xffff; upper_32_bits 1777 drivers/scsi/qla1280.c mb[6] = upper_32_bits(p_tbuf) >> 16; upper_32_bits 1899 drivers/scsi/qla1280.c mb[7] = upper_32_bits(ha->request_dma) & 0xffff; upper_32_bits 1900 drivers/scsi/qla1280.c mb[6] = upper_32_bits(ha->request_dma) >> 16; upper_32_bits 1913 drivers/scsi/qla1280.c mb[7] = upper_32_bits(ha->response_dma) & 0xffff; upper_32_bits 1914 drivers/scsi/qla1280.c mb[6] = upper_32_bits(ha->response_dma) >> 16; upper_32_bits 2869 drivers/scsi/qla1280.c cpu_to_le32(upper_32_bits(dma_handle)); upper_32_bits 2872 drivers/scsi/qla1280.c cpu_to_le32(upper_32_bits(dma_handle)), upper_32_bits 2925 drivers/scsi/qla1280.c cpu_to_le32(upper_32_bits(dma_handle)); upper_32_bits 2929 drivers/scsi/qla1280.c cpu_to_le32(upper_32_bits(dma_handle)), upper_32_bits 2255 drivers/scsi/smartpqi/smartpqi_init.c encryption_info->encrypt_tweak_upper = upper_32_bits(first_block); upper_32_bits 306 drivers/scsi/smartpqi/smartpqi_sis.c put_unaligned_le32(upper_32_bits(error_buffer_paddr), upper_32_bits 322 drivers/scsi/smartpqi/smartpqi_sis.c params.mailbox[2] = upper_32_bits((u64)bus_address); upper_32_bits 37 drivers/scsi/snic/vnic_dev.h writel(upper_32_bits(val), reg + 0x4UL); upper_32_bits 2136 drivers/scsi/ufs/ufshcd.c cpu_to_le32(upper_32_bits(sg->dma_address)); upper_32_bits 3482 drivers/scsi/ufs/ufshcd.c cpu_to_le32(upper_32_bits(cmd_desc_element_addr)); upper_32_bits 4208 drivers/scsi/ufs/ufshcd.c ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), upper_32_bits 4212 drivers/scsi/ufs/ufshcd.c ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), upper_32_bits 437 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed(upper_32_bits(params_pa), upper_32_bits 120 drivers/soc/fsl/qbman/bman_ccsr.c if (bare != upper_32_bits(ba) || bar != lower_32_bits(ba)) { upper_32_bits 130 drivers/soc/fsl/qbman/bman_ccsr.c bm_ccsr_out(REG_FBPR_BARE, upper_32_bits(ba)); upper_32_bits 75 drivers/soc/fsl/qbman/dpaa_sys.c res_array[0] = cpu_to_be32(upper_32_bits(*addr)); upper_32_bits 77 drivers/soc/fsl/qbman/dpaa_sys.c res_array[2] = cpu_to_be32(upper_32_bits(*size)); upper_32_bits 362 drivers/soc/fsl/qbman/qman_ccsr.c if (bare != upper_32_bits(ba) || bar != lower_32_bits(ba)) { upper_32_bits 389 drivers/soc/fsl/qbman/qman_ccsr.c qm_ccsr_out(offset, upper_32_bits(ba)); upper_32_bits 645 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); upper_32_bits 681 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); upper_32_bits 1840 drivers/staging/media/allegro-dvt/allegro-core.c upper_32_bits(dev->firmware.paddr)); upper_32_bits 1845 drivers/staging/media/allegro-dvt/allegro-core.c upper_32_bits(icache_offset), lower_32_bits(icache_offset)); upper_32_bits 1847 drivers/staging/media/allegro-dvt/allegro-core.c upper_32_bits(icache_offset)); upper_32_bits 1855 drivers/staging/media/allegro-dvt/allegro-core.c upper_32_bits(dcache_offset), lower_32_bits(dcache_offset)); upper_32_bits 1857 drivers/staging/media/allegro-dvt/allegro-core.c upper_32_bits(dcache_offset)); upper_32_bits 629 drivers/thunderbolt/icm.c sw->config.route_hi = upper_32_bits(route); upper_32_bits 1081 drivers/thunderbolt/icm.c request.route_hi = upper_32_bits(xd->route); upper_32_bits 1111 drivers/thunderbolt/icm.c request.route_hi = upper_32_bits(xd->route); upper_32_bits 1551 drivers/thunderbolt/switch.c sw->config.route_hi = upper_32_bits(route); upper_32_bits 1627 drivers/thunderbolt/switch.c sw->config.route_hi = upper_32_bits(route); upper_32_bits 2046 drivers/thunderbolt/switch.c sw->config.route_hi == upper_32_bits(lookup->route); upper_32_bits 195 drivers/thunderbolt/xdomain.c hdr->xd_hdr.route_hi = upper_32_bits(route); upper_32_bits 263 drivers/thunderbolt/xdomain.c res.src_route_hi = upper_32_bits(route); upper_32_bits 414 drivers/usb/dwc3/core.c upper_32_bits(evt->dma)); upper_32_bits 487 drivers/usb/dwc3/core.c param = upper_32_bits(scratch_addr); upper_32_bits 827 drivers/usb/dwc3/debugfs.c u32 upper_32_bits; upper_32_bits 835 drivers/usb/dwc3/debugfs.c upper_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1); upper_32_bits 837 drivers/usb/dwc3/debugfs.c ep_info = ((u64)upper_32_bits << 32) | lower_32_bits; upper_32_bits 47 drivers/usb/dwc3/ep0.c trb->bph = upper_32_bits(buf_dma); upper_32_bits 75 drivers/usb/dwc3/ep0.c params.param0 = upper_32_bits(dwc->ep0_trb_addr); upper_32_bits 654 drivers/usb/dwc3/gadget.c trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); upper_32_bits 674 drivers/usb/dwc3/gadget.c params.param0 = upper_32_bits(trb_dma); upper_32_bits 920 drivers/usb/dwc3/gadget.c trb->bph = upper_32_bits(dma); upper_32_bits 1243 drivers/usb/dwc3/gadget.c params.param0 = upper_32_bits(req->trb_dma); upper_32_bits 1342 drivers/usb/dwc3/gadget.c params.param0 = upper_32_bits(dep->dwc->bounce_addr); upper_32_bits 212 drivers/usb/early/xhci-dbc.c link_trb->field[1] = cpu_to_le32(upper_32_bits(seg->dma)); upper_32_bits 507 drivers/usb/early/xhci-dbc.c xdbc_queue_trb(ring, lower_32_bits(addr), upper_32_bits(addr), length, control); upper_32_bits 146 drivers/usb/gadget/udc/bdc/bdc_cmd.c param1 = upper_32_bits(ep->bd_list.bd_table_array[0]->dma); upper_32_bits 231 drivers/usb/gadget/udc/bdc/bdc_cmd.c param1 = upper_32_bits(dma_addr); upper_32_bits 185 drivers/usb/gadget/udc/bdc/bdc_core.c upp32 = upper_32_bits(bdc->scratchpad.sp_dma); upper_32_bits 245 drivers/usb/gadget/udc/bdc/bdc_core.c upp32 = upper_32_bits(bdc->srr.dma_addr); upper_32_bits 111 drivers/usb/gadget/udc/bdc/bdc_ep.c cpu_to_le32(upper_32_bits(next_table->dma)); upper_32_bits 483 drivers/usb/gadget/udc/bdc/bdc_ep.c bd->offset[1] = cpu_to_le32(upper_32_bits(buf_add)); upper_32_bits 844 drivers/usb/gadget/udc/bdc/bdc_ep.c bd_start->offset[1] = cpu_to_le32(upper_32_bits(next_bd_dma)); upper_32_bits 269 drivers/usb/host/xhci-dbgcap.c upper_32_bits(addr), upper_32_bits 2696 drivers/usb/host/xhci-ring.c upper_32_bits(le64_to_cpu(event->buffer)), upper_32_bits 3413 drivers/usb/host/xhci-ring.c upper_32_bits(send_addr), upper_32_bits 3557 drivers/usb/host/xhci-ring.c upper_32_bits(addr), upper_32_bits 3862 drivers/usb/host/xhci-ring.c upper_32_bits(addr), upper_32_bits 4062 drivers/usb/host/xhci-ring.c upper_32_bits(in_ctx_ptr), 0, upper_32_bits 4088 drivers/usb/host/xhci-ring.c upper_32_bits(in_ctx_ptr), 0, upper_32_bits 4098 drivers/usb/host/xhci-ring.c upper_32_bits(in_ctx_ptr), 0, upper_32_bits 4169 drivers/usb/host/xhci-ring.c upper_32_bits(addr), trb_stream_id, upper_32_bits 263 drivers/usb/host/xhci.c if (upper_32_bits(val)) upper_32_bits 266 drivers/usb/host/xhci.c if (upper_32_bits(val)) upper_32_bits 274 drivers/usb/host/xhci.c if (upper_32_bits(val)) upper_32_bits 277 drivers/usb/host/xhci.c if (upper_32_bits(val)) upper_32_bits 103 drivers/usb/mtu3/mtu3_qmu.c tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); upper_32_bits 115 drivers/usb/mtu3/mtu3_qmu.c rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); upper_32_bits 255 drivers/usb/mtu3/mtu3_qmu.c ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma)); upper_32_bits 266 drivers/usb/mtu3/mtu3_qmu.c ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma)); upper_32_bits 296 drivers/usb/mtu3/mtu3_qmu.c ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma)); upper_32_bits 307 drivers/usb/mtu3/mtu3_qmu.c ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma)); upper_32_bits 506 fs/afs/fsclient.c bp[4] = htonl(upper_32_bits(req->pos)); upper_32_bits 534 fs/afs/fsclient.c if (upper_32_bits(req->pos) || upper_32_bits 535 fs/afs/fsclient.c upper_32_bits(req->len) || upper_32_bits 536 fs/afs/fsclient.c upper_32_bits(req->pos + req->len)) upper_32_bits 346 fs/ext4/super.c *hi = upper_32_bits(now); upper_32_bits 18 include/linux/goldfish.h writel(upper_32_bits(addr), porth); upper_32_bits 28 include/linux/goldfish.h writel(upper_32_bits(addr), porth); upper_32_bits 45 include/linux/qed/common_hsi.h #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) upper_32_bits 61 include/soc/fsl/bman.h buf->hi = cpu_to_be16(upper_32_bits(addr)); upper_32_bits 127 include/soc/fsl/qman.h fd->addr_hi = upper_32_bits(addr); upper_32_bits 213 include/soc/fsl/qman.h sg->addr_hi = upper_32_bits(addr); upper_32_bits 416 include/soc/fsl/qman.h fqd->context_a.context_hi = cpu_to_be16(upper_32_bits(addr)); upper_32_bits 422 include/soc/fsl/qman.h fqd->context_a.hi = cpu_to_be32(upper_32_bits(addr)); upper_32_bits 678 ipc/msg.c v.msg_stime_high = upper_32_bits(in->msg_stime); upper_32_bits 680 ipc/msg.c v.msg_rtime_high = upper_32_bits(in->msg_rtime); upper_32_bits 682 ipc/msg.c v.msg_ctime_high = upper_32_bits(in->msg_ctime); upper_32_bits 1740 ipc/sem.c v.sem_otime_high = upper_32_bits(in->sem_otime); upper_32_bits 1742 ipc/sem.c v.sem_ctime_high = upper_32_bits(in->sem_ctime); upper_32_bits 1296 ipc/shm.c v.shm_atime_high = upper_32_bits(in->shm_atime); upper_32_bits 1298 ipc/shm.c v.shm_dtime_high = upper_32_bits(in->shm_dtime); upper_32_bits 1300 ipc/shm.c v.shm_ctime_high = upper_32_bits(in->shm_ctime); upper_32_bits 2614 kernel/sys.c if (upper_32_bits(s.totalram) || upper_32_bits(s.totalswap)) { upper_32_bits 314 sound/core/oss/pcm_plugin.c if (formats.bits[1] & upper_32_bits(linfmts)) upper_32_bits 315 sound/core/oss/pcm_plugin.c formats.bits[1] |= upper_32_bits(linfmts); upper_32_bits 51 sound/hda/hdac_controller.c snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); upper_32_bits 72 sound/hda/hdac_controller.c snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); upper_32_bits 501 sound/hda/hdac_controller.c snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); upper_32_bits 223 sound/hda/hdac_stream.c upper_32_bits(azx_dev->bdl.addr)); upper_32_bits 376 sound/hda/hdac_stream.c bdl[1] = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 1268 sound/pci/ctxfi/cthw20k1.c ptp_phys_high = upper_32_bits(info->vm_pgt_phys); upper_32_bits 1247 sound/pci/ctxfi/cthw20k2.c ptp_phys_high = upper_32_bits(info->vm_pgt_phys); upper_32_bits 377 sound/pci/lola/lola.c lola_writel(chip, BAR0, CORBUBASE, upper_32_bits(chip->corb.addr)); upper_32_bits 394 sound/pci/lola/lola.c lola_writel(chip, BAR0, RIRBUBASE, upper_32_bits(chip->rirb.addr)); upper_32_bits 321 sound/pci/lola/lola_pcm.c bdl[1] = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 439 sound/pci/lola/lola_pcm.c lola_dsd_write(chip, str->dsd, BDPU, upper_32_bits(bdl)); upper_32_bits 443 sound/pci/lx6464es/lx6464es.c lower_32_bits(buf), upper_32_bits(buf), upper_32_bits 313 sound/soc/amd/acp-pcm-dma.c high = upper_32_bits(addr); upper_32_bits 232 sound/soc/amd/raven/acp3x-pcm-dma.c high = upper_32_bits(addr); upper_32_bits 173 sound/soc/fsl/fsl_dma.c upper_32_bits(dma_private->dma_buf_next)); upper_32_bits 179 sound/soc/fsl/fsl_dma.c upper_32_bits(dma_private->dma_buf_next)); upper_32_bits 668 sound/soc/fsl/fsl_dma.c upper_32_bits(temp_addr)); upper_32_bits 672 sound/soc/fsl/fsl_dma.c upper_32_bits(ssi_sxx_phys)); upper_32_bits 676 sound/soc/fsl/fsl_dma.c upper_32_bits(ssi_sxx_phys)); upper_32_bits 680 sound/soc/fsl/fsl_dma.c upper_32_bits(temp_addr)); upper_32_bits 88 sound/soc/intel/skylake/skl-sst-cldma.c bdl[1] = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 152 sound/soc/intel/skylake/skl-sst-cldma.h ((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK) upper_32_bits 131 sound/soc/mediatek/common/mtk-afe-fe-dai.c msb_at_bit33 = upper_32_bits(substream->runtime->dma_addr) ? 1 : 0; upper_32_bits 397 sound/soc/qcom/qdsp6/q6asm.c mregions->shm_addr_msw = upper_32_bits(ab->phys); upper_32_bits 614 sound/soc/qcom/qdsp6/q6asm.c upper_32_bits(phys) != result->status) { upper_32_bits 641 sound/soc/qcom/qdsp6/q6asm.c if (upper_32_bits(phys) != done->buf_addr_msw || upper_32_bits 1110 sound/soc/qcom/qdsp6/q6asm.c read->buf_addr_msw = upper_32_bits(ab->phys); upper_32_bits 1232 sound/soc/qcom/qdsp6/q6asm.c write->buf_addr_msw = upper_32_bits(ab->phys); upper_32_bits 247 sound/soc/sof/intel/hda-ctrl.c upper_32_bits(bus->posbuf.addr)); upper_32_bits 49 sound/soc/sof/intel/hda-stream.c bdl->addr_h = cpu_to_le32(upper_32_bits(addr)); upper_32_bits 484 sound/soc/sof/intel/hda-stream.c upper_32_bits(hstream->bdl.addr)); upper_32_bits 490 sound/soc/sof/intel/hda-stream.c upper_32_bits(bus->posbuf.addr)); upper_32_bits 1115 sound/soc/uniphier/aio-core.c upper_32_bits(pos)); upper_32_bits 1149 sound/soc/uniphier/aio-core.c upper_32_bits(start)); upper_32_bits 1153 sound/soc/uniphier/aio-core.c upper_32_bits(end)); upper_32_bits 465 sound/soc/xilinx/xlnx_formatter_pcm.c high = upper_32_bits(substream->dma_buffer.addr); upper_32_bits 455 virt/kvm/arm/arch_timer.c u32 high = upper_32_bits(cntvoff); upper_32_bits 149 virt/kvm/arm/pmu.c counter = upper_32_bits(counter); upper_32_bits 215 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg + 1) = upper_32_bits(counter);