This source file includes following definitions.
- pcm037_variant_setup
- pcm037_variant
- pcm970_sdhc1_get_ro
- pcm970_sdhc1_init
- pcm970_sdhc1_exit
- pcm037_otg_init
- pcm037_usbh2_init
- pcm037_otg_mode
- pcm037_init
- pcm037_timer_init
- pcm037_init_late
1
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3
4
5
6 #include <linux/types.h>
7 #include <linux/init.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/platform_device.h>
10 #include <linux/mtd/physmap.h>
11 #include <linux/mtd/plat-ram.h>
12 #include <linux/memory.h>
13 #include <linux/gpio.h>
14 #include <linux/smsc911x.h>
15 #include <linux/interrupt.h>
16 #include <linux/i2c.h>
17 #include <linux/property.h>
18 #include <linux/delay.h>
19 #include <linux/spi/spi.h>
20 #include <linux/irq.h>
21 #include <linux/can/platform/sja1000.h>
22 #include <linux/usb/otg.h>
23 #include <linux/usb/ulpi.h>
24 #include <linux/gfp.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/fixed.h>
27
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/time.h>
31 #include <asm/mach/map.h>
32
33 #include "common.h"
34 #include "devices-imx31.h"
35 #include "ehci.h"
36 #include "hardware.h"
37 #include "iomux-mx3.h"
38 #include "pcm037.h"
39 #include "ulpi.h"
40
41 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
42
43 static int __init pcm037_variant_setup(char *str)
44 {
45 if (!strcmp("eet", str))
46 pcm037_instance = PCM037_EET;
47 else if (strcmp("pcm970", str))
48 pr_warn("Unknown pcm037 baseboard variant %s\n", str);
49
50 return 1;
51 }
52
53
54 __setup("pcm037_variant=", pcm037_variant_setup);
55
56 enum pcm037_board_variant pcm037_variant(void)
57 {
58 return pcm037_instance;
59 }
60
61
62 static unsigned int pcm037_uart1_handshake_pins[] = {
63 MX31_PIN_CTS1__CTS1,
64 MX31_PIN_RTS1__RTS1,
65 MX31_PIN_TXD1__TXD1,
66 MX31_PIN_RXD1__RXD1,
67 };
68
69
70 static unsigned int pcm037_uart1_pins[] = {
71 MX31_PIN_TXD1__TXD1,
72 MX31_PIN_RXD1__RXD1,
73 };
74
75 static unsigned int pcm037_pins[] = {
76
77 MX31_PIN_CSPI2_MOSI__SCL,
78 MX31_PIN_CSPI2_MISO__SDA,
79 MX31_PIN_CSPI2_SS2__I2C3_SDA,
80 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
81
82 MX31_PIN_SD1_DATA3__SD1_DATA3,
83 MX31_PIN_SD1_DATA2__SD1_DATA2,
84 MX31_PIN_SD1_DATA1__SD1_DATA1,
85 MX31_PIN_SD1_DATA0__SD1_DATA0,
86 MX31_PIN_SD1_CLK__SD1_CLK,
87 MX31_PIN_SD1_CMD__SD1_CMD,
88 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO),
89 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
90
91 MX31_PIN_CSPI1_MOSI__MOSI,
92 MX31_PIN_CSPI1_MISO__MISO,
93 MX31_PIN_CSPI1_SCLK__SCLK,
94 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
95 MX31_PIN_CSPI1_SS0__SS0,
96 MX31_PIN_CSPI1_SS1__SS1,
97 MX31_PIN_CSPI1_SS2__SS2,
98
99 MX31_PIN_TXD2__TXD2,
100 MX31_PIN_RXD2__RXD2,
101 MX31_PIN_CTS2__CTS2,
102 MX31_PIN_RTS2__RTS2,
103
104 MX31_PIN_CSPI3_MOSI__RXD3,
105 MX31_PIN_CSPI3_MISO__TXD3,
106 MX31_PIN_CSPI3_SCLK__RTS3,
107 MX31_PIN_CSPI3_SPI_RDY__CTS3,
108
109 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
110
111 MX31_PIN_BATT_LINE__OWIRE,
112
113 MX31_PIN_LD0__LD0,
114 MX31_PIN_LD1__LD1,
115 MX31_PIN_LD2__LD2,
116 MX31_PIN_LD3__LD3,
117 MX31_PIN_LD4__LD4,
118 MX31_PIN_LD5__LD5,
119 MX31_PIN_LD6__LD6,
120 MX31_PIN_LD7__LD7,
121 MX31_PIN_LD8__LD8,
122 MX31_PIN_LD9__LD9,
123 MX31_PIN_LD10__LD10,
124 MX31_PIN_LD11__LD11,
125 MX31_PIN_LD12__LD12,
126 MX31_PIN_LD13__LD13,
127 MX31_PIN_LD14__LD14,
128 MX31_PIN_LD15__LD15,
129 MX31_PIN_LD16__LD16,
130 MX31_PIN_LD17__LD17,
131 MX31_PIN_VSYNC3__VSYNC3,
132 MX31_PIN_HSYNC__HSYNC,
133 MX31_PIN_FPSHIFT__FPSHIFT,
134 MX31_PIN_DRDY0__DRDY0,
135 MX31_PIN_D3_REV__D3_REV,
136 MX31_PIN_CONTRAST__CONTRAST,
137 MX31_PIN_D3_SPL__D3_SPL,
138 MX31_PIN_D3_CLS__D3_CLS,
139 MX31_PIN_LCS0__GPIO3_23,
140
141 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
142
143 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
144 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
145 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
146 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
147 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
148 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
149 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
150 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
151 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
152 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
153 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
154 MX31_PIN_USBOTG_STP__USBOTG_STP,
155
156 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
157 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
158 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
159 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
160 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
161 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
162 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
163 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
164 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
165 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
166 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
167 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
168 };
169
170 static struct physmap_flash_data pcm037_flash_data = {
171 .width = 2,
172 };
173
174 static struct resource pcm037_flash_resource = {
175 .start = 0xa0000000,
176 .end = 0xa1ffffff,
177 .flags = IORESOURCE_MEM,
178 };
179
180 static struct platform_device pcm037_flash = {
181 .name = "physmap-flash",
182 .id = 0,
183 .dev = {
184 .platform_data = &pcm037_flash_data,
185 },
186 .resource = &pcm037_flash_resource,
187 .num_resources = 1,
188 };
189
190 static const struct imxuart_platform_data uart_pdata __initconst = {
191 .flags = IMXUART_HAVE_RTSCTS,
192 };
193
194 static struct resource smsc911x_resources[] = {
195 {
196 .start = MX31_CS1_BASE_ADDR + 0x300,
197 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
198 .flags = IORESOURCE_MEM,
199 }, {
200
201 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
202 },
203 };
204
205 static struct smsc911x_platform_config smsc911x_info = {
206 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
207 SMSC911X_SAVE_MAC_ADDRESS,
208 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
209 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
210 .phy_interface = PHY_INTERFACE_MODE_MII,
211 };
212
213 static struct platform_device pcm037_eth = {
214 .name = "smsc911x",
215 .id = -1,
216 .num_resources = ARRAY_SIZE(smsc911x_resources),
217 .resource = smsc911x_resources,
218 .dev = {
219 .platform_data = &smsc911x_info,
220 },
221 };
222
223 static struct platdata_mtd_ram pcm038_sram_data = {
224 .bankwidth = 2,
225 };
226
227 static struct resource pcm038_sram_resource = {
228 .start = MX31_CS4_BASE_ADDR,
229 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
230 .flags = IORESOURCE_MEM,
231 };
232
233 static struct platform_device pcm037_sram_device = {
234 .name = "mtd-ram",
235 .id = 0,
236 .dev = {
237 .platform_data = &pcm038_sram_data,
238 },
239 .num_resources = 1,
240 .resource = &pcm038_sram_resource,
241 };
242
243 static const struct mxc_nand_platform_data
244 pcm037_nand_board_info __initconst = {
245 .width = 1,
246 .hw_ecc = 1,
247 };
248
249 static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
250 .bitrate = 100000,
251 };
252
253 static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
254 .bitrate = 20000,
255 };
256
257 static const struct property_entry board_eeprom_properties[] = {
258 PROPERTY_ENTRY_U32("pagesize", 32),
259 { }
260 };
261
262 static struct i2c_board_info pcm037_i2c_devices[] = {
263 {
264 I2C_BOARD_INFO("24c32", 0x52),
265 .properties = board_eeprom_properties,
266 }, {
267 I2C_BOARD_INFO("pcf8563", 0x51),
268 }
269 };
270
271
272 #ifdef PCM970_SDHC_RW_SWITCH
273 static int pcm970_sdhc1_get_ro(struct device *dev)
274 {
275 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
276 }
277 #endif
278
279 #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
280 #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
281
282 static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
283 void *data)
284 {
285 int ret;
286
287 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
288 if (ret)
289 return ret;
290
291 gpio_direction_input(SDHC1_GPIO_DET);
292
293 #ifdef PCM970_SDHC_RW_SWITCH
294 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
295 if (ret)
296 goto err_gpio_free;
297 gpio_direction_input(SDHC1_GPIO_WP);
298 #endif
299
300 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
301 IRQF_TRIGGER_FALLING, "sdhc-detect", data);
302 if (ret)
303 goto err_gpio_free_2;
304
305 return 0;
306
307 err_gpio_free_2:
308 #ifdef PCM970_SDHC_RW_SWITCH
309 gpio_free(SDHC1_GPIO_WP);
310 err_gpio_free:
311 #endif
312 gpio_free(SDHC1_GPIO_DET);
313
314 return ret;
315 }
316
317 static void pcm970_sdhc1_exit(struct device *dev, void *data)
318 {
319 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
320 gpio_free(SDHC1_GPIO_DET);
321 gpio_free(SDHC1_GPIO_WP);
322 }
323
324 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
325 #ifdef PCM970_SDHC_RW_SWITCH
326 .get_ro = pcm970_sdhc1_get_ro,
327 #endif
328 .init = pcm970_sdhc1_init,
329 .exit = pcm970_sdhc1_exit,
330 };
331
332 static struct platform_device *devices[] __initdata = {
333 &pcm037_flash,
334 &pcm037_sram_device,
335 };
336
337 static const struct fb_videomode fb_modedb[] = {
338 {
339
340 .name = "Sharp-LQ035Q7DH06-QVGA",
341 .refresh = 60,
342 .xres = 240,
343 .yres = 320,
344 .pixclock = 185925,
345 .left_margin = 9,
346 .right_margin = 16,
347 .upper_margin = 7,
348 .lower_margin = 9,
349 .hsync_len = 1,
350 .vsync_len = 1,
351 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
352 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
353 .vmode = FB_VMODE_NONINTERLACED,
354 .flag = 0,
355 }, {
356
357 .name = "TX090",
358 .refresh = 60,
359 .xres = 240,
360 .yres = 320,
361 .pixclock = 38255,
362 .left_margin = 144,
363 .right_margin = 0,
364 .upper_margin = 7,
365 .lower_margin = 40,
366 .hsync_len = 96,
367 .vsync_len = 1,
368 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
369 .vmode = FB_VMODE_NONINTERLACED,
370 .flag = 0,
371 }, {
372
373 .name = "CMEL-OLED",
374 .refresh = 60,
375 .xres = 240,
376 .yres = 320,
377 .pixclock = 185925,
378 .left_margin = 9,
379 .right_margin = 16,
380 .upper_margin = 7,
381 .lower_margin = 9,
382 .hsync_len = 1,
383 .vsync_len = 1,
384 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
385 .vmode = FB_VMODE_NONINTERLACED,
386 .flag = 0,
387 },
388 };
389
390 static struct mx3fb_platform_data mx3fb_pdata = {
391 .name = "Sharp-LQ035Q7DH06-QVGA",
392 .mode = fb_modedb,
393 .num_modes = ARRAY_SIZE(fb_modedb),
394 };
395
396 static struct resource pcm970_sja1000_resources[] = {
397 {
398 .start = MX31_CS5_BASE_ADDR,
399 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
400 .flags = IORESOURCE_MEM,
401 }, {
402
403 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
404 },
405 };
406
407 struct sja1000_platform_data pcm970_sja1000_platform_data = {
408 .osc_freq = 16000000,
409 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
410 .cdr = CDR_CBP,
411 };
412
413 static struct platform_device pcm970_sja1000 = {
414 .name = "sja1000_platform",
415 .dev = {
416 .platform_data = &pcm970_sja1000_platform_data,
417 },
418 .resource = pcm970_sja1000_resources,
419 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
420 };
421
422 static int pcm037_otg_init(struct platform_device *pdev)
423 {
424 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
425 }
426
427 static struct mxc_usbh_platform_data otg_pdata __initdata = {
428 .init = pcm037_otg_init,
429 .portsc = MXC_EHCI_MODE_ULPI,
430 };
431
432 static int pcm037_usbh2_init(struct platform_device *pdev)
433 {
434 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
435 }
436
437 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
438 .init = pcm037_usbh2_init,
439 .portsc = MXC_EHCI_MODE_ULPI,
440 };
441
442 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
443 .operating_mode = FSL_USB2_DR_DEVICE,
444 .phy_mode = FSL_USB2_PHY_ULPI,
445 };
446
447 static bool otg_mode_host __initdata;
448
449 static int __init pcm037_otg_mode(char *options)
450 {
451 if (!strcmp(options, "host"))
452 otg_mode_host = true;
453 else if (!strcmp(options, "device"))
454 otg_mode_host = false;
455 else
456 pr_info("otg_mode neither \"host\" nor \"device\". "
457 "Defaulting to device\n");
458 return 1;
459 }
460 __setup("otg_mode=", pcm037_otg_mode);
461
462 static struct regulator_consumer_supply dummy_supplies[] = {
463 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
464 REGULATOR_SUPPLY("vddvario", "smsc911x"),
465 };
466
467
468
469
470 static void __init pcm037_init(void)
471 {
472 imx31_soc_init();
473
474 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
475
476 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
477
478 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
479 "pcm037");
480
481 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
482 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
483
484 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
485 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
486 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
487 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
488 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG);
489 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG);
490 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);
491 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);
492 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);
493 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);
494 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);
495 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);
496
497 if (pcm037_variant() == PCM037_EET)
498 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
499 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
500 else
501 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
502 ARRAY_SIZE(pcm037_uart1_handshake_pins),
503 "pcm037_uart1");
504
505 platform_add_devices(devices, ARRAY_SIZE(devices));
506
507 imx31_add_imx2_wdt();
508 imx31_add_imx_uart0(&uart_pdata);
509
510 imx31_add_imx_uart1(&uart_pdata);
511 imx31_add_imx_uart2(&uart_pdata);
512
513 imx31_add_mxc_w1();
514
515
516 i2c_register_board_info(1, pcm037_i2c_devices,
517 ARRAY_SIZE(pcm037_i2c_devices));
518
519 imx31_add_imx_i2c1(&pcm037_i2c1_data);
520 imx31_add_imx_i2c2(&pcm037_i2c2_data);
521
522 imx31_add_mxc_nand(&pcm037_nand_board_info);
523 imx31_add_ipu_core();
524 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
525
526 if (otg_mode_host) {
527 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
528 ULPI_OTG_DRVVBUS_EXT);
529 if (otg_pdata.otg)
530 imx31_add_mxc_ehci_otg(&otg_pdata);
531 }
532
533 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
534 ULPI_OTG_DRVVBUS_EXT);
535 if (usbh2_pdata.otg)
536 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
537
538 if (!otg_mode_host)
539 imx31_add_fsl_usb2_udc(&otg_device_pdata);
540 }
541
542 static void __init pcm037_timer_init(void)
543 {
544 mx31_clocks_init(26000000);
545 }
546
547 static void __init pcm037_init_late(void)
548 {
549 int ret;
550
551
552 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
553 if (!ret) {
554 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
555 smsc911x_resources[1].start =
556 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
557 smsc911x_resources[1].end =
558 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
559 platform_device_register(&pcm037_eth);
560 } else {
561 pr_warn("could not get LAN irq gpio\n");
562 }
563
564 imx31_add_mxc_mmc(0, &sdhc_pdata);
565
566 pcm970_sja1000_resources[1].start =
567 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
568 pcm970_sja1000_resources[1].end =
569 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
570 platform_device_register(&pcm970_sja1000);
571
572 pcm037_eet_init_devices();
573 }
574
575 MACHINE_START(PCM037, "Phytec Phycore pcm037")
576
577 .atag_offset = 0x100,
578 .map_io = mx31_map_io,
579 .init_early = imx31_init_early,
580 .init_irq = mx31_init_irq,
581 .init_time = pcm037_timer_init,
582 .init_machine = pcm037_init,
583 .init_late = pcm037_init_late,
584 .restart = mxc_restart,
585 MACHINE_END