This source file includes following definitions.
- mxc_set_cpu_type
- imx_set_soc_revision
- imx_get_soc_revision
- imx_print_silicon_rev
- imx_set_aips
- imx_aips_allow_unprivileged_access
- imx_soc_device_init
1
2 #include <linux/err.h>
3 #include <linux/module.h>
4 #include <linux/io.h>
5 #include <linux/of.h>
6 #include <linux/of_address.h>
7 #include <linux/slab.h>
8 #include <linux/sys_soc.h>
9
10 #include "hardware.h"
11 #include "common.h"
12
13 unsigned int __mxc_cpu_type;
14 static unsigned int imx_soc_revision;
15
16 void mxc_set_cpu_type(unsigned int type)
17 {
18 __mxc_cpu_type = type;
19 }
20
21 void imx_set_soc_revision(unsigned int rev)
22 {
23 imx_soc_revision = rev;
24 }
25
26 unsigned int imx_get_soc_revision(void)
27 {
28 return imx_soc_revision;
29 }
30
31 void imx_print_silicon_rev(const char *cpu, int srev)
32 {
33 if (srev == IMX_CHIP_REVISION_UNKNOWN)
34 pr_info("CPU identified as %s, unknown revision\n", cpu);
35 else
36 pr_info("CPU identified as %s, silicon rev %d.%d\n",
37 cpu, (srev >> 4) & 0xf, srev & 0xf);
38 }
39
40 void __init imx_set_aips(void __iomem *base)
41 {
42 unsigned int reg;
43
44
45
46
47 imx_writel(0x77777777, base + 0x0);
48 imx_writel(0x77777777, base + 0x4);
49
50
51
52
53
54
55 imx_writel(0x0, base + 0x40);
56 imx_writel(0x0, base + 0x44);
57 imx_writel(0x0, base + 0x48);
58 imx_writel(0x0, base + 0x4C);
59 reg = imx_readl(base + 0x50) & 0x00FFFFFF;
60 imx_writel(reg, base + 0x50);
61 }
62
63 void __init imx_aips_allow_unprivileged_access(
64 const char *compat)
65 {
66 void __iomem *aips_base_addr;
67 struct device_node *np;
68
69 for_each_compatible_node(np, NULL, compat) {
70 aips_base_addr = of_iomap(np, 0);
71 WARN_ON(!aips_base_addr);
72 imx_set_aips(aips_base_addr);
73 }
74 }
75
76 struct device * __init imx_soc_device_init(void)
77 {
78 struct soc_device_attribute *soc_dev_attr;
79 struct soc_device *soc_dev;
80 struct device_node *root;
81 const char *soc_id;
82 int ret;
83
84 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
85 if (!soc_dev_attr)
86 return NULL;
87
88 soc_dev_attr->family = "Freescale i.MX";
89
90 root = of_find_node_by_path("/");
91 ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
92 of_node_put(root);
93 if (ret)
94 goto free_soc;
95
96 switch (__mxc_cpu_type) {
97 case MXC_CPU_MX1:
98 soc_id = "i.MX1";
99 break;
100 case MXC_CPU_MX21:
101 soc_id = "i.MX21";
102 break;
103 case MXC_CPU_MX25:
104 soc_id = "i.MX25";
105 break;
106 case MXC_CPU_MX27:
107 soc_id = "i.MX27";
108 break;
109 case MXC_CPU_MX31:
110 soc_id = "i.MX31";
111 break;
112 case MXC_CPU_MX35:
113 soc_id = "i.MX35";
114 break;
115 case MXC_CPU_MX51:
116 soc_id = "i.MX51";
117 break;
118 case MXC_CPU_MX53:
119 soc_id = "i.MX53";
120 break;
121 case MXC_CPU_IMX6SL:
122 soc_id = "i.MX6SL";
123 break;
124 case MXC_CPU_IMX6DL:
125 soc_id = "i.MX6DL";
126 break;
127 case MXC_CPU_IMX6SX:
128 soc_id = "i.MX6SX";
129 break;
130 case MXC_CPU_IMX6Q:
131 soc_id = "i.MX6Q";
132 break;
133 case MXC_CPU_IMX6UL:
134 soc_id = "i.MX6UL";
135 break;
136 case MXC_CPU_IMX6ULL:
137 soc_id = "i.MX6ULL";
138 break;
139 case MXC_CPU_IMX6ULZ:
140 soc_id = "i.MX6ULZ";
141 break;
142 case MXC_CPU_IMX6SLL:
143 soc_id = "i.MX6SLL";
144 break;
145 case MXC_CPU_IMX7D:
146 soc_id = "i.MX7D";
147 break;
148 case MXC_CPU_IMX7ULP:
149 soc_id = "i.MX7ULP";
150 break;
151 default:
152 soc_id = "Unknown";
153 }
154 soc_dev_attr->soc_id = soc_id;
155
156 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
157 (imx_soc_revision >> 4) & 0xf,
158 imx_soc_revision & 0xf);
159 if (!soc_dev_attr->revision)
160 goto free_soc;
161
162 soc_dev = soc_device_register(soc_dev_attr);
163 if (IS_ERR(soc_dev))
164 goto free_rev;
165
166 return soc_device_to_device(soc_dev);
167
168 free_rev:
169 kfree(soc_dev_attr->revision);
170 free_soc:
171 kfree(soc_dev_attr);
172 return NULL;
173 }