This source file includes following definitions.
- omap2_prm_read_mod_reg
- omap2_prm_write_mod_reg
- omap2_prm_rmw_mod_reg_bits
- omap2_prm_read_mod_bits_shift
- omap2_prm_set_mod_reg_bits
- omap2_prm_clear_mod_reg_bits
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13 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
14 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
15
16 #include "prcm-common.h"
17 #include "prm.h"
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31 #define OMAP2_RM_RSTCTRL 0x0050
32 #define OMAP2_RM_RSTTIME 0x0054
33 #define OMAP2_RM_RSTST 0x0058
34 #define OMAP2_PM_PWSTCTRL 0x00e0
35 #define OMAP2_PM_PWSTST 0x00e4
36
37 #define PM_WKEN 0x00a0
38 #define PM_WKEN1 PM_WKEN
39 #define PM_WKST 0x00b0
40 #define PM_WKST1 PM_WKST
41 #define PM_WKDEP 0x00c8
42 #define PM_EVGENCTRL 0x00d4
43 #define PM_EVGENONTIM 0x00d8
44 #define PM_EVGENOFFTIM 0x00dc
45
46
47 #ifndef __ASSEMBLER__
48
49 #include <linux/io.h>
50 #include "powerdomain.h"
51
52
53 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
54 {
55 return readl_relaxed(prm_base.va + module + idx);
56 }
57
58 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
59 {
60 writel_relaxed(val, prm_base.va + module + idx);
61 }
62
63
64 static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
65 s16 idx)
66 {
67 u32 v;
68
69 v = omap2_prm_read_mod_reg(module, idx);
70 v &= ~mask;
71 v |= bits;
72 omap2_prm_write_mod_reg(v, module, idx);
73
74 return v;
75 }
76
77
78 static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
79 {
80 u32 v;
81
82 v = omap2_prm_read_mod_reg(domain, idx);
83 v &= mask;
84 v >>= __ffs(mask);
85
86 return v;
87 }
88
89 static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
90 {
91 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
92 }
93
94 static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
95 {
96 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
97 }
98
99
100 int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
101 int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
102 u16 offset);
103 int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
104 s16 prm_mod, u16 reset_offset,
105 u16 st_offset);
106
107 extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
108 extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
109 extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
110 extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
111 u8 pwrst);
112 extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
113 u8 pwrst);
114 extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
115 extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
116 extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
117 extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
118
119 extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
120 struct clockdomain *clkdm2);
121 extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
122 struct clockdomain *clkdm2);
123 extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
124 struct clockdomain *clkdm2);
125 extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
126
127 #endif
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138 #define OMAP_ONTIMEVAL_SHIFT 0
139 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
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143 #define OMAP_OFFTIMEVAL_SHIFT 0
144 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
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147
148 #define OMAP_SETUP_TIME_SHIFT 0
149 #define OMAP_SETUP_TIME_MASK (0xffff << 0)
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153 #define OMAP_SYSCLKDIV_SHIFT 6
154 #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
155 #define OMAP_SYSCLKDIV_WIDTH 2
156 #define OMAP_AUTOEXTCLKMODE_SHIFT 3
157 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
158 #define OMAP_SYSCLKSEL_SHIFT 0
159 #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
160
161
162 #define OMAP_OFFLOADMODE_SHIFT 3
163 #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
164 #define OMAP_ONLOADMODE_SHIFT 1
165 #define OMAP_ONLOADMODE_MASK (0x3 << 1)
166 #define OMAP_ENABLE_MASK (1 << 0)
167
168
169
170 #define OMAP_RSTTIME2_SHIFT 8
171 #define OMAP_RSTTIME2_MASK (0x1f << 8)
172 #define OMAP_RSTTIME1_SHIFT 0
173 #define OMAP_RSTTIME1_MASK (0xff << 0)
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178 #define OMAP_RST_DPLL3_MASK (1 << 2)
179 #define OMAP_RST_GS_MASK (1 << 1)
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195
196 #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
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205 #define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
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214
215 #define OMAP_GLOBALWARM_RST_SHIFT 1
216 #define OMAP_GLOBALWARM_RST_MASK (1 << 1)
217 #define OMAP_GLOBALCOLD_RST_SHIFT 0
218 #define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
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228
229 #define OMAP_EN_WKUP_SHIFT 4
230 #define OMAP_EN_WKUP_MASK (1 << 4)
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241
242 #define OMAP_LOGICRETSTATE_MASK (1 << 2)
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244
245 #endif