root/arch/arm/mach-shmobile/pm-rcar-gen2.c

DEFINITIONS

1. phys_to_sbar
2. rcar_gen2_pm_init

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R-Car Generation 2 Power management support
   4  *
   5  * Copyright (C) 2013 - 2015  Renesas Electronics Corporation
   6  * Copyright (C) 2011  Renesas Solutions Corp.
   7  * Copyright (C) 2011  Magnus Damm
   8  */
   9 
  10 #include <linux/kernel.h>
  11 #include <linux/ioport.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/smp.h>
  15 #include <asm/io.h>
  16 #include <asm/cputype.h>
  17 #include "common.h"
  18 #include "rcar-gen2.h"
  19 
  20 /* RST */
  21 #define RST             0xe6160000
  22 
  23 #define CA15BAR         0x0020          /* CA15 Boot Address Register */
  24 #define CA7BAR          0x0030          /* CA7 Boot Address Register */
  25 #define CA15RESCNT      0x0040          /* CA15 Reset Control Register */
  26 #define CA7RESCNT       0x0044          /* CA7 Reset Control Register */
  27 
  28 /* SYS Boot Address Register */
  29 #define SBAR_BAREN      BIT(4)          /* SBAR is valid */
  30 
  31 /* Reset Control Registers */
  32 #define CA15RESCNT_CODE 0xa5a50000
  33 #define CA15RESCNT_CPUS 0xf             /* CPU0-3 */
  34 #define CA7RESCNT_CODE  0x5a5a0000
  35 #define CA7RESCNT_CPUS  0xf             /* CPU0-3 */
  36 
  37 /* On-chip RAM */
  38 #define ICRAM1          0xe63c0000      /* Inter Connect RAM1 (4 KiB) */
  39 
  40 static inline u32 phys_to_sbar(phys_addr_t addr)
  41 {
  42         return (addr >> 8) & 0xfffffc00;
  43 }
  44 
  45 void __init rcar_gen2_pm_init(void)
  46 {
  47         void __iomem *p;
  48         u32 bar;
  49         static int once;
  50         struct device_node *np;
  51         bool has_a7 = false;
  52         bool has_a15 = false;
  53         struct resource res;
  54         int error;
  55 
  56         if (once++)
  57                 return;
  58 
  59         for_each_of_cpu_node(np) {
  60                 if (of_device_is_compatible(np, "arm,cortex-a15"))
  61                         has_a15 = true;
  62                 else if (of_device_is_compatible(np, "arm,cortex-a7"))
  63                         has_a7 = true;
  64         }
  65 
  66         np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
  67         if (!np) {
  68                 /* No smp-sram in DT, fall back to hardcoded address */
  69                 res = (struct resource)DEFINE_RES_MEM(ICRAM1,
  70                                                       shmobile_boot_size);
  71                 goto map;
  72         }
  73 
  74         error = of_address_to_resource(np, 0, &res);
  75         of_node_put(np);
  76         if (error) {
  77                 pr_err("Failed to get smp-sram address: %d\n", error);
  78                 return;
  79         }
  80 
  81 map:
  82         /* RAM for jump stub, because BAR requires 256KB aligned address */
  83         if (res.start & (256 * 1024 - 1) ||
  84             resource_size(&res) < shmobile_boot_size) {
  85                 pr_err("Invalid smp-sram region\n");
  86                 return;
  87         }
  88 
  89         p = ioremap(res.start, resource_size(&res));
  90         if (!p)
  91                 return;
  92         /*
  93          * install the reset vector, use the largest version if we have enough
  94          * memory available
  95          */
  96         if (resource_size(&res) >= shmobile_boot_size_gen2) {
  97                 shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
  98                 memcpy_toio(p, shmobile_boot_vector_gen2,
  99                             shmobile_boot_size_gen2);
 100         } else {
 101                 memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
 102         }
 103         iounmap(p);
 104 
 105         /* setup reset vectors */
 106         p = ioremap_nocache(RST, 0x63);
 107         bar = phys_to_sbar(res.start);
 108         if (has_a15) {
 109                 writel_relaxed(bar, p + CA15BAR);
 110                 writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
 111 
 112                 /* de-assert reset for CA15 CPUs */
 113                 writel_relaxed((readl_relaxed(p + CA15RESCNT) &
 114                                 ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
 115                                p + CA15RESCNT);
 116         }
 117         if (has_a7) {
 118                 writel_relaxed(bar, p + CA7BAR);
 119                 writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
 120 
 121                 /* de-assert reset for CA7 CPUs */
 122                 writel_relaxed((readl_relaxed(p + CA7RESCNT) &
 123                                 ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
 124                                p + CA7RESCNT);
 125         }
 126         iounmap(p);
 127 
 128         shmobile_smp_apmu_suspend_init();
 129 }