root/arch/arm/include/asm/hardware/sa1111.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * arch/arm/include/asm/hardware/sa1111.h
   4  *
   5  * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
   6  *
   7  * This file contains definitions for the SA-1111 Companion Chip.
   8  * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
   9  *
  10  * Macro that calculates real address for registers in the SA-1111
  11  */
  12 
  13 #ifndef _ASM_ARCH_SA1111
  14 #define _ASM_ARCH_SA1111
  15 
  16 #include <mach/bitfield.h>
  17 
  18 /*
  19  * Don't ask the (SAC) DMA engines to move less than this amount.
  20  */
  21 
  22 #define SA1111_SAC_DMA_MIN_XFER (0x800)
  23 
  24 /*
  25  * System Bus Interface (SBI)
  26  *
  27  * Registers
  28  *    SKCR      Control Register
  29  *    SMCR      Shared Memory Controller Register
  30  *    SKID      ID Register
  31  */
  32 #define SA1111_SKCR     0x0000
  33 #define SA1111_SMCR     0x0004
  34 #define SA1111_SKID     0x0008
  35 
  36 #define SKCR_PLL_BYPASS (1<<0)
  37 #define SKCR_RCLKEN     (1<<1)
  38 #define SKCR_SLEEP      (1<<2)
  39 #define SKCR_DOZE       (1<<3)
  40 #define SKCR_VCO_OFF    (1<<4)
  41 #define SKCR_SCANTSTEN  (1<<5)
  42 #define SKCR_CLKTSTEN   (1<<6)
  43 #define SKCR_RDYEN      (1<<7)
  44 #define SKCR_SELAC      (1<<8)
  45 #define SKCR_OPPC       (1<<9)
  46 #define SKCR_PLLTSTEN   (1<<10)
  47 #define SKCR_USBIOTSTEN (1<<11)
  48 /*
  49  * Don't believe the specs!  Take them, throw them outside.  Leave them
  50  * there for a week.  Spit on them.  Walk on them.  Stamp on them.
  51  * Pour gasoline over them and finally burn them.  Now think about coding.
  52  *  - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
  53  *  - The Feb 2001 errata (278260-010) says that the previous errata
  54  *    (278260-009) is wrong, and its bit actually 12, fixed in spec
  55  *    278242-003.
  56  *  - The SA1111 manual (278242) says bit 12, but 0 to enable.
  57  *  - Reality is bit 13, 1 to enable.
  58  *      -- rmk
  59  */
  60 #define SKCR_OE_EN      (1<<13)
  61 
  62 #define SMCR_DTIM       (1<<0)
  63 #define SMCR_MBGE       (1<<1)
  64 #define SMCR_DRAC_0     (1<<2)
  65 #define SMCR_DRAC_1     (1<<3)
  66 #define SMCR_DRAC_2     (1<<4)
  67 #define SMCR_DRAC       Fld(3, 2)
  68 #define SMCR_CLAT       (1<<5)
  69 
  70 #define SKID_SIREV_MASK (0x000000f0)
  71 #define SKID_MTREV_MASK (0x0000000f)
  72 #define SKID_ID_MASK    (0xffffff00)
  73 #define SKID_SA1111_ID  (0x690cc200)
  74 
  75 /*
  76  * System Controller
  77  *
  78  * Registers
  79  *    SKPCR     Power Control Register
  80  *    SKCDR     Clock Divider Register
  81  *    SKAUD     Audio Clock Divider Register
  82  *    SKPMC     PS/2 Mouse Clock Divider Register
  83  *    SKPTC     PS/2 Track Pad Clock Divider Register
  84  *    SKPEN0    PWM0 Enable Register
  85  *    SKPWM0    PWM0 Clock Register
  86  *    SKPEN1    PWM1 Enable Register
  87  *    SKPWM1    PWM1 Clock Register
  88  */
  89 #define SA1111_SKPCR    0x0200
  90 #define SA1111_SKCDR    0x0204
  91 #define SA1111_SKAUD    0x0208
  92 #define SA1111_SKPMC    0x020c
  93 #define SA1111_SKPTC    0x0210
  94 #define SA1111_SKPEN0   0x0214
  95 #define SA1111_SKPWM0   0x0218
  96 #define SA1111_SKPEN1   0x021c
  97 #define SA1111_SKPWM1   0x0220
  98 
  99 #define SKPCR_UCLKEN    (1<<0)
 100 #define SKPCR_ACCLKEN   (1<<1)
 101 #define SKPCR_I2SCLKEN  (1<<2)
 102 #define SKPCR_L3CLKEN   (1<<3)
 103 #define SKPCR_SCLKEN    (1<<4)
 104 #define SKPCR_PMCLKEN   (1<<5)
 105 #define SKPCR_PTCLKEN   (1<<6)
 106 #define SKPCR_DCLKEN    (1<<7)
 107 #define SKPCR_PWMCLKEN  (1<<8)
 108 
 109 /* USB Host controller */
 110 #define SA1111_USB              0x0400
 111 
 112 /*
 113  * Serial Audio Controller
 114  *
 115  * Registers
 116  *    SACR0             Serial Audio Common Control Register
 117  *    SACR1             Serial Audio Alternate Mode (I2C/MSB) Control Register
 118  *    SACR2             Serial Audio AC-link Control Register
 119  *    SASR0             Serial Audio I2S/MSB Interface & FIFO Status Register
 120  *    SASR1             Serial Audio AC-link Interface & FIFO Status Register
 121  *    SASCR             Serial Audio Status Clear Register
 122  *    L3_CAR            L3 Control Bus Address Register
 123  *    L3_CDR            L3 Control Bus Data Register
 124  *    ACCAR             AC-link Command Address Register
 125  *    ACCDR             AC-link Command Data Register
 126  *    ACSAR             AC-link Status Address Register
 127  *    ACSDR             AC-link Status Data Register
 128  *    SADTCS            Serial Audio DMA Transmit Control/Status Register
 129  *    SADTSA            Serial Audio DMA Transmit Buffer Start Address A
 130  *    SADTCA            Serial Audio DMA Transmit Buffer Count Register A
 131  *    SADTSB            Serial Audio DMA Transmit Buffer Start Address B
 132  *    SADTCB            Serial Audio DMA Transmit Buffer Count Register B
 133  *    SADRCS            Serial Audio DMA Receive Control/Status Register
 134  *    SADRSA            Serial Audio DMA Receive Buffer Start Address A
 135  *    SADRCA            Serial Audio DMA Receive Buffer Count Register A
 136  *    SADRSB            Serial Audio DMA Receive Buffer Start Address B
 137  *    SADRCB            Serial Audio DMA Receive Buffer Count Register B
 138  *    SAITR             Serial Audio Interrupt Test Register
 139  *    SADR              Serial Audio Data Register (16 x 32-bit)
 140  */
 141 
 142 #define SA1111_SERAUDIO         0x0600
 143 
 144 /*
 145  * These are offsets from the above base.
 146  */
 147 #define SA1111_SACR0            0x00
 148 #define SA1111_SACR1            0x04
 149 #define SA1111_SACR2            0x08
 150 #define SA1111_SASR0            0x0c
 151 #define SA1111_SASR1            0x10
 152 #define SA1111_SASCR            0x18
 153 #define SA1111_L3_CAR           0x1c
 154 #define SA1111_L3_CDR           0x20
 155 #define SA1111_ACCAR            0x24
 156 #define SA1111_ACCDR            0x28
 157 #define SA1111_ACSAR            0x2c
 158 #define SA1111_ACSDR            0x30
 159 #define SA1111_SADTCS           0x34
 160 #define SA1111_SADTSA           0x38
 161 #define SA1111_SADTCA           0x3c
 162 #define SA1111_SADTSB           0x40
 163 #define SA1111_SADTCB           0x44
 164 #define SA1111_SADRCS           0x48
 165 #define SA1111_SADRSA           0x4c
 166 #define SA1111_SADRCA           0x50
 167 #define SA1111_SADRSB           0x54
 168 #define SA1111_SADRCB           0x58
 169 #define SA1111_SAITR            0x5c
 170 #define SA1111_SADR             0x80
 171 
 172 #ifndef CONFIG_ARCH_PXA
 173 
 174 #define SACR0_ENB       (1<<0)
 175 #define SACR0_BCKD      (1<<2)
 176 #define SACR0_RST       (1<<3)
 177 
 178 #define SACR1_AMSL      (1<<0)
 179 #define SACR1_L3EN      (1<<1)
 180 #define SACR1_L3MB      (1<<2)
 181 #define SACR1_DREC      (1<<3)
 182 #define SACR1_DRPL      (1<<4)
 183 #define SACR1_ENLBF     (1<<5)
 184 
 185 #define SACR2_TS3V      (1<<0)
 186 #define SACR2_TS4V      (1<<1)
 187 #define SACR2_WKUP      (1<<2)
 188 #define SACR2_DREC      (1<<3)
 189 #define SACR2_DRPL      (1<<4)
 190 #define SACR2_ENLBF     (1<<5)
 191 #define SACR2_RESET     (1<<6)
 192 
 193 #define SASR0_TNF       (1<<0)
 194 #define SASR0_RNE       (1<<1)
 195 #define SASR0_BSY       (1<<2)
 196 #define SASR0_TFS       (1<<3)
 197 #define SASR0_RFS       (1<<4)
 198 #define SASR0_TUR       (1<<5)
 199 #define SASR0_ROR       (1<<6)
 200 #define SASR0_L3WD      (1<<16)
 201 #define SASR0_L3RD      (1<<17)
 202 
 203 #define SASR1_TNF       (1<<0)
 204 #define SASR1_RNE       (1<<1)
 205 #define SASR1_BSY       (1<<2)
 206 #define SASR1_TFS       (1<<3)
 207 #define SASR1_RFS       (1<<4)
 208 #define SASR1_TUR       (1<<5)
 209 #define SASR1_ROR       (1<<6)
 210 #define SASR1_CADT      (1<<16)
 211 #define SASR1_SADR      (1<<17)
 212 #define SASR1_RSTO      (1<<18)
 213 #define SASR1_CLPM      (1<<19)
 214 #define SASR1_CRDY      (1<<20)
 215 #define SASR1_RS3V      (1<<21)
 216 #define SASR1_RS4V      (1<<22)
 217 
 218 #define SASCR_TUR       (1<<5)
 219 #define SASCR_ROR       (1<<6)
 220 #define SASCR_DTS       (1<<16)
 221 #define SASCR_RDD       (1<<17)
 222 #define SASCR_STO       (1<<18)
 223 
 224 #define SADTCS_TDEN     (1<<0)
 225 #define SADTCS_TDIE     (1<<1)
 226 #define SADTCS_TDBDA    (1<<3)
 227 #define SADTCS_TDSTA    (1<<4)
 228 #define SADTCS_TDBDB    (1<<5)
 229 #define SADTCS_TDSTB    (1<<6)
 230 #define SADTCS_TBIU     (1<<7)
 231 
 232 #define SADRCS_RDEN     (1<<0)
 233 #define SADRCS_RDIE     (1<<1)
 234 #define SADRCS_RDBDA    (1<<3)
 235 #define SADRCS_RDSTA    (1<<4)
 236 #define SADRCS_RDBDB    (1<<5)
 237 #define SADRCS_RDSTB    (1<<6)
 238 #define SADRCS_RBIU     (1<<7)
 239 
 240 #define SAD_CS_DEN      (1<<0)
 241 #define SAD_CS_DIE      (1<<1)  /* Not functional on metal 1 */
 242 #define SAD_CS_DBDA     (1<<3)  /* Not functional on metal 1 */
 243 #define SAD_CS_DSTA     (1<<4)
 244 #define SAD_CS_DBDB     (1<<5)  /* Not functional on metal 1 */
 245 #define SAD_CS_DSTB     (1<<6)
 246 #define SAD_CS_BIU      (1<<7)  /* Not functional on metal 1 */
 247 
 248 #define SAITR_TFS       (1<<0)
 249 #define SAITR_RFS       (1<<1)
 250 #define SAITR_TUR       (1<<2)
 251 #define SAITR_ROR       (1<<3)
 252 #define SAITR_CADT      (1<<4)
 253 #define SAITR_SADR      (1<<5)
 254 #define SAITR_RSTO      (1<<6)
 255 #define SAITR_TDBDA     (1<<8)
 256 #define SAITR_TDBDB     (1<<9)
 257 #define SAITR_RDBDA     (1<<10)
 258 #define SAITR_RDBDB     (1<<11)
 259 
 260 #endif  /* !CONFIG_ARCH_PXA */
 261 
 262 /*
 263  * General-Purpose I/O Interface
 264  *
 265  * Registers
 266  *    PA_DDR            GPIO Block A Data Direction
 267  *    PA_DRR/PA_DWR     GPIO Block A Data Value Register (read/write)
 268  *    PA_SDR            GPIO Block A Sleep Direction
 269  *    PA_SSR            GPIO Block A Sleep State
 270  *    PB_DDR            GPIO Block B Data Direction
 271  *    PB_DRR/PB_DWR     GPIO Block B Data Value Register (read/write)
 272  *    PB_SDR            GPIO Block B Sleep Direction
 273  *    PB_SSR            GPIO Block B Sleep State
 274  *    PC_DDR            GPIO Block C Data Direction
 275  *    PC_DRR/PC_DWR     GPIO Block C Data Value Register (read/write)
 276  *    PC_SDR            GPIO Block C Sleep Direction
 277  *    PC_SSR            GPIO Block C Sleep State
 278  */
 279 
 280 #define SA1111_GPIO     0x1000
 281 
 282 #define SA1111_GPIO_PADDR       (0x000)
 283 #define SA1111_GPIO_PADRR       (0x004)
 284 #define SA1111_GPIO_PADWR       (0x004)
 285 #define SA1111_GPIO_PASDR       (0x008)
 286 #define SA1111_GPIO_PASSR       (0x00c)
 287 #define SA1111_GPIO_PBDDR       (0x010)
 288 #define SA1111_GPIO_PBDRR       (0x014)
 289 #define SA1111_GPIO_PBDWR       (0x014)
 290 #define SA1111_GPIO_PBSDR       (0x018)
 291 #define SA1111_GPIO_PBSSR       (0x01c)
 292 #define SA1111_GPIO_PCDDR       (0x020)
 293 #define SA1111_GPIO_PCDRR       (0x024)
 294 #define SA1111_GPIO_PCDWR       (0x024)
 295 #define SA1111_GPIO_PCSDR       (0x028)
 296 #define SA1111_GPIO_PCSSR       (0x02c)
 297 
 298 #define GPIO_A0         (1 << 0)
 299 #define GPIO_A1         (1 << 1)
 300 #define GPIO_A2         (1 << 2)
 301 #define GPIO_A3         (1 << 3)
 302 
 303 #define GPIO_B0         (1 << 8)
 304 #define GPIO_B1         (1 << 9)
 305 #define GPIO_B2         (1 << 10)
 306 #define GPIO_B3         (1 << 11)
 307 #define GPIO_B4         (1 << 12)
 308 #define GPIO_B5         (1 << 13)
 309 #define GPIO_B6         (1 << 14)
 310 #define GPIO_B7         (1 << 15)
 311 
 312 #define GPIO_C0         (1 << 16)
 313 #define GPIO_C1         (1 << 17)
 314 #define GPIO_C2         (1 << 18)
 315 #define GPIO_C3         (1 << 19)
 316 #define GPIO_C4         (1 << 20)
 317 #define GPIO_C5         (1 << 21)
 318 #define GPIO_C6         (1 << 22)
 319 #define GPIO_C7         (1 << 23)
 320 
 321 /*
 322  * Interrupt Controller
 323  *
 324  * Registers
 325  *    INTTEST0          Test register 0
 326  *    INTTEST1          Test register 1
 327  *    INTEN0            Interrupt Enable register 0
 328  *    INTEN1            Interrupt Enable register 1
 329  *    INTPOL0           Interrupt Polarity selection 0
 330  *    INTPOL1           Interrupt Polarity selection 1
 331  *    INTTSTSEL         Interrupt source selection
 332  *    INTSTATCLR0       Interrupt Status/Clear 0
 333  *    INTSTATCLR1       Interrupt Status/Clear 1
 334  *    INTSET0           Interrupt source set 0
 335  *    INTSET1           Interrupt source set 1
 336  *    WAKE_EN0          Wake-up source enable 0
 337  *    WAKE_EN1          Wake-up source enable 1
 338  *    WAKE_POL0         Wake-up polarity selection 0
 339  *    WAKE_POL1         Wake-up polarity selection 1
 340  */
 341 #define SA1111_INTC             0x1600
 342 
 343 /*
 344  * These are offsets from the above base.
 345  */
 346 #define SA1111_INTTEST0         0x0000
 347 #define SA1111_INTTEST1         0x0004
 348 #define SA1111_INTEN0           0x0008
 349 #define SA1111_INTEN1           0x000c
 350 #define SA1111_INTPOL0          0x0010
 351 #define SA1111_INTPOL1          0x0014
 352 #define SA1111_INTTSTSEL        0x0018
 353 #define SA1111_INTSTATCLR0      0x001c
 354 #define SA1111_INTSTATCLR1      0x0020
 355 #define SA1111_INTSET0          0x0024
 356 #define SA1111_INTSET1          0x0028
 357 #define SA1111_WAKEEN0          0x002c
 358 #define SA1111_WAKEEN1          0x0030
 359 #define SA1111_WAKEPOL0         0x0034
 360 #define SA1111_WAKEPOL1         0x0038
 361 
 362 /* PS/2 Trackpad and Mouse Interfaces */
 363 #define SA1111_KBD              0x0a00
 364 #define SA1111_MSE              0x0c00
 365 
 366 /* PCMCIA Interface */
 367 #define SA1111_PCMCIA           0x1600
 368 
 369 
 370 
 371 
 372 
 373 extern struct bus_type sa1111_bus_type;
 374 
 375 #define SA1111_DEVID_SBI        (1 << 0)
 376 #define SA1111_DEVID_SK         (1 << 1)
 377 #define SA1111_DEVID_USB        (1 << 2)
 378 #define SA1111_DEVID_SAC        (1 << 3)
 379 #define SA1111_DEVID_SSP        (1 << 4)
 380 #define SA1111_DEVID_PS2        (3 << 5)
 381 #define SA1111_DEVID_PS2_KBD    (1 << 5)
 382 #define SA1111_DEVID_PS2_MSE    (1 << 6)
 383 #define SA1111_DEVID_GPIO       (1 << 7)
 384 #define SA1111_DEVID_INT        (1 << 8)
 385 #define SA1111_DEVID_PCMCIA     (1 << 9)
 386 
 387 struct sa1111_dev {
 388         struct device   dev;
 389         unsigned int    devid;
 390         struct resource res;
 391         void __iomem    *mapbase;
 392         unsigned int    skpcr_mask;
 393         unsigned int    hwirq[6];
 394         u64             dma_mask;
 395 };
 396 
 397 #define to_sa1111_device(x)     container_of(x, struct sa1111_dev, dev)
 398 
 399 #define sa1111_get_drvdata(d)   dev_get_drvdata(&(d)->dev)
 400 #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
 401 
 402 struct sa1111_driver {
 403         struct device_driver    drv;
 404         unsigned int            devid;
 405         int (*probe)(struct sa1111_dev *);
 406         int (*remove)(struct sa1111_dev *);
 407 };
 408 
 409 #define SA1111_DRV(_d)  container_of((_d), struct sa1111_driver, drv)
 410 
 411 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
 412 
 413 /*
 414  * These frob the SKPCR register, and call platform specific
 415  * enable/disable functions.
 416  */
 417 int sa1111_enable_device(struct sa1111_dev *);
 418 void sa1111_disable_device(struct sa1111_dev *);
 419 
 420 int sa1111_get_irq(struct sa1111_dev *, unsigned num);
 421 
 422 unsigned int sa1111_pll_clock(struct sa1111_dev *);
 423 
 424 #define SA1111_AUDIO_ACLINK     0
 425 #define SA1111_AUDIO_I2S        1
 426 
 427 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
 428 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
 429 int sa1111_get_audio_rate(struct sa1111_dev *sadev);
 430 
 431 int sa1111_check_dma_bug(dma_addr_t addr);
 432 
 433 int sa1111_driver_register(struct sa1111_driver *);
 434 void sa1111_driver_unregister(struct sa1111_driver *);
 435 
 436 struct sa1111_platform_data {
 437         int     irq_base;       /* base for cascaded on-chip IRQs */
 438         unsigned disable_devs;
 439         void    *data;
 440         int     (*enable)(void *, unsigned);
 441         void    (*disable)(void *, unsigned);
 442 };
 443 
 444 #endif  /* _ASM_ARCH_SA1111 */
/* [<][>][^][v][top][bottom][index][help] */