root/arch/arm/include/debug/exynos.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  */
   6 
   7 /* pull in the relevant register and map files. */
   8 
   9 #define S3C_ADDR_BASE   0xF6000000
  10 #define S3C_VA_UART     S3C_ADDR_BASE + 0x01000000
  11 #define EXYNOS4_PA_UART 0x13800000
  12 #define EXYNOS5_PA_UART 0x12C00000
  13 
  14         /* note, for the boot process to work we have to keep the UART
  15          * virtual address aligned to an 1MiB boundary for the L1
  16          * mapping the head code makes. We keep the UART virtual address
  17          * aligned and add in the offset when we load the value here.
  18          */
  19 
  20         .macro addruart, rp, rv, tmp
  21                 mrc     p15, 0, \tmp, c0, c0, 0
  22                 and     \tmp, \tmp, #0xf0
  23                 teq     \tmp, #0xf0             @@ A15
  24                 beq     100f
  25                 mrc     p15, 0, \tmp, c0, c0, 5
  26                 and     \tmp, \tmp, #0xf00
  27                 teq     \tmp, #0x100            @@ A15 + A7 but boot to A7
  28 100:            ldreq   \rp, =EXYNOS5_PA_UART
  29                 movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
  30                 ldr     \rv, =S3C_VA_UART
  31 #if CONFIG_DEBUG_S3C_UART != 0
  32                 add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
  33                 add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
  34 #endif
  35         .endm
  36 
  37 #define fifo_full fifo_full_s5pv210
  38 #define fifo_level fifo_level_s5pv210
  39 
  40 #include <debug/samsung.S>