root/arch/xtensa/include/asm/pgtable.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. paging_init
  2. pte_write
  3. pte_dirty
  4. pte_young
  5. pte_special
  6. pte_wrprotect
  7. pte_mkclean
  8. pte_mkold
  9. pte_mkdirty
  10. pte_mkyoung
  11. pte_mkwrite
  12. pte_mkspecial
  13. pte_modify
  14. update_pte
  15. set_pte_at
  16. set_pte
  17. set_pmd
  18. ptep_test_and_clear_young
  19. ptep_get_and_clear
  20. ptep_set_wrprotect
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * include/asm-xtensa/pgtable.h
   4  *
   5  * Copyright (C) 2001 - 2013 Tensilica Inc.
   6  */
   7 
   8 #ifndef _XTENSA_PGTABLE_H
   9 #define _XTENSA_PGTABLE_H
  10 
  11 #define __ARCH_USE_5LEVEL_HACK
  12 #include <asm/page.h>
  13 #include <asm/kmem_layout.h>
  14 #include <asm-generic/pgtable-nopmd.h>
  15 
  16 /*
  17  * We only use two ring levels, user and kernel space.
  18  */
  19 
  20 #ifdef CONFIG_MMU
  21 #define USER_RING               1       /* user ring level */
  22 #else
  23 #define USER_RING               0
  24 #endif
  25 #define KERNEL_RING             0       /* kernel ring level */
  26 
  27 /*
  28  * The Xtensa architecture port of Linux has a two-level page table system,
  29  * i.e. the logical three-level Linux page table layout is folded.
  30  * Each task has the following memory page tables:
  31  *
  32  *   PGD table (page directory), ie. 3rd-level page table:
  33  *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
  34  *      (Architectures that don't have the PMD folded point to the PMD tables)
  35  *
  36  *      The pointer to the PGD table for a given task can be retrieved from
  37  *      the task structure (struct task_struct*) t, e.g. current():
  38  *        (t->mm ? t->mm : t->active_mm)->pgd
  39  *
  40  *   PMD tables (page middle-directory), ie. 2nd-level page tables:
  41  *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
  42  *
  43  *   PTE tables (page table entry), ie. 1st-level page tables:
  44  *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
  45  *      invalid_pte_table for absent mappings.
  46  *
  47  * The individual pages are 4 kB big with special pages for the empty_zero_page.
  48  */
  49 
  50 #define PGDIR_SHIFT     22
  51 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  52 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  53 
  54 /*
  55  * Entries per page directory level: we use two-level, so
  56  * we don't really have any PMD directory physically.
  57  */
  58 #define PTRS_PER_PTE            1024
  59 #define PTRS_PER_PTE_SHIFT      10
  60 #define PTRS_PER_PGD            1024
  61 #define PGD_ORDER               0
  62 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  63 #define FIRST_USER_ADDRESS      0UL
  64 #define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
  65 
  66 #ifdef CONFIG_MMU
  67 /*
  68  * Virtual memory area. We keep a distance to other memory regions to be
  69  * on the safe side. We also use this area for cache aliasing.
  70  */
  71 #define VMALLOC_START           (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
  72 #define VMALLOC_END             (VMALLOC_START + 0x07FEFFFF)
  73 #define TLBTEMP_BASE_1          (VMALLOC_END + 1)
  74 #define TLBTEMP_BASE_2          (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
  75 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
  76 #define TLBTEMP_SIZE            (2 * DCACHE_WAY_SIZE)
  77 #else
  78 #define TLBTEMP_SIZE            ICACHE_WAY_SIZE
  79 #endif
  80 
  81 #else
  82 
  83 #define VMALLOC_START           __XTENSA_UL_CONST(0)
  84 #define VMALLOC_END             __XTENSA_UL_CONST(0xffffffff)
  85 
  86 #endif
  87 
  88 /*
  89  * For the Xtensa architecture, the PTE layout is as follows:
  90  *
  91  *              31------12  11  10-9   8-6  5-4  3-2  1-0
  92  *              +-----------------------------------------+
  93  *              |           |   Software   |   HARDWARE   |
  94  *              |    PPN    |          ADW | RI |Attribute|
  95  *              +-----------------------------------------+
  96  *   pte_none   |             MBZ          | 01 | 11 | 00 |
  97  *              +-----------------------------------------+
  98  *   present    |    PPN    | 0 | 00 | ADW | RI | CA | wx |
  99  *              +- - - - - - - - - - - - - - - - - - - - -+
 100  *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
 101  *              +-----------------------------------------+
 102  *   swap       |     index     |   type   | 01 | 11 | 00 |
 103  *              +-----------------------------------------+
 104  *
 105  * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
 106  *              +-----------------------------------------+
 107  *   present    |    PPN    | 0 | 00 | ADW | RI | CA | w1 |
 108  *              +-----------------------------------------+
 109  *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
 110  *              +-----------------------------------------+
 111  *
 112  *  Legend:
 113  *   PPN        Physical Page Number
 114  *   ADW        software: accessed (young) / dirty / writable
 115  *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
 116  *   CA         cache attribute: 00 bypass, 01 writeback, 10 writethrough
 117  *              (11 is invalid and used to mark pages that are not present)
 118  *   w          page is writable (hw)
 119  *   x          page is executable (hw)
 120  *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
 121  *              (note that the index is always non-zero)
 122  *   type       swap type (5 bits -> 32 types)
 123  *
 124  *  Notes:
 125  *   - (PROT_NONE) is a special case of 'present' but causes an exception for
 126  *     any access (read, write, and execute).
 127  *   - 'multihit-exception' has the highest priority of all MMU exceptions,
 128  *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
 129  *   - on older hardware, the exectuable flag was not supported and
 130  *     used as a 'valid' flag, so it needs to be always set.
 131  *   - we need to keep track of certain flags in software (dirty and young)
 132  *     to do this, we use write exceptions and have a separate software w-flag.
 133  *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
 134  */
 135 
 136 #define _PAGE_ATTRIB_MASK       0xf
 137 
 138 #define _PAGE_HW_EXEC           (1<<0)  /* hardware: page is executable */
 139 #define _PAGE_HW_WRITE          (1<<1)  /* hardware: page is writable */
 140 
 141 #define _PAGE_CA_BYPASS         (0<<2)  /* bypass, non-speculative */
 142 #define _PAGE_CA_WB             (1<<2)  /* write-back */
 143 #define _PAGE_CA_WT             (2<<2)  /* write-through */
 144 #define _PAGE_CA_MASK           (3<<2)
 145 #define _PAGE_CA_INVALID        (3<<2)
 146 
 147 /* We use invalid attribute values to distinguish special pte entries */
 148 #if XCHAL_HW_VERSION_MAJOR < 2000
 149 #define _PAGE_HW_VALID          0x01    /* older HW needed this bit set */
 150 #define _PAGE_NONE              0x04
 151 #else
 152 #define _PAGE_HW_VALID          0x00
 153 #define _PAGE_NONE              0x0f
 154 #endif
 155 
 156 #define _PAGE_USER              (1<<4)  /* user access (ring=1) */
 157 
 158 /* Software */
 159 #define _PAGE_WRITABLE_BIT      6
 160 #define _PAGE_WRITABLE          (1<<6)  /* software: page writable */
 161 #define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
 162 #define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
 163 
 164 #ifdef CONFIG_MMU
 165 
 166 #define _PAGE_CHG_MASK     (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 167 #define _PAGE_PRESENT      (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
 168 
 169 #define PAGE_NONE          __pgprot(_PAGE_NONE | _PAGE_USER)
 170 #define PAGE_COPY          __pgprot(_PAGE_PRESENT | _PAGE_USER)
 171 #define PAGE_COPY_EXEC     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 172 #define PAGE_READONLY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
 173 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 174 #define PAGE_SHARED        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
 175 #define PAGE_SHARED_EXEC \
 176         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
 177 #define PAGE_KERNEL        __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
 178 #define PAGE_KERNEL_RO     __pgprot(_PAGE_PRESENT)
 179 #define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
 180 
 181 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
 182 # define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
 183 #else
 184 # define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
 185 #endif
 186 
 187 #else /* no mmu */
 188 
 189 # define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 190 # define PAGE_NONE       __pgprot(0)
 191 # define PAGE_SHARED     __pgprot(0)
 192 # define PAGE_COPY       __pgprot(0)
 193 # define PAGE_READONLY   __pgprot(0)
 194 # define PAGE_KERNEL     __pgprot(0)
 195 
 196 #endif
 197 
 198 /*
 199  * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 200  * the MMU can't do page protection for execute, and considers that the same as
 201  * read.  Also, write permissions may imply read permissions.
 202  * What follows is the closest we can get by reasonable means..
 203  * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 204  */
 205 #define __P000  PAGE_NONE               /* private --- */
 206 #define __P001  PAGE_READONLY           /* private --r */
 207 #define __P010  PAGE_COPY               /* private -w- */
 208 #define __P011  PAGE_COPY               /* private -wr */
 209 #define __P100  PAGE_READONLY_EXEC      /* private x-- */
 210 #define __P101  PAGE_READONLY_EXEC      /* private x-r */
 211 #define __P110  PAGE_COPY_EXEC          /* private xw- */
 212 #define __P111  PAGE_COPY_EXEC          /* private xwr */
 213 
 214 #define __S000  PAGE_NONE               /* shared  --- */
 215 #define __S001  PAGE_READONLY           /* shared  --r */
 216 #define __S010  PAGE_SHARED             /* shared  -w- */
 217 #define __S011  PAGE_SHARED             /* shared  -wr */
 218 #define __S100  PAGE_READONLY_EXEC      /* shared  x-- */
 219 #define __S101  PAGE_READONLY_EXEC      /* shared  x-r */
 220 #define __S110  PAGE_SHARED_EXEC        /* shared  xw- */
 221 #define __S111  PAGE_SHARED_EXEC        /* shared  xwr */
 222 
 223 #ifndef __ASSEMBLY__
 224 
 225 #define pte_ERROR(e) \
 226         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 227 #define pgd_ERROR(e) \
 228         printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 229 
 230 extern unsigned long empty_zero_page[1024];
 231 
 232 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 233 
 234 #ifdef CONFIG_MMU
 235 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
 236 extern void paging_init(void);
 237 #else
 238 # define swapper_pg_dir NULL
 239 static inline void paging_init(void) { }
 240 #endif
 241 
 242 /*
 243  * The pmd contains the kernel virtual address of the pte page.
 244  */
 245 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
 246 #define pmd_page(pmd) virt_to_page(pmd_val(pmd))
 247 
 248 /*
 249  * pte status.
 250  */
 251 # define pte_none(pte)   (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
 252 #if XCHAL_HW_VERSION_MAJOR < 2000
 253 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
 254 #else
 255 # define pte_present(pte)                                               \
 256         (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)           \
 257          || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
 258 #endif
 259 #define pte_clear(mm,addr,ptep)                                         \
 260         do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
 261 
 262 #define pmd_none(pmd)    (!pmd_val(pmd))
 263 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
 264 #define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
 265 #define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
 266 
 267 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
 268 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 269 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 270 static inline int pte_special(pte_t pte) { return 0; }
 271 
 272 static inline pte_t pte_wrprotect(pte_t pte)    
 273         { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
 274 static inline pte_t pte_mkclean(pte_t pte)
 275         { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
 276 static inline pte_t pte_mkold(pte_t pte)
 277         { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 278 static inline pte_t pte_mkdirty(pte_t pte)
 279         { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 280 static inline pte_t pte_mkyoung(pte_t pte)
 281         { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 282 static inline pte_t pte_mkwrite(pte_t pte)
 283         { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
 284 static inline pte_t pte_mkspecial(pte_t pte)
 285         { return pte; }
 286 
 287 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
 288 
 289 /*
 290  * Conversion functions: convert a page and protection to a page entry,
 291  * and a page entry and page directory to the page they refer to.
 292  */
 293 
 294 #define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 295 #define pte_same(a,b)           (pte_val(a) == pte_val(b))
 296 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 297 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 298 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 299 
 300 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 301 {
 302         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 303 }
 304 
 305 /*
 306  * Certain architectures need to do special things when pte's
 307  * within a page table are directly modified.  Thus, the following
 308  * hook is made available.
 309  */
 310 static inline void update_pte(pte_t *ptep, pte_t pteval)
 311 {
 312         *ptep = pteval;
 313 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 314         __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
 315 #endif
 316 
 317 }
 318 
 319 struct mm_struct;
 320 
 321 static inline void
 322 set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
 323 {
 324         update_pte(ptep, pteval);
 325 }
 326 
 327 static inline void set_pte(pte_t *ptep, pte_t pteval)
 328 {
 329         update_pte(ptep, pteval);
 330 }
 331 
 332 static inline void
 333 set_pmd(pmd_t *pmdp, pmd_t pmdval)
 334 {
 335         *pmdp = pmdval;
 336 }
 337 
 338 struct vm_area_struct;
 339 
 340 static inline int
 341 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
 342                           pte_t *ptep)
 343 {
 344         pte_t pte = *ptep;
 345         if (!pte_young(pte))
 346                 return 0;
 347         update_pte(ptep, pte_mkold(pte));
 348         return 1;
 349 }
 350 
 351 static inline pte_t
 352 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 353 {
 354         pte_t pte = *ptep;
 355         pte_clear(mm, addr, ptep);
 356         return pte;
 357 }
 358 
 359 static inline void
 360 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 361 {
 362         pte_t pte = *ptep;
 363         update_pte(ptep, pte_wrprotect(pte));
 364 }
 365 
 366 /* to find an entry in a kernel page-table-directory */
 367 #define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 368 
 369 /* to find an entry in a page-table-directory */
 370 #define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
 371 
 372 #define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 373 
 374 /* Find an entry in the second-level page table.. */
 375 #define pmd_offset(dir,address) ((pmd_t*)(dir))
 376 
 377 /* Find an entry in the third-level page table.. */
 378 #define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 379 #define pte_offset_kernel(dir,addr)                                     \
 380         ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
 381 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
 382 #define pte_unmap(pte)          do { } while (0)
 383 
 384 
 385 /*
 386  * Encode and decode a swap and file entry.
 387  */
 388 #define SWP_TYPE_BITS           5
 389 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
 390 
 391 #define __swp_type(entry)       (((entry).val >> 6) & 0x1f)
 392 #define __swp_offset(entry)     ((entry).val >> 11)
 393 #define __swp_entry(type,offs)  \
 394         ((swp_entry_t){((type) << 6) | ((offs) << 11) | \
 395          _PAGE_CA_INVALID | _PAGE_USER})
 396 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 397 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 398 
 399 #endif /*  !defined (__ASSEMBLY__) */
 400 
 401 
 402 #ifdef __ASSEMBLY__
 403 
 404 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 405  *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 406  *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 407  *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 408  *
 409  * Note: We require an additional temporary register which can be the same as
 410  *       the register that holds the address.
 411  *
 412  * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 413  *
 414  */
 415 #define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
 416 #define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
 417 
 418 #define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
 419                                         _PGD_INDEX(tmp, adr);           \
 420                                         addx4   mm, tmp, mm
 421 
 422 #define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
 423                                         srli    pmd, pmd, PAGE_SHIFT;   \
 424                                         slli    pmd, pmd, PAGE_SHIFT;   \
 425                                         addx4   pmd, tmp, pmd
 426 
 427 #else
 428 
 429 #define kern_addr_valid(addr)   (1)
 430 
 431 extern  void update_mmu_cache(struct vm_area_struct * vma,
 432                               unsigned long address, pte_t *ptep);
 433 
 434 typedef pte_t *pte_addr_t;
 435 
 436 #endif /* !defined (__ASSEMBLY__) */
 437 
 438 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 439 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 440 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 441 #define __HAVE_ARCH_PTEP_MKDIRTY
 442 #define __HAVE_ARCH_PTE_SAME
 443 /* We provide our own get_unmapped_area to cope with
 444  * SHM area cache aliasing for userland.
 445  */
 446 #define HAVE_ARCH_UNMAPPED_AREA
 447 
 448 #include <asm-generic/pgtable.h>
 449 
 450 #endif /* _XTENSA_PGTABLE_H */
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