virt/kvm/arm/vgic/vgic-mmio-v3.c

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This source file includes following definitions.
extract_bytes
update_64bit_reg
vgic_has_its
vgic_supports_direct_msis
vgic_mmio_read_v3_misc
vgic_mmio_write_v3_misc
vgic_mmio_uaccess_write_v3_misc
vgic_mmio_read_irouter
vgic_mmio_write_irouter
vgic_mmio_read_v3r_ctlr
vgic_mmio_write_v3r_ctlr
vgic_mmio_read_v3r_typer
vgic_mmio_read_v3r_iidr
vgic_mmio_read_v3_idregs
vgic_v3_uaccess_read_pending
vgic_v3_uaccess_write_pending
vgic_sanitise_shareability
vgic_sanitise_inner_cacheability
vgic_sanitise_outer_cacheability
vgic_sanitise_field
vgic_sanitise_pendbaser
vgic_sanitise_propbaser
vgic_mmio_read_propbase
vgic_mmio_write_propbase
vgic_mmio_read_pendbase
vgic_mmio_write_pendbase
vgic_v3_init_dist_iodev
vgic_register_redist_iodev
vgic_unregister_redist_iodev
vgic_register_all_redist_iodevs
vgic_v3_insert_redist_region
vgic_v3_set_redist_base
vgic_v3_has_attr_regs
match_mpidr
vgic_v3_dispatch_sgi
vgic_v3_dist_uaccess
vgic_v3_redist_uaccess
vgic_v3_line_level_info_uaccess
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VGICv3 MMIO handling functions
   4  */
   5 
   6 #include <linux/irqchip/arm-gic-v3.h>
   7 #include <linux/kvm.h>
   8 #include <linux/kvm_host.h>
   9 #include <kvm/iodev.h>
  10 #include <kvm/arm_vgic.h>
  11 
  12 #include <asm/kvm_emulate.h>
  13 #include <asm/kvm_arm.h>
  14 #include <asm/kvm_mmu.h>
  15 
  16 #include "vgic.h"
  17 #include "vgic-mmio.h"
  18 
  19 /* extract @num bytes at @offset bytes offset in data */
  20 unsigned long extract_bytes(u64 data, unsigned int offset,
  21                             unsigned int num)
  22 {
  23         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  24 }
  25 
  26 /* allows updates of any half of a 64-bit register (or the whole thing) */
  27 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
  28                      unsigned long val)
  29 {
  30         int lower = (offset & 4) * 8;
  31         int upper = lower + 8 * len - 1;
  32 
  33         reg &= ~GENMASK_ULL(upper, lower);
  34         val &= GENMASK_ULL(len * 8 - 1, 0);
  35 
  36         return reg | ((u64)val << lower);
  37 }
  38 
  39 bool vgic_has_its(struct kvm *kvm)
  40 {
  41         struct vgic_dist *dist = &kvm->arch.vgic;
  42 
  43         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
  44                 return false;
  45 
  46         return dist->has_its;
  47 }
  48 
  49 bool vgic_supports_direct_msis(struct kvm *kvm)
  50 {
  51         return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
  52 }
  53 
  54 /*
  55  * The Revision field in the IIDR have the following meanings:
  56  *
  57  * Revision 2: Interrupt groups are guest-configurable and signaled using
  58  *             their configured groups.
  59  */
  60 
  61 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  62                                             gpa_t addr, unsigned int len)
  63 {
  64         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
  65         u32 value = 0;
  66 
  67         switch (addr & 0x0c) {
  68         case GICD_CTLR:
  69                 if (vgic->enabled)
  70                         value |= GICD_CTLR_ENABLE_SS_G1;
  71                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  72                 break;
  73         case GICD_TYPER:
  74                 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
  75                 value = (value >> 5) - 1;
  76                 if (vgic_has_its(vcpu->kvm)) {
  77                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
  78                         value |= GICD_TYPER_LPIS;
  79                 } else {
  80                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  81                 }
  82                 break;
  83         case GICD_IIDR:
  84                 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
  85                         (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
  86                         (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
  87                 break;
  88         default:
  89                 return 0;
  90         }
  91 
  92         return value;
  93 }
  94 
  95 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
  96                                     gpa_t addr, unsigned int len,
  97                                     unsigned long val)
  98 {
  99         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 100         bool was_enabled = dist->enabled;
 101 
 102         switch (addr & 0x0c) {
 103         case GICD_CTLR:
 104                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 105 
 106                 if (!was_enabled && dist->enabled)
 107                         vgic_kick_vcpus(vcpu->kvm);
 108                 break;
 109         case GICD_TYPER:
 110         case GICD_IIDR:
 111                 return;
 112         }
 113 }
 114 
 115 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 116                                            gpa_t addr, unsigned int len,
 117                                            unsigned long val)
 118 {
 119         switch (addr & 0x0c) {
 120         case GICD_IIDR:
 121                 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 122                         return -EINVAL;
 123         }
 124 
 125         vgic_mmio_write_v3_misc(vcpu, addr, len, val);
 126         return 0;
 127 }
 128 
 129 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
 130                                             gpa_t addr, unsigned int len)
 131 {
 132         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 133         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 134         unsigned long ret = 0;
 135 
 136         if (!irq)
 137                 return 0;
 138 
 139         /* The upper word is RAZ for us. */
 140         if (!(addr & 4))
 141                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
 142 
 143         vgic_put_irq(vcpu->kvm, irq);
 144         return ret;
 145 }
 146 
 147 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
 148                                     gpa_t addr, unsigned int len,
 149                                     unsigned long val)
 150 {
 151         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 152         struct vgic_irq *irq;
 153         unsigned long flags;
 154 
 155         /* The upper word is WI for us since we don't implement Aff3. */
 156         if (addr & 4)
 157                 return;
 158 
 159         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 160 
 161         if (!irq)
 162                 return;
 163 
 164         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 165 
 166         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 167         irq->mpidr = val & GENMASK(23, 0);
 168         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 169 
 170         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 171         vgic_put_irq(vcpu->kvm, irq);
 172 }
 173 
 174 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
 175                                              gpa_t addr, unsigned int len)
 176 {
 177         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 178 
 179         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
 180 }
 181 
 182 
 183 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
 184                                      gpa_t addr, unsigned int len,
 185                                      unsigned long val)
 186 {
 187         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 188         bool was_enabled = vgic_cpu->lpis_enabled;
 189 
 190         if (!vgic_has_its(vcpu->kvm))
 191                 return;
 192 
 193         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
 194 
 195         if (was_enabled && !vgic_cpu->lpis_enabled) {
 196                 vgic_flush_pending_lpis(vcpu);
 197                 vgic_its_invalidate_cache(vcpu->kvm);
 198         }
 199 
 200         if (!was_enabled && vgic_cpu->lpis_enabled)
 201                 vgic_enable_lpis(vcpu);
 202 }
 203 
 204 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 205                                               gpa_t addr, unsigned int len)
 206 {
 207         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 208         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 209         struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
 210         int target_vcpu_id = vcpu->vcpu_id;
 211         gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
 212                         (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
 213         u64 value;
 214 
 215         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 216         value |= ((target_vcpu_id & 0xffff) << 8);
 217 
 218         if (addr == last_rdist_typer)
 219                 value |= GICR_TYPER_LAST;
 220         if (vgic_has_its(vcpu->kvm))
 221                 value |= GICR_TYPER_PLPIS;
 222 
 223         return extract_bytes(value, addr & 7, len);
 224 }
 225 
 226 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 227                                              gpa_t addr, unsigned int len)
 228 {
 229         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 230 }
 231 
 232 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 233                                               gpa_t addr, unsigned int len)
 234 {
 235         switch (addr & 0xffff) {
 236         case GICD_PIDR2:
 237                 /* report a GICv3 compliant implementation */
 238                 return 0x3b;
 239         }
 240 
 241         return 0;
 242 }
 243 
 244 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
 245                                                   gpa_t addr, unsigned int len)
 246 {
 247         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 248         u32 value = 0;
 249         int i;
 250 
 251         /*
 252          * pending state of interrupt is latched in pending_latch variable.
 253          * Userspace will save and restore pending state and line_level
 254          * separately.
 255          * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.txt
 256          * for handling of ISPENDR and ICPENDR.
 257          */
 258         for (i = 0; i < len * 8; i++) {
 259                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 260 
 261                 if (irq->pending_latch)
 262                         value |= (1U << i);
 263 
 264                 vgic_put_irq(vcpu->kvm, irq);
 265         }
 266 
 267         return value;
 268 }
 269 
 270 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
 271                                          gpa_t addr, unsigned int len,
 272                                          unsigned long val)
 273 {
 274         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 275         int i;
 276         unsigned long flags;
 277 
 278         for (i = 0; i < len * 8; i++) {
 279                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 280 
 281                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 282                 if (test_bit(i, &val)) {
 283                         /*
 284                          * pending_latch is set irrespective of irq type
 285                          * (level or edge) to avoid dependency that VM should
 286                          * restore irq config before pending info.
 287                          */
 288                         irq->pending_latch = true;
 289                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 290                 } else {
 291                         irq->pending_latch = false;
 292                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 293                 }
 294 
 295                 vgic_put_irq(vcpu->kvm, irq);
 296         }
 297 
 298         return 0;
 299 }
 300 
 301 /* We want to avoid outer shareable. */
 302 u64 vgic_sanitise_shareability(u64 field)
 303 {
 304         switch (field) {
 305         case GIC_BASER_OuterShareable:
 306                 return GIC_BASER_InnerShareable;
 307         default:
 308                 return field;
 309         }
 310 }
 311 
 312 /* Avoid any inner non-cacheable mapping. */
 313 u64 vgic_sanitise_inner_cacheability(u64 field)
 314 {
 315         switch (field) {
 316         case GIC_BASER_CACHE_nCnB:
 317         case GIC_BASER_CACHE_nC:
 318                 return GIC_BASER_CACHE_RaWb;
 319         default:
 320                 return field;
 321         }
 322 }
 323 
 324 /* Non-cacheable or same-as-inner are OK. */
 325 u64 vgic_sanitise_outer_cacheability(u64 field)
 326 {
 327         switch (field) {
 328         case GIC_BASER_CACHE_SameAsInner:
 329         case GIC_BASER_CACHE_nC:
 330                 return field;
 331         default:
 332                 return GIC_BASER_CACHE_nC;
 333         }
 334 }
 335 
 336 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 337                         u64 (*sanitise_fn)(u64))
 338 {
 339         u64 field = (reg & field_mask) >> field_shift;
 340 
 341         field = sanitise_fn(field) << field_shift;
 342         return (reg & ~field_mask) | field;
 343 }
 344 
 345 #define PROPBASER_RES0_MASK                                             \
 346         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
 347 #define PENDBASER_RES0_MASK                                             \
 348         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
 349          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
 350 
 351 static u64 vgic_sanitise_pendbaser(u64 reg)
 352 {
 353         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
 354                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
 355                                   vgic_sanitise_shareability);
 356         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
 357                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
 358                                   vgic_sanitise_inner_cacheability);
 359         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
 360                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
 361                                   vgic_sanitise_outer_cacheability);
 362 
 363         reg &= ~PENDBASER_RES0_MASK;
 364 
 365         return reg;
 366 }
 367 
 368 static u64 vgic_sanitise_propbaser(u64 reg)
 369 {
 370         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
 371                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
 372                                   vgic_sanitise_shareability);
 373         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
 374                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
 375                                   vgic_sanitise_inner_cacheability);
 376         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
 377                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
 378                                   vgic_sanitise_outer_cacheability);
 379 
 380         reg &= ~PROPBASER_RES0_MASK;
 381         return reg;
 382 }
 383 
 384 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
 385                                              gpa_t addr, unsigned int len)
 386 {
 387         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 388 
 389         return extract_bytes(dist->propbaser, addr & 7, len);
 390 }
 391 
 392 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
 393                                      gpa_t addr, unsigned int len,
 394                                      unsigned long val)
 395 {
 396         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 397         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 398         u64 old_propbaser, propbaser;
 399 
 400         /* Storing a value with LPIs already enabled is undefined */
 401         if (vgic_cpu->lpis_enabled)
 402                 return;
 403 
 404         do {
 405                 old_propbaser = READ_ONCE(dist->propbaser);
 406                 propbaser = old_propbaser;
 407                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
 408                 propbaser = vgic_sanitise_propbaser(propbaser);
 409         } while (cmpxchg64(&dist->propbaser, old_propbaser,
 410                            propbaser) != old_propbaser);
 411 }
 412 
 413 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
 414                                              gpa_t addr, unsigned int len)
 415 {
 416         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 417 
 418         return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
 419 }
 420 
 421 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
 422                                      gpa_t addr, unsigned int len,
 423                                      unsigned long val)
 424 {
 425         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 426         u64 old_pendbaser, pendbaser;
 427 
 428         /* Storing a value with LPIs already enabled is undefined */
 429         if (vgic_cpu->lpis_enabled)
 430                 return;
 431 
 432         do {
 433                 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
 434                 pendbaser = old_pendbaser;
 435                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
 436                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
 437         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
 438                            pendbaser) != old_pendbaser);
 439 }
 440 
 441 /*
 442  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 443  * redistributors, while SPIs are covered by registers in the distributor
 444  * block. Trying to set private IRQs in this block gets ignored.
 445  * We take some special care here to fix the calculation of the register
 446  * offset.
 447  */
 448 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
 449         {                                                               \
 450                 .reg_offset = off,                                      \
 451                 .bits_per_irq = bpi,                                    \
 452                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 453                 .access_flags = acc,                                    \
 454                 .read = vgic_mmio_read_raz,                             \
 455                 .write = vgic_mmio_write_wi,                            \
 456         }, {                                                            \
 457                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 458                 .bits_per_irq = bpi,                                    \
 459                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 460                 .access_flags = acc,                                    \
 461                 .read = rd,                                             \
 462                 .write = wr,                                            \
 463                 .uaccess_read = ur,                                     \
 464                 .uaccess_write = uw,                                    \
 465         }
 466 
 467 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 468         REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
 469                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
 470                 NULL, vgic_mmio_uaccess_write_v3_misc,
 471                 16, VGIC_ACCESS_32bit),
 472         REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
 473                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 474                 VGIC_ACCESS_32bit),
 475         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 476                 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
 477                 VGIC_ACCESS_32bit),
 478         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 479                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
 480                 VGIC_ACCESS_32bit),
 481         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 482                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
 483                 VGIC_ACCESS_32bit),
 484         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 485                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 486                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
 487                 VGIC_ACCESS_32bit),
 488         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 489                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 490                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
 491                 VGIC_ACCESS_32bit),
 492         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 493                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 494                 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,
 495                 VGIC_ACCESS_32bit),
 496         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 497                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 498                 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive,
 499                 1, VGIC_ACCESS_32bit),
 500         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 501                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
 502                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 503         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 504                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
 505                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 506         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 507                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
 508                 VGIC_ACCESS_32bit),
 509         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 510                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
 511                 VGIC_ACCESS_32bit),
 512         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 513                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
 514                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 515         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 516                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 517                 VGIC_ACCESS_32bit),
 518 };
 519 
 520 static const struct vgic_register_region vgic_v3_rd_registers[] = {
 521         /* RD_base registers */
 522         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 523                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
 524                 VGIC_ACCESS_32bit),
 525         REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
 526                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 527                 VGIC_ACCESS_32bit),
 528         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 529                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 530                 VGIC_ACCESS_32bit),
 531         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 532                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 533                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 534         REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
 535                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 536                 VGIC_ACCESS_32bit),
 537         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 538                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
 539                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 540         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 541                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
 542                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 543         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 544                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 545                 VGIC_ACCESS_32bit),
 546         /* SGI_base registers */
 547         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
 548                 vgic_mmio_read_group, vgic_mmio_write_group, 4,
 549                 VGIC_ACCESS_32bit),
 550         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0,
 551                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 552                 VGIC_ACCESS_32bit),
 553         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0,
 554                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 555                 VGIC_ACCESS_32bit),
 556         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
 557                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 558                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
 559                 VGIC_ACCESS_32bit),
 560         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
 561                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 562                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
 563                 VGIC_ACCESS_32bit),
 564         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
 565                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 566                 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4,
 567                 VGIC_ACCESS_32bit),
 568         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
 569                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 570                 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4,
 571                 VGIC_ACCESS_32bit),
 572         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
 573                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 574                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 575         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
 576                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 577                 VGIC_ACCESS_32bit),
 578         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
 579                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 580                 VGIC_ACCESS_32bit),
 581         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
 582                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 583                 VGIC_ACCESS_32bit),
 584 };
 585 
 586 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 587 {
 588         dev->regions = vgic_v3_dist_registers;
 589         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 590 
 591         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 592 
 593         return SZ_64K;
 594 }
 595 
 596 /**
 597  * vgic_register_redist_iodev - register a single redist iodev
 598  * @vcpu:    The VCPU to which the redistributor belongs
 599  *
 600  * Register a KVM iodev for this VCPU's redistributor using the address
 601  * provided.
 602  *
 603  * Return 0 on success, -ERRNO otherwise.
 604  */
 605 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
 606 {
 607         struct kvm *kvm = vcpu->kvm;
 608         struct vgic_dist *vgic = &kvm->arch.vgic;
 609         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 610         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 611         struct vgic_redist_region *rdreg;
 612         gpa_t rd_base;
 613         int ret;
 614 
 615         if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
 616                 return 0;
 617 
 618         /*
 619          * We may be creating VCPUs before having set the base address for the
 620          * redistributor region, in which case we will come back to this
 621          * function for all VCPUs when the base address is set.  Just return
 622          * without doing any work for now.
 623          */
 624         rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
 625         if (!rdreg)
 626                 return 0;
 627 
 628         if (!vgic_v3_check_base(kvm))
 629                 return -EINVAL;
 630 
 631         vgic_cpu->rdreg = rdreg;
 632 
 633         rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
 634 
 635         kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 636         rd_dev->base_addr = rd_base;
 637         rd_dev->iodev_type = IODEV_REDIST;
 638         rd_dev->regions = vgic_v3_rd_registers;
 639         rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
 640         rd_dev->redist_vcpu = vcpu;
 641 
 642         mutex_lock(&kvm->slots_lock);
 643         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 644                                       2 * SZ_64K, &rd_dev->dev);
 645         mutex_unlock(&kvm->slots_lock);
 646 
 647         if (ret)
 648                 return ret;
 649 
 650         rdreg->free_index++;
 651         return 0;
 652 }
 653 
 654 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
 655 {
 656         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 657 
 658         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
 659 }
 660 
 661 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
 662 {
 663         struct kvm_vcpu *vcpu;
 664         int c, ret = 0;
 665 
 666         kvm_for_each_vcpu(c, vcpu, kvm) {
 667                 ret = vgic_register_redist_iodev(vcpu);
 668                 if (ret)
 669                         break;
 670         }
 671 
 672         if (ret) {
 673                 /* The current c failed, so we start with the previous one. */
 674                 mutex_lock(&kvm->slots_lock);
 675                 for (c--; c >= 0; c--) {
 676                         vcpu = kvm_get_vcpu(kvm, c);
 677                         vgic_unregister_redist_iodev(vcpu);
 678                 }
 679                 mutex_unlock(&kvm->slots_lock);
 680         }
 681 
 682         return ret;
 683 }
 684 
 685 /**
 686  * vgic_v3_insert_redist_region - Insert a new redistributor region
 687  *
 688  * Performs various checks before inserting the rdist region in the list.
 689  * Those tests depend on whether the size of the rdist region is known
 690  * (ie. count != 0). The list is sorted by rdist region index.
 691  *
 692  * @kvm: kvm handle
 693  * @index: redist region index
 694  * @base: base of the new rdist region
 695  * @count: number of redistributors the region is made of (0 in the old style
 696  * single region, whose size is induced from the number of vcpus)
 697  *
 698  * Return 0 on success, < 0 otherwise
 699  */
 700 static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
 701                                         gpa_t base, uint32_t count)
 702 {
 703         struct vgic_dist *d = &kvm->arch.vgic;
 704         struct vgic_redist_region *rdreg;
 705         struct list_head *rd_regions = &d->rd_regions;
 706         size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
 707         int ret;
 708 
 709         /* single rdist region already set ?*/
 710         if (!count && !list_empty(rd_regions))
 711                 return -EINVAL;
 712 
 713         /* cross the end of memory ? */
 714         if (base + size < base)
 715                 return -EINVAL;
 716 
 717         if (list_empty(rd_regions)) {
 718                 if (index != 0)
 719                         return -EINVAL;
 720         } else {
 721                 rdreg = list_last_entry(rd_regions,
 722                                         struct vgic_redist_region, list);
 723                 if (index != rdreg->index + 1)
 724                         return -EINVAL;
 725 
 726                 /* Cannot add an explicitly sized regions after legacy region */
 727                 if (!rdreg->count)
 728                         return -EINVAL;
 729         }
 730 
 731         /*
 732          * For legacy single-region redistributor regions (!count),
 733          * check that the redistributor region does not overlap with the
 734          * distributor's address space.
 735          */
 736         if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 737                 vgic_dist_overlap(kvm, base, size))
 738                 return -EINVAL;
 739 
 740         /* collision with any other rdist region? */
 741         if (vgic_v3_rdist_overlap(kvm, base, size))
 742                 return -EINVAL;
 743 
 744         rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
 745         if (!rdreg)
 746                 return -ENOMEM;
 747 
 748         rdreg->base = VGIC_ADDR_UNDEF;
 749 
 750         ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
 751         if (ret)
 752                 goto free;
 753 
 754         rdreg->base = base;
 755         rdreg->count = count;
 756         rdreg->free_index = 0;
 757         rdreg->index = index;
 758 
 759         list_add_tail(&rdreg->list, rd_regions);
 760         return 0;
 761 free:
 762         kfree(rdreg);
 763         return ret;
 764 }
 765 
 766 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
 767 {
 768         int ret;
 769 
 770         ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
 771         if (ret)
 772                 return ret;
 773 
 774         /*
 775          * Register iodevs for each existing VCPU.  Adding more VCPUs
 776          * afterwards will register the iodevs when needed.
 777          */
 778         ret = vgic_register_all_redist_iodevs(kvm);
 779         if (ret)
 780                 return ret;
 781 
 782         return 0;
 783 }
 784 
 785 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 786 {
 787         const struct vgic_register_region *region;
 788         struct vgic_io_device iodev;
 789         struct vgic_reg_attr reg_attr;
 790         struct kvm_vcpu *vcpu;
 791         gpa_t addr;
 792         int ret;
 793 
 794         ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
 795         if (ret)
 796                 return ret;
 797 
 798         vcpu = reg_attr.vcpu;
 799         addr = reg_attr.addr;
 800 
 801         switch (attr->group) {
 802         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 803                 iodev.regions = vgic_v3_dist_registers;
 804                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 805                 iodev.base_addr = 0;
 806                 break;
 807         case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
 808                 iodev.regions = vgic_v3_rd_registers;
 809                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
 810                 iodev.base_addr = 0;
 811                 break;
 812         }
 813         case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
 814                 u64 reg, id;
 815 
 816                 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
 817                 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
 818         }
 819         default:
 820                 return -ENXIO;
 821         }
 822 
 823         /* We only support aligned 32-bit accesses. */
 824         if (addr & 3)
 825                 return -ENXIO;
 826 
 827         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 828         if (!region)
 829                 return -ENXIO;
 830 
 831         return 0;
 832 }
 833 /*
 834  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 835  * generation register ICC_SGI1R_EL1) with a given VCPU.
 836  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 837  * return -1.
 838  */
 839 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 840 {
 841         unsigned long affinity;
 842         int level0;
 843 
 844         /*
 845          * Split the current VCPU's MPIDR into affinity level 0 and the
 846          * rest as this is what we have to compare against.
 847          */
 848         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 849         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 850         affinity &= ~MPIDR_LEVEL_MASK;
 851 
 852         /* bail out if the upper three levels don't match */
 853         if (sgi_aff != affinity)
 854                 return -1;
 855 
 856         /* Is this VCPU's bit set in the mask ? */
 857         if (!(sgi_cpu_mask & BIT(level0)))
 858                 return -1;
 859 
 860         return level0;
 861 }
 862 
 863 /*
 864  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 865  * so provide a wrapper to use the existing defines to isolate a certain
 866  * affinity level.
 867  */
 868 #define SGI_AFFINITY_LEVEL(reg, level) \
 869         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 870         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 871 
 872 /**
 873  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 874  * @vcpu: The VCPU requesting a SGI
 875  * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
 876  * @allow_group1: Does the sysreg access allow generation of G1 SGIs
 877  *
 878  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 879  * This will trap in sys_regs.c and call this function.
 880  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 881  * target processors as well as a bitmask of 16 Aff0 CPUs.
 882  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 883  * check for matching ones. If this bit is set, we signal all, but not the
 884  * calling VCPU.
 885  */
 886 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
 887 {
 888         struct kvm *kvm = vcpu->kvm;
 889         struct kvm_vcpu *c_vcpu;
 890         u16 target_cpus;
 891         u64 mpidr;
 892         int sgi, c;
 893         int vcpu_id = vcpu->vcpu_id;
 894         bool broadcast;
 895         unsigned long flags;
 896 
 897         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 898         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 899         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 900         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 901         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 902         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 903 
 904         /*
 905          * We iterate over all VCPUs to find the MPIDRs matching the request.
 906          * If we have handled one CPU, we clear its bit to detect early
 907          * if we are already finished. This avoids iterating through all
 908          * VCPUs when most of the times we just signal a single VCPU.
 909          */
 910         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 911                 struct vgic_irq *irq;
 912 
 913                 /* Exit early if we have dealt with all requested CPUs */
 914                 if (!broadcast && target_cpus == 0)
 915                         break;
 916 
 917                 /* Don't signal the calling VCPU */
 918                 if (broadcast && c == vcpu_id)
 919                         continue;
 920 
 921                 if (!broadcast) {
 922                         int level0;
 923 
 924                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 925                         if (level0 == -1)
 926                                 continue;
 927 
 928                         /* remove this matching VCPU from the mask */
 929                         target_cpus &= ~BIT(level0);
 930                 }
 931 
 932                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 933 
 934                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 935 
 936                 /*
 937                  * An access targetting Group0 SGIs can only generate
 938                  * those, while an access targetting Group1 SGIs can
 939                  * generate interrupts of either group.
 940                  */
 941                 if (!irq->group || allow_group1) {
 942                         irq->pending_latch = true;
 943                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 944                 } else {
 945                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 946                 }
 947 
 948                 vgic_put_irq(vcpu->kvm, irq);
 949         }
 950 }
 951 
 952 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 953                          int offset, u32 *val)
 954 {
 955         struct vgic_io_device dev = {
 956                 .regions = vgic_v3_dist_registers,
 957                 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
 958         };
 959 
 960         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 961 }
 962 
 963 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 964                            int offset, u32 *val)
 965 {
 966         struct vgic_io_device rd_dev = {
 967                 .regions = vgic_v3_rd_registers,
 968                 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
 969         };
 970 
 971         return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
 972 }
 973 
 974 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 975                                     u32 intid, u64 *val)
 976 {
 977         if (intid % 32)
 978                 return -EINVAL;
 979 
 980         if (is_write)
 981                 vgic_write_irq_line_level_info(vcpu, intid, *val);
 982         else
 983                 *val = vgic_read_irq_line_level_info(vcpu, intid);
 984 
 985         return 0;
 986 }
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root/virt/kvm/arm/vgic/vgic-mmio-v3.c

DEFINITIONS
