sound/soc/codecs/da9055.c

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This source file includes following definitions.
da9055_get_alc_data
da9055_put_alc_sw
da9055_volatile_register
da9055_hw_params
da9055_set_dai_fmt
da9055_mute
da9055_set_dai_sysclk
da9055_set_dai_pll
da9055_set_bias_level
da9055_probe
da9055_i2c_probe
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * DA9055 ALSA Soc codec driver
   4  *
   5  * Copyright (c) 2012 Dialog Semiconductor
   6  *
   7  * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
   8  * Written by David Chen <david.chen@diasemi.com> and
   9  * Ashish Chavan <ashish.chavan@kpitcummins.com>
  10  */
  11 
  12 #include <linux/delay.h>
  13 #include <linux/i2c.h>
  14 #include <linux/regmap.h>
  15 #include <linux/slab.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <sound/pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/soc.h>
  22 #include <sound/initval.h>
  23 #include <sound/tlv.h>
  24 #include <sound/da9055.h>
  25 
  26 /* DA9055 register space */
  27 
  28 /* Status Registers */
  29 #define DA9055_STATUS1                  0x02
  30 #define DA9055_PLL_STATUS               0x03
  31 #define DA9055_AUX_L_GAIN_STATUS        0x04
  32 #define DA9055_AUX_R_GAIN_STATUS        0x05
  33 #define DA9055_MIC_L_GAIN_STATUS        0x06
  34 #define DA9055_MIC_R_GAIN_STATUS        0x07
  35 #define DA9055_MIXIN_L_GAIN_STATUS      0x08
  36 #define DA9055_MIXIN_R_GAIN_STATUS      0x09
  37 #define DA9055_ADC_L_GAIN_STATUS        0x0A
  38 #define DA9055_ADC_R_GAIN_STATUS        0x0B
  39 #define DA9055_DAC_L_GAIN_STATUS        0x0C
  40 #define DA9055_DAC_R_GAIN_STATUS        0x0D
  41 #define DA9055_HP_L_GAIN_STATUS         0x0E
  42 #define DA9055_HP_R_GAIN_STATUS         0x0F
  43 #define DA9055_LINE_GAIN_STATUS         0x10
  44 
  45 /* System Initialisation Registers */
  46 #define DA9055_CIF_CTRL                 0x20
  47 #define DA9055_DIG_ROUTING_AIF          0X21
  48 #define DA9055_SR                       0x22
  49 #define DA9055_REFERENCES               0x23
  50 #define DA9055_PLL_FRAC_TOP             0x24
  51 #define DA9055_PLL_FRAC_BOT             0x25
  52 #define DA9055_PLL_INTEGER              0x26
  53 #define DA9055_PLL_CTRL                 0x27
  54 #define DA9055_AIF_CLK_MODE             0x28
  55 #define DA9055_AIF_CTRL                 0x29
  56 #define DA9055_DIG_ROUTING_DAC          0x2A
  57 #define DA9055_ALC_CTRL1                0x2B
  58 
  59 /* Input - Gain, Select and Filter Registers */
  60 #define DA9055_AUX_L_GAIN               0x30
  61 #define DA9055_AUX_R_GAIN               0x31
  62 #define DA9055_MIXIN_L_SELECT           0x32
  63 #define DA9055_MIXIN_R_SELECT           0x33
  64 #define DA9055_MIXIN_L_GAIN             0x34
  65 #define DA9055_MIXIN_R_GAIN             0x35
  66 #define DA9055_ADC_L_GAIN               0x36
  67 #define DA9055_ADC_R_GAIN               0x37
  68 #define DA9055_ADC_FILTERS1             0x38
  69 #define DA9055_MIC_L_GAIN               0x39
  70 #define DA9055_MIC_R_GAIN               0x3A
  71 
  72 /* Output - Gain, Select and Filter Registers */
  73 #define DA9055_DAC_FILTERS5             0x40
  74 #define DA9055_DAC_FILTERS2             0x41
  75 #define DA9055_DAC_FILTERS3             0x42
  76 #define DA9055_DAC_FILTERS4             0x43
  77 #define DA9055_DAC_FILTERS1             0x44
  78 #define DA9055_DAC_L_GAIN               0x45
  79 #define DA9055_DAC_R_GAIN               0x46
  80 #define DA9055_CP_CTRL                  0x47
  81 #define DA9055_HP_L_GAIN                0x48
  82 #define DA9055_HP_R_GAIN                0x49
  83 #define DA9055_LINE_GAIN                0x4A
  84 #define DA9055_MIXOUT_L_SELECT          0x4B
  85 #define DA9055_MIXOUT_R_SELECT          0x4C
  86 
  87 /* System Controller Registers */
  88 #define DA9055_SYSTEM_MODES_INPUT       0x50
  89 #define DA9055_SYSTEM_MODES_OUTPUT      0x51
  90 
  91 /* Control Registers */
  92 #define DA9055_AUX_L_CTRL               0x60
  93 #define DA9055_AUX_R_CTRL               0x61
  94 #define DA9055_MIC_BIAS_CTRL            0x62
  95 #define DA9055_MIC_L_CTRL               0x63
  96 #define DA9055_MIC_R_CTRL               0x64
  97 #define DA9055_MIXIN_L_CTRL             0x65
  98 #define DA9055_MIXIN_R_CTRL             0x66
  99 #define DA9055_ADC_L_CTRL               0x67
 100 #define DA9055_ADC_R_CTRL               0x68
 101 #define DA9055_DAC_L_CTRL               0x69
 102 #define DA9055_DAC_R_CTRL               0x6A
 103 #define DA9055_HP_L_CTRL                0x6B
 104 #define DA9055_HP_R_CTRL                0x6C
 105 #define DA9055_LINE_CTRL                0x6D
 106 #define DA9055_MIXOUT_L_CTRL            0x6E
 107 #define DA9055_MIXOUT_R_CTRL            0x6F
 108 
 109 /* Configuration Registers */
 110 #define DA9055_LDO_CTRL                 0x90
 111 #define DA9055_IO_CTRL                  0x91
 112 #define DA9055_GAIN_RAMP_CTRL           0x92
 113 #define DA9055_MIC_CONFIG               0x93
 114 #define DA9055_PC_COUNT                 0x94
 115 #define DA9055_CP_VOL_THRESHOLD1        0x95
 116 #define DA9055_CP_DELAY                 0x96
 117 #define DA9055_CP_DETECTOR              0x97
 118 #define DA9055_AIF_OFFSET               0x98
 119 #define DA9055_DIG_CTRL                 0x99
 120 #define DA9055_ALC_CTRL2                0x9A
 121 #define DA9055_ALC_CTRL3                0x9B
 122 #define DA9055_ALC_NOISE                0x9C
 123 #define DA9055_ALC_TARGET_MIN           0x9D
 124 #define DA9055_ALC_TARGET_MAX           0x9E
 125 #define DA9055_ALC_GAIN_LIMITS          0x9F
 126 #define DA9055_ALC_ANA_GAIN_LIMITS      0xA0
 127 #define DA9055_ALC_ANTICLIP_CTRL        0xA1
 128 #define DA9055_ALC_ANTICLIP_LEVEL       0xA2
 129 #define DA9055_ALC_OFFSET_OP2M_L        0xA6
 130 #define DA9055_ALC_OFFSET_OP2U_L        0xA7
 131 #define DA9055_ALC_OFFSET_OP2M_R        0xAB
 132 #define DA9055_ALC_OFFSET_OP2U_R        0xAC
 133 #define DA9055_ALC_CIC_OP_LVL_CTRL      0xAD
 134 #define DA9055_ALC_CIC_OP_LVL_DATA      0xAE
 135 #define DA9055_DAC_NG_SETUP_TIME        0xAF
 136 #define DA9055_DAC_NG_OFF_THRESHOLD     0xB0
 137 #define DA9055_DAC_NG_ON_THRESHOLD      0xB1
 138 #define DA9055_DAC_NG_CTRL              0xB2
 139 
 140 /* SR bit fields */
 141 #define DA9055_SR_8000                  (0x1 << 0)
 142 #define DA9055_SR_11025                 (0x2 << 0)
 143 #define DA9055_SR_12000                 (0x3 << 0)
 144 #define DA9055_SR_16000                 (0x5 << 0)
 145 #define DA9055_SR_22050                 (0x6 << 0)
 146 #define DA9055_SR_24000                 (0x7 << 0)
 147 #define DA9055_SR_32000                 (0x9 << 0)
 148 #define DA9055_SR_44100                 (0xA << 0)
 149 #define DA9055_SR_48000                 (0xB << 0)
 150 #define DA9055_SR_88200                 (0xE << 0)
 151 #define DA9055_SR_96000                 (0xF << 0)
 152 
 153 /* REFERENCES bit fields */
 154 #define DA9055_BIAS_EN                  (1 << 3)
 155 #define DA9055_VMID_EN                  (1 << 7)
 156 
 157 /* PLL_CTRL bit fields */
 158 #define DA9055_PLL_INDIV_10_20_MHZ      (1 << 2)
 159 #define DA9055_PLL_SRM_EN               (1 << 6)
 160 #define DA9055_PLL_EN                   (1 << 7)
 161 
 162 /* AIF_CLK_MODE bit fields */
 163 #define DA9055_AIF_BCLKS_PER_WCLK_32    (0 << 0)
 164 #define DA9055_AIF_BCLKS_PER_WCLK_64    (1 << 0)
 165 #define DA9055_AIF_BCLKS_PER_WCLK_128   (2 << 0)
 166 #define DA9055_AIF_BCLKS_PER_WCLK_256   (3 << 0)
 167 #define DA9055_AIF_CLK_EN_SLAVE_MODE    (0 << 7)
 168 #define DA9055_AIF_CLK_EN_MASTER_MODE   (1 << 7)
 169 
 170 /* AIF_CTRL bit fields */
 171 #define DA9055_AIF_FORMAT_I2S_MODE      (0 << 0)
 172 #define DA9055_AIF_FORMAT_LEFT_J        (1 << 0)
 173 #define DA9055_AIF_FORMAT_RIGHT_J       (2 << 0)
 174 #define DA9055_AIF_FORMAT_DSP           (3 << 0)
 175 #define DA9055_AIF_WORD_S16_LE          (0 << 2)
 176 #define DA9055_AIF_WORD_S20_3LE         (1 << 2)
 177 #define DA9055_AIF_WORD_S24_LE          (2 << 2)
 178 #define DA9055_AIF_WORD_S32_LE          (3 << 2)
 179 
 180 /* MIC_L_CTRL bit fields */
 181 #define DA9055_MIC_L_MUTE_EN            (1 << 6)
 182 
 183 /* MIC_R_CTRL bit fields */
 184 #define DA9055_MIC_R_MUTE_EN            (1 << 6)
 185 
 186 /* MIXIN_L_CTRL bit fields */
 187 #define DA9055_MIXIN_L_MIX_EN           (1 << 3)
 188 
 189 /* MIXIN_R_CTRL bit fields */
 190 #define DA9055_MIXIN_R_MIX_EN           (1 << 3)
 191 
 192 /* ADC_L_CTRL bit fields */
 193 #define DA9055_ADC_L_EN                 (1 << 7)
 194 
 195 /* ADC_R_CTRL bit fields */
 196 #define DA9055_ADC_R_EN                 (1 << 7)
 197 
 198 /* DAC_L_CTRL bit fields */
 199 #define DA9055_DAC_L_MUTE_EN            (1 << 6)
 200 
 201 /* DAC_R_CTRL bit fields */
 202 #define DA9055_DAC_R_MUTE_EN            (1 << 6)
 203 
 204 /* HP_L_CTRL bit fields */
 205 #define DA9055_HP_L_AMP_OE              (1 << 3)
 206 
 207 /* HP_R_CTRL bit fields */
 208 #define DA9055_HP_R_AMP_OE              (1 << 3)
 209 
 210 /* LINE_CTRL bit fields */
 211 #define DA9055_LINE_AMP_OE              (1 << 3)
 212 
 213 /* MIXOUT_L_CTRL bit fields */
 214 #define DA9055_MIXOUT_L_MIX_EN          (1 << 3)
 215 
 216 /* MIXOUT_R_CTRL bit fields */
 217 #define DA9055_MIXOUT_R_MIX_EN          (1 << 3)
 218 
 219 /* MIC bias select bit fields */
 220 #define DA9055_MICBIAS2_EN              (1 << 6)
 221 
 222 /* ALC_CIC_OP_LEVEL_CTRL bit fields */
 223 #define DA9055_ALC_DATA_MIDDLE          (2 << 0)
 224 #define DA9055_ALC_DATA_TOP             (3 << 0)
 225 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT  (0 << 7)
 226 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
 227 
 228 #define DA9055_AIF_BCLK_MASK            (3 << 0)
 229 #define DA9055_AIF_CLK_MODE_MASK        (1 << 7)
 230 #define DA9055_AIF_FORMAT_MASK          (3 << 0)
 231 #define DA9055_AIF_WORD_LENGTH_MASK     (3 << 2)
 232 #define DA9055_GAIN_RAMPING_EN          (1 << 5)
 233 #define DA9055_MICBIAS_LEVEL_MASK       (3 << 4)
 234 
 235 #define DA9055_ALC_OFFSET_15_8          0x00FF00
 236 #define DA9055_ALC_OFFSET_17_16         0x030000
 237 #define DA9055_ALC_AVG_ITERATIONS       5
 238 
 239 struct pll_div {
 240         int fref;
 241         int fout;
 242         u8 frac_top;
 243         u8 frac_bot;
 244         u8 integer;
 245         u8 mode;        /* 0 = slave, 1 = master */
 246 };
 247 
 248 /* PLL divisor table */
 249 static const struct pll_div da9055_pll_div[] = {
 250         /* for MASTER mode, fs = 44.1Khz and its harmonics */
 251         {11289600, 2822400, 0x00, 0x00, 0x20, 1},       /* MCLK=11.2896Mhz */
 252         {12000000, 2822400, 0x03, 0x61, 0x1E, 1},       /* MCLK=12Mhz */
 253         {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1},       /* MCLK=12.288Mhz */
 254         {13000000, 2822400, 0x19, 0x45, 0x1B, 1},       /* MCLK=13Mhz */
 255         {13500000, 2822400, 0x18, 0x56, 0x1A, 1},       /* MCLK=13.5Mhz */
 256         {14400000, 2822400, 0x02, 0xD0, 0x19, 1},       /* MCLK=14.4Mhz */
 257         {19200000, 2822400, 0x1A, 0x1C, 0x12, 1},       /* MCLK=19.2Mhz */
 258         {19680000, 2822400, 0x0B, 0x6D, 0x12, 1},       /* MCLK=19.68Mhz */
 259         {19800000, 2822400, 0x07, 0xDD, 0x12, 1},       /* MCLK=19.8Mhz */
 260         /* for MASTER mode, fs = 48Khz and its harmonics */
 261         {11289600, 3072000, 0x1A, 0x8E, 0x22, 1},       /* MCLK=11.2896Mhz */
 262         {12000000, 3072000, 0x18, 0x93, 0x20, 1},       /* MCLK=12Mhz */
 263         {12288000, 3072000, 0x00, 0x00, 0x20, 1},       /* MCLK=12.288Mhz */
 264         {13000000, 3072000, 0x07, 0xEA, 0x1E, 1},       /* MCLK=13Mhz */
 265         {13500000, 3072000, 0x04, 0x11, 0x1D, 1},       /* MCLK=13.5Mhz */
 266         {14400000, 3072000, 0x09, 0xD0, 0x1B, 1},       /* MCLK=14.4Mhz */
 267         {19200000, 3072000, 0x0F, 0x5C, 0x14, 1},       /* MCLK=19.2Mhz */
 268         {19680000, 3072000, 0x1F, 0x60, 0x13, 1},       /* MCLK=19.68Mhz */
 269         {19800000, 3072000, 0x1B, 0x80, 0x13, 1},       /* MCLK=19.8Mhz */
 270         /* for SLAVE mode with SRM */
 271         {11289600, 2822400, 0x0D, 0x47, 0x21, 0},       /* MCLK=11.2896Mhz */
 272         {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0},       /* MCLK=12Mhz */
 273         {12288000, 2822400, 0x16, 0x66, 0x1E, 0},       /* MCLK=12.288Mhz */
 274         {13000000, 2822400, 0x00, 0x98, 0x1D, 0},       /* MCLK=13Mhz */
 275         {13500000, 2822400, 0x1E, 0x33, 0x1B, 0},       /* MCLK=13.5Mhz */
 276         {14400000, 2822400, 0x06, 0x50, 0x1A, 0},       /* MCLK=14.4Mhz */
 277         {19200000, 2822400, 0x14, 0xBC, 0x13, 0},       /* MCLK=19.2Mhz */
 278         {19680000, 2822400, 0x05, 0x66, 0x13, 0},       /* MCLK=19.68Mhz */
 279         {19800000, 2822400, 0x01, 0xAE, 0x13, 0},       /* MCLK=19.8Mhz  */
 280 };
 281 
 282 enum clk_src {
 283         DA9055_CLKSRC_MCLK
 284 };
 285 
 286 /* Gain and Volume */
 287 
 288 static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
 289         0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
 290         /* -54dB to 15dB */
 291         0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
 292 );
 293 
 294 static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
 295         0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
 296         /* -78dB to 12dB */
 297         0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
 298 );
 299 
 300 static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
 301         0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
 302         /* 0dB to 36dB */
 303         0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
 304 );
 305 
 306 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
 307 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
 308 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
 309 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
 310 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
 311 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
 312 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
 313 
 314 /* ADC and DAC high pass filter cutoff value */
 315 static const char * const da9055_hpf_cutoff_txt[] = {
 316         "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
 317 };
 318 
 319 static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff,
 320                             DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt);
 321 
 322 static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff,
 323                             DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt);
 324 
 325 /* ADC and DAC voice mode (8kHz) high pass cutoff value */
 326 static const char * const da9055_vf_cutoff_txt[] = {
 327         "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 328 };
 329 
 330 static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff,
 331                             DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt);
 332 
 333 static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff,
 334                             DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt);
 335 
 336 /* Gain ramping rate value */
 337 static const char * const da9055_gain_ramping_txt[] = {
 338         "nominal rate", "nominal rate * 4", "nominal rate * 8",
 339         "nominal rate / 8"
 340 };
 341 
 342 static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate,
 343                             DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt);
 344 
 345 /* DAC noise gate setup time value */
 346 static const char * const da9055_dac_ng_setup_time_txt[] = {
 347         "256 samples", "512 samples", "1024 samples", "2048 samples"
 348 };
 349 
 350 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time,
 351                             DA9055_DAC_NG_SETUP_TIME, 0,
 352                             da9055_dac_ng_setup_time_txt);
 353 
 354 /* DAC noise gate rampup rate value */
 355 static const char * const da9055_dac_ng_rampup_txt[] = {
 356         "0.02 ms/dB", "0.16 ms/dB"
 357 };
 358 
 359 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate,
 360                             DA9055_DAC_NG_SETUP_TIME, 2,
 361                             da9055_dac_ng_rampup_txt);
 362 
 363 /* DAC noise gate rampdown rate value */
 364 static const char * const da9055_dac_ng_rampdown_txt[] = {
 365         "0.64 ms/dB", "20.48 ms/dB"
 366 };
 367 
 368 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate,
 369                             DA9055_DAC_NG_SETUP_TIME, 3,
 370                             da9055_dac_ng_rampdown_txt);
 371 
 372 /* DAC soft mute rate value */
 373 static const char * const da9055_dac_soft_mute_rate_txt[] = {
 374         "1", "2", "4", "8", "16", "32", "64"
 375 };
 376 
 377 static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate,
 378                             DA9055_DAC_FILTERS5, 4,
 379                             da9055_dac_soft_mute_rate_txt);
 380 
 381 /* DAC routing select */
 382 static const char * const da9055_dac_src_txt[] = {
 383         "ADC output left", "ADC output right", "AIF input left",
 384         "AIF input right"
 385 };
 386 
 387 static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src,
 388                             DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt);
 389 
 390 static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src,
 391                             DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt);
 392 
 393 /* MIC PGA Left source select */
 394 static const char * const da9055_mic_l_src_txt[] = {
 395         "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
 396 };
 397 
 398 static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src,
 399                             DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt);
 400 
 401 /* MIC PGA Right source select */
 402 static const char * const da9055_mic_r_src_txt[] = {
 403         "MIC2_R_L", "MIC2_R", "MIC2_L"
 404 };
 405 
 406 static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src,
 407                             DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt);
 408 
 409 /* ALC Input Signal Tracking rate select */
 410 static const char * const da9055_signal_tracking_rate_txt[] = {
 411         "1/4", "1/16", "1/256", "1/65536"
 412 };
 413 
 414 static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate,
 415                             DA9055_ALC_CTRL3, 4,
 416                             da9055_signal_tracking_rate_txt);
 417 
 418 static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate,
 419                             DA9055_ALC_CTRL3, 6,
 420                             da9055_signal_tracking_rate_txt);
 421 
 422 /* ALC Attack Rate select */
 423 static const char * const da9055_attack_rate_txt[] = {
 424         "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
 425         "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
 426 };
 427 
 428 static SOC_ENUM_SINGLE_DECL(da9055_attack_rate,
 429                             DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt);
 430 
 431 /* ALC Release Rate select */
 432 static const char * const da9055_release_rate_txt[] = {
 433         "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
 434         "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
 435 };
 436 
 437 static SOC_ENUM_SINGLE_DECL(da9055_release_rate,
 438                             DA9055_ALC_CTRL2, 4, da9055_release_rate_txt);
 439 
 440 /* ALC Hold Time select */
 441 static const char * const da9055_hold_time_txt[] = {
 442         "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
 443         "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
 444         "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
 445 };
 446 
 447 static SOC_ENUM_SINGLE_DECL(da9055_hold_time,
 448                             DA9055_ALC_CTRL3, 0, da9055_hold_time_txt);
 449 
 450 static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val)
 451 {
 452         int mid_data, top_data;
 453         int sum = 0;
 454         u8 iteration;
 455 
 456         for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
 457              iteration++) {
 458                 /* Select the left or right channel and capture data */
 459                 snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
 460 
 461                 /* Select middle 8 bits for read back from data register */
 462                 snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
 463                               reg_val | DA9055_ALC_DATA_MIDDLE);
 464                 mid_data = snd_soc_component_read32(component, DA9055_ALC_CIC_OP_LVL_DATA);
 465 
 466                 /* Select top 8 bits for read back from data register */
 467                 snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
 468                               reg_val | DA9055_ALC_DATA_TOP);
 469                 top_data = snd_soc_component_read32(component, DA9055_ALC_CIC_OP_LVL_DATA);
 470 
 471                 sum += ((mid_data << 8) | (top_data << 16));
 472         }
 473 
 474         return sum / DA9055_ALC_AVG_ITERATIONS;
 475 }
 476 
 477 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
 478                              struct snd_ctl_elem_value *ucontrol)
 479 {
 480         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 481         u8 reg_val, adc_left, adc_right, mic_left, mic_right;
 482         int avg_left_data, avg_right_data, offset_l, offset_r;
 483 
 484         if (ucontrol->value.integer.value[0]) {
 485                 /*
 486                  * While enabling ALC (or ALC sync mode), calibration of the DC
 487                  * offsets must be done first
 488                  */
 489 
 490                 /* Save current values from Mic control registers */
 491                 mic_left = snd_soc_component_read32(component, DA9055_MIC_L_CTRL);
 492                 mic_right = snd_soc_component_read32(component, DA9055_MIC_R_CTRL);
 493 
 494                 /* Mute Mic PGA Left and Right */
 495                 snd_soc_component_update_bits(component, DA9055_MIC_L_CTRL,
 496                                     DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
 497                 snd_soc_component_update_bits(component, DA9055_MIC_R_CTRL,
 498                                     DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
 499 
 500                 /* Save current values from ADC control registers */
 501                 adc_left = snd_soc_component_read32(component, DA9055_ADC_L_CTRL);
 502                 adc_right = snd_soc_component_read32(component, DA9055_ADC_R_CTRL);
 503 
 504                 /* Enable ADC Left and Right */
 505                 snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
 506                                     DA9055_ADC_L_EN, DA9055_ADC_L_EN);
 507                 snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
 508                                     DA9055_ADC_R_EN, DA9055_ADC_R_EN);
 509 
 510                 /* Calculate average for Left and Right data */
 511                 /* Left Data */
 512                 avg_left_data = da9055_get_alc_data(component,
 513                                 DA9055_ALC_CIC_OP_CHANNEL_LEFT);
 514                 /* Right Data */
 515                 avg_right_data = da9055_get_alc_data(component,
 516                                  DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
 517 
 518                 /* Calculate DC offset */
 519                 offset_l = -avg_left_data;
 520                 offset_r = -avg_right_data;
 521 
 522                 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
 523                 snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val);
 524                 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
 525                 snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val);
 526 
 527                 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
 528                 snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val);
 529                 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
 530                 snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val);
 531 
 532                 /* Restore original values of ADC control registers */
 533                 snd_soc_component_write(component, DA9055_ADC_L_CTRL, adc_left);
 534                 snd_soc_component_write(component, DA9055_ADC_R_CTRL, adc_right);
 535 
 536                 /* Restore original values of Mic control registers */
 537                 snd_soc_component_write(component, DA9055_MIC_L_CTRL, mic_left);
 538                 snd_soc_component_write(component, DA9055_MIC_R_CTRL, mic_right);
 539         }
 540 
 541         return snd_soc_put_volsw(kcontrol, ucontrol);
 542 }
 543 
 544 static const struct snd_kcontrol_new da9055_snd_controls[] = {
 545 
 546         /* Volume controls */
 547         SOC_DOUBLE_R_TLV("Mic Volume",
 548                          DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
 549                          0, 0x7, 0, mic_vol_tlv),
 550         SOC_DOUBLE_R_TLV("Aux Volume",
 551                          DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
 552                          0, 0x3f, 0, aux_vol_tlv),
 553         SOC_DOUBLE_R_TLV("Mixin PGA Volume",
 554                          DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
 555                          0, 0xf, 0, mixin_gain_tlv),
 556         SOC_DOUBLE_R_TLV("ADC Volume",
 557                          DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
 558                          0, 0x7f, 0, digital_gain_tlv),
 559 
 560         SOC_DOUBLE_R_TLV("DAC Volume",
 561                          DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
 562                          0, 0x7f, 0, digital_gain_tlv),
 563         SOC_DOUBLE_R_TLV("Headphone Volume",
 564                          DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
 565                          0, 0x3f, 0, hp_vol_tlv),
 566         SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
 567                        lineout_vol_tlv),
 568 
 569         /* DAC Equalizer controls */
 570         SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
 571         SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
 572                        eq_gain_tlv),
 573         SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
 574                        eq_gain_tlv),
 575         SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
 576                        eq_gain_tlv),
 577         SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
 578                        eq_gain_tlv),
 579         SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
 580                        eq_gain_tlv),
 581 
 582         /* High Pass Filter and Voice Mode controls */
 583         SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
 584         SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
 585         SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
 586         SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
 587 
 588         SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
 589         SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
 590         SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
 591         SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
 592 
 593         /* Mute controls */
 594         SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
 595                      DA9055_MIC_R_CTRL, 6, 1, 0),
 596         SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
 597                      DA9055_AUX_R_CTRL, 6, 1, 0),
 598         SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
 599                      DA9055_MIXIN_R_CTRL, 6, 1, 0),
 600         SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
 601                      DA9055_ADC_R_CTRL, 6, 1, 0),
 602         SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
 603                      DA9055_HP_R_CTRL, 6, 1, 0),
 604         SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
 605         SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
 606         SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
 607 
 608         /* Zero Cross controls */
 609         SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
 610                      DA9055_AUX_R_CTRL, 4, 1, 0),
 611         SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
 612                      DA9055_MIXIN_R_CTRL, 4, 1, 0),
 613         SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
 614                      DA9055_HP_R_CTRL, 4, 1, 0),
 615         SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
 616 
 617         /* Gain Ramping controls */
 618         SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
 619                      DA9055_AUX_R_CTRL, 5, 1, 0),
 620         SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
 621                      DA9055_MIXIN_R_CTRL, 5, 1, 0),
 622         SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
 623                      DA9055_ADC_R_CTRL, 5, 1, 0),
 624         SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
 625                      DA9055_DAC_R_CTRL, 5, 1, 0),
 626         SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
 627                      DA9055_HP_R_CTRL, 5, 1, 0),
 628         SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
 629         SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
 630 
 631         /* DAC Noise Gate controls */
 632         SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
 633         SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
 634                    0, 0x7, 0),
 635         SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
 636                    0, 0x7, 0),
 637         SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
 638         SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
 639         SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
 640 
 641         /* DAC Invertion control */
 642         SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
 643         SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
 644 
 645         /* DMIC controls */
 646         SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
 647                      DA9055_MIXIN_R_SELECT, 7, 1, 0),
 648 
 649         /* ALC Controls */
 650         SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
 651                        snd_soc_get_volsw, da9055_put_alc_sw),
 652         SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
 653                        snd_soc_get_volsw, da9055_put_alc_sw),
 654         SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
 655         SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
 656                    7, 1, 0),
 657         SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
 658                    0, 0x7f, 0),
 659         SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
 660                        0, 0x3f, 1, alc_threshold_tlv),
 661         SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
 662                        0, 0x3f, 1, alc_threshold_tlv),
 663         SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
 664                        0, 0x3f, 1, alc_threshold_tlv),
 665         SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
 666                        4, 0xf, 0, alc_gain_tlv),
 667         SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
 668                        0, 0xf, 0, alc_gain_tlv),
 669         SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
 670                        DA9055_ALC_ANA_GAIN_LIMITS,
 671                        0, 0x7, 0, alc_analog_gain_tlv),
 672         SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
 673                        DA9055_ALC_ANA_GAIN_LIMITS,
 674                        4, 0x7, 0, alc_analog_gain_tlv),
 675         SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
 676         SOC_ENUM("ALC Release Rate", da9055_release_rate),
 677         SOC_ENUM("ALC Hold Time", da9055_hold_time),
 678         /*
 679          * Rate at which input signal envelope is tracked as the signal gets
 680          * larger
 681          */
 682         SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
 683         /*
 684          * Rate at which input signal envelope is tracked as the signal gets
 685          * smaller
 686          */
 687         SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
 688 };
 689 
 690 /* DAPM Controls */
 691 
 692 /* Mic PGA Left Source */
 693 static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
 694 SOC_DAPM_ENUM("Route", da9055_mic_l_src);
 695 
 696 /* Mic PGA Right Source */
 697 static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
 698 SOC_DAPM_ENUM("Route", da9055_mic_r_src);
 699 
 700 /* In Mixer Left */
 701 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
 702         SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
 703         SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
 704         SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
 705 };
 706 
 707 /* In Mixer Right */
 708 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
 709         SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
 710         SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
 711         SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
 712         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
 713 };
 714 
 715 /* DAC Left Source */
 716 static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
 717 SOC_DAPM_ENUM("Route", da9055_dac_l_src);
 718 
 719 /* DAC Right Source */
 720 static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
 721 SOC_DAPM_ENUM("Route", da9055_dac_r_src);
 722 
 723 /* Out Mixer Left */
 724 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
 725         SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
 726         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
 727         SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
 728         SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
 729         SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
 730                         4, 1, 0),
 731         SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
 732                         5, 1, 0),
 733         SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
 734                         6, 1, 0),
 735 };
 736 
 737 /* Out Mixer Right */
 738 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
 739         SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
 740         SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
 741         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
 742         SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
 743         SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
 744                         4, 1, 0),
 745         SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
 746                         5, 1, 0),
 747         SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
 748                         6, 1, 0),
 749 };
 750 
 751 /* Headphone Output Enable */
 752 static const struct snd_kcontrol_new da9055_dapm_hp_l_control =
 753 SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0);
 754 
 755 static const struct snd_kcontrol_new da9055_dapm_hp_r_control =
 756 SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0);
 757 
 758 /* Lineout Output Enable */
 759 static const struct snd_kcontrol_new da9055_dapm_lineout_control =
 760 SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0);
 761 
 762 /* DAPM widgets */
 763 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
 764         /* Input Side */
 765 
 766         /* Input Lines */
 767         SND_SOC_DAPM_INPUT("MIC1"),
 768         SND_SOC_DAPM_INPUT("MIC2"),
 769         SND_SOC_DAPM_INPUT("AUXL"),
 770         SND_SOC_DAPM_INPUT("AUXR"),
 771 
 772         /* MUXs for Mic PGA source selection */
 773         SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
 774                          &da9055_mic_l_mux_controls),
 775         SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
 776                          &da9055_mic_r_mux_controls),
 777 
 778         /* Input PGAs */
 779         SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
 780         SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
 781         SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
 782         SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
 783         SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
 784         SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
 785 
 786         SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
 787         SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
 788         SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
 789 
 790         /* Input Mixers */
 791         SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
 792                            &da9055_dapm_mixinl_controls[0],
 793                            ARRAY_SIZE(da9055_dapm_mixinl_controls)),
 794         SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
 795                            &da9055_dapm_mixinr_controls[0],
 796                            ARRAY_SIZE(da9055_dapm_mixinr_controls)),
 797 
 798         /* ADCs */
 799         SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
 800         SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
 801 
 802         /* Output Side */
 803 
 804         /* MUXs for DAC source selection */
 805         SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
 806                          &da9055_dac_l_mux_controls),
 807         SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
 808                          &da9055_dac_r_mux_controls),
 809 
 810         /* AIF input */
 811         SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
 812         SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
 813 
 814         /* DACs */
 815         SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
 816         SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
 817 
 818         /* Output Mixers */
 819         SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
 820                            &da9055_dapm_mixoutl_controls[0],
 821                            ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
 822         SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
 823                            &da9055_dapm_mixoutr_controls[0],
 824                            ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
 825 
 826         /* Output Enable Switches */
 827         SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
 828                             &da9055_dapm_hp_l_control),
 829         SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
 830                             &da9055_dapm_hp_r_control),
 831         SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
 832                             &da9055_dapm_lineout_control),
 833 
 834         /* Output PGAs */
 835         SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
 836         SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
 837         SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
 838         SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
 839         SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
 840 
 841         /* Output Lines */
 842         SND_SOC_DAPM_OUTPUT("HPL"),
 843         SND_SOC_DAPM_OUTPUT("HPR"),
 844         SND_SOC_DAPM_OUTPUT("LINE"),
 845 };
 846 
 847 /* DAPM audio route definition */
 848 static const struct snd_soc_dapm_route da9055_audio_map[] = {
 849         /* Dest       Connecting Widget    source */
 850 
 851         /* Input path */
 852         {"Mic Left Source", "MIC1_P_N", "MIC1"},
 853         {"Mic Left Source", "MIC1_P", "MIC1"},
 854         {"Mic Left Source", "MIC1_N", "MIC1"},
 855         {"Mic Left Source", "MIC2_L", "MIC2"},
 856 
 857         {"Mic Right Source", "MIC2_R_L", "MIC2"},
 858         {"Mic Right Source", "MIC2_R", "MIC2"},
 859         {"Mic Right Source", "MIC2_L", "MIC2"},
 860 
 861         {"Mic Left", NULL, "Mic Left Source"},
 862         {"Mic Right", NULL, "Mic Right Source"},
 863 
 864         {"Aux Left", NULL, "AUXL"},
 865         {"Aux Right", NULL, "AUXR"},
 866 
 867         {"In Mixer Left", "Mic Left Switch", "Mic Left"},
 868         {"In Mixer Left", "Mic Right Switch", "Mic Right"},
 869         {"In Mixer Left", "Aux Left Switch", "Aux Left"},
 870 
 871         {"In Mixer Right", "Mic Right Switch", "Mic Right"},
 872         {"In Mixer Right", "Mic Left Switch", "Mic Left"},
 873         {"In Mixer Right", "Aux Right Switch", "Aux Right"},
 874         {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
 875 
 876         {"MIXIN Left", NULL, "In Mixer Left"},
 877         {"ADC Left", NULL, "MIXIN Left"},
 878 
 879         {"MIXIN Right", NULL, "In Mixer Right"},
 880         {"ADC Right", NULL, "MIXIN Right"},
 881 
 882         {"ADC Left", NULL, "AIF"},
 883         {"ADC Right", NULL, "AIF"},
 884 
 885         /* Output path */
 886         {"AIFIN Left", NULL, "AIF"},
 887         {"AIFIN Right", NULL, "AIF"},
 888 
 889         {"DAC Left Source", "ADC output left", "ADC Left"},
 890         {"DAC Left Source", "ADC output right", "ADC Right"},
 891         {"DAC Left Source", "AIF input left", "AIFIN Left"},
 892         {"DAC Left Source", "AIF input right", "AIFIN Right"},
 893 
 894         {"DAC Right Source", "ADC output left", "ADC Left"},
 895         {"DAC Right Source", "ADC output right", "ADC Right"},
 896         {"DAC Right Source", "AIF input left", "AIFIN Left"},
 897         {"DAC Right Source", "AIF input right", "AIFIN Right"},
 898 
 899         {"DAC Left", NULL, "DAC Left Source"},
 900         {"DAC Right", NULL, "DAC Right Source"},
 901 
 902         {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
 903         {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
 904         {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
 905         {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
 906         {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
 907         {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
 908         {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
 909 
 910         {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
 911         {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
 912         {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
 913         {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
 914         {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
 915         {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
 916         {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
 917 
 918         {"MIXOUT Left", NULL, "Out Mixer Left"},
 919         {"Headphone Left Enable", "Switch", "MIXOUT Left"},
 920         {"Headphone Left", NULL, "Headphone Left Enable"},
 921         {"Headphone Left", NULL, "Charge Pump"},
 922         {"HPL", NULL, "Headphone Left"},
 923 
 924         {"MIXOUT Right", NULL, "Out Mixer Right"},
 925         {"Headphone Right Enable", "Switch", "MIXOUT Right"},
 926         {"Headphone Right", NULL, "Headphone Right Enable"},
 927         {"Headphone Right", NULL, "Charge Pump"},
 928         {"HPR", NULL, "Headphone Right"},
 929 
 930         {"MIXOUT Right", NULL, "Out Mixer Right"},
 931         {"Lineout Enable", "Switch", "MIXOUT Right"},
 932         {"Lineout", NULL, "Lineout Enable"},
 933         {"LINE", NULL, "Lineout"},
 934 };
 935 
 936 /* Codec private data */
 937 struct da9055_priv {
 938         struct regmap *regmap;
 939         unsigned int mclk_rate;
 940         int master;
 941         struct da9055_platform_data *pdata;
 942 };
 943 
 944 static const struct reg_default da9055_reg_defaults[] = {
 945         { 0x21, 0x10 },
 946         { 0x22, 0x0A },
 947         { 0x23, 0x00 },
 948         { 0x24, 0x00 },
 949         { 0x25, 0x00 },
 950         { 0x26, 0x00 },
 951         { 0x27, 0x0C },
 952         { 0x28, 0x01 },
 953         { 0x29, 0x08 },
 954         { 0x2A, 0x32 },
 955         { 0x2B, 0x00 },
 956         { 0x30, 0x35 },
 957         { 0x31, 0x35 },
 958         { 0x32, 0x00 },
 959         { 0x33, 0x00 },
 960         { 0x34, 0x03 },
 961         { 0x35, 0x03 },
 962         { 0x36, 0x6F },
 963         { 0x37, 0x6F },
 964         { 0x38, 0x80 },
 965         { 0x39, 0x01 },
 966         { 0x3A, 0x01 },
 967         { 0x40, 0x00 },
 968         { 0x41, 0x88 },
 969         { 0x42, 0x88 },
 970         { 0x43, 0x08 },
 971         { 0x44, 0x80 },
 972         { 0x45, 0x6F },
 973         { 0x46, 0x6F },
 974         { 0x47, 0x61 },
 975         { 0x48, 0x35 },
 976         { 0x49, 0x35 },
 977         { 0x4A, 0x35 },
 978         { 0x4B, 0x00 },
 979         { 0x4C, 0x00 },
 980         { 0x60, 0x44 },
 981         { 0x61, 0x44 },
 982         { 0x62, 0x00 },
 983         { 0x63, 0x40 },
 984         { 0x64, 0x40 },
 985         { 0x65, 0x40 },
 986         { 0x66, 0x40 },
 987         { 0x67, 0x40 },
 988         { 0x68, 0x40 },
 989         { 0x69, 0x48 },
 990         { 0x6A, 0x40 },
 991         { 0x6B, 0x41 },
 992         { 0x6C, 0x40 },
 993         { 0x6D, 0x40 },
 994         { 0x6E, 0x10 },
 995         { 0x6F, 0x10 },
 996         { 0x90, 0x80 },
 997         { 0x92, 0x02 },
 998         { 0x93, 0x00 },
 999         { 0x99, 0x00 },
1000         { 0x9A, 0x00 },
1001         { 0x9B, 0x00 },
1002         { 0x9C, 0x3F },
1003         { 0x9D, 0x00 },
1004         { 0x9E, 0x3F },
1005         { 0x9F, 0xFF },
1006         { 0xA0, 0x71 },
1007         { 0xA1, 0x00 },
1008         { 0xA2, 0x00 },
1009         { 0xA6, 0x00 },
1010         { 0xA7, 0x00 },
1011         { 0xAB, 0x00 },
1012         { 0xAC, 0x00 },
1013         { 0xAD, 0x00 },
1014         { 0xAF, 0x08 },
1015         { 0xB0, 0x00 },
1016         { 0xB1, 0x00 },
1017         { 0xB2, 0x00 },
1018 };
1019 
1020 static bool da9055_volatile_register(struct device *dev,
1021                                      unsigned int reg)
1022 {
1023         switch (reg) {
1024         case DA9055_STATUS1:
1025         case DA9055_PLL_STATUS:
1026         case DA9055_AUX_L_GAIN_STATUS:
1027         case DA9055_AUX_R_GAIN_STATUS:
1028         case DA9055_MIC_L_GAIN_STATUS:
1029         case DA9055_MIC_R_GAIN_STATUS:
1030         case DA9055_MIXIN_L_GAIN_STATUS:
1031         case DA9055_MIXIN_R_GAIN_STATUS:
1032         case DA9055_ADC_L_GAIN_STATUS:
1033         case DA9055_ADC_R_GAIN_STATUS:
1034         case DA9055_DAC_L_GAIN_STATUS:
1035         case DA9055_DAC_R_GAIN_STATUS:
1036         case DA9055_HP_L_GAIN_STATUS:
1037         case DA9055_HP_R_GAIN_STATUS:
1038         case DA9055_LINE_GAIN_STATUS:
1039         case DA9055_ALC_CIC_OP_LVL_DATA:
1040                 return true;
1041         default:
1042                 return false;
1043         }
1044 }
1045 
1046 /* Set DAI word length */
1047 static int da9055_hw_params(struct snd_pcm_substream *substream,
1048                             struct snd_pcm_hw_params *params,
1049                             struct snd_soc_dai *dai)
1050 {
1051         struct snd_soc_component *component = dai->component;
1052         struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1053         u8 aif_ctrl, fs;
1054         u32 sysclk;
1055 
1056         switch (params_width(params)) {
1057         case 16:
1058                 aif_ctrl = DA9055_AIF_WORD_S16_LE;
1059                 break;
1060         case 20:
1061                 aif_ctrl = DA9055_AIF_WORD_S20_3LE;
1062                 break;
1063         case 24:
1064                 aif_ctrl = DA9055_AIF_WORD_S24_LE;
1065                 break;
1066         case 32:
1067                 aif_ctrl = DA9055_AIF_WORD_S32_LE;
1068                 break;
1069         default:
1070                 return -EINVAL;
1071         }
1072 
1073         /* Set AIF format */
1074         snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
1075                             aif_ctrl);
1076 
1077         switch (params_rate(params)) {
1078         case 8000:
1079                 fs              = DA9055_SR_8000;
1080                 sysclk          = 3072000;
1081                 break;
1082         case 11025:
1083                 fs              = DA9055_SR_11025;
1084                 sysclk          = 2822400;
1085                 break;
1086         case 12000:
1087                 fs              = DA9055_SR_12000;
1088                 sysclk          = 3072000;
1089                 break;
1090         case 16000:
1091                 fs              = DA9055_SR_16000;
1092                 sysclk          = 3072000;
1093                 break;
1094         case 22050:
1095                 fs              = DA9055_SR_22050;
1096                 sysclk          = 2822400;
1097                 break;
1098         case 32000:
1099                 fs              = DA9055_SR_32000;
1100                 sysclk          = 3072000;
1101                 break;
1102         case 44100:
1103                 fs              = DA9055_SR_44100;
1104                 sysclk          = 2822400;
1105                 break;
1106         case 48000:
1107                 fs              = DA9055_SR_48000;
1108                 sysclk          = 3072000;
1109                 break;
1110         case 88200:
1111                 fs              = DA9055_SR_88200;
1112                 sysclk          = 2822400;
1113                 break;
1114         case 96000:
1115                 fs              = DA9055_SR_96000;
1116                 sysclk          = 3072000;
1117                 break;
1118         default:
1119                 return -EINVAL;
1120         }
1121 
1122         if (da9055->mclk_rate) {
1123                 /* PLL Mode, Write actual FS */
1124                 snd_soc_component_write(component, DA9055_SR, fs);
1125         } else {
1126                 /*
1127                  * Non-PLL Mode
1128                  * When PLL is bypassed, chip assumes constant MCLK of
1129                  * 12.288MHz and uses sample rate value to divide this MCLK
1130                  * to derive its sys clk. As sys clk has to be 256 * Fs, we
1131                  * need to write constant sample rate i.e. 48KHz.
1132                  */
1133                 snd_soc_component_write(component, DA9055_SR, DA9055_SR_48000);
1134         }
1135 
1136         if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
1137                 /* PLL Mode */
1138                 if (!da9055->master) {
1139                         /* PLL slave mode, enable PLL and also SRM */
1140                         snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
1141                                             DA9055_PLL_EN | DA9055_PLL_SRM_EN,
1142                                             DA9055_PLL_EN | DA9055_PLL_SRM_EN);
1143                 } else {
1144                         /* PLL master mode, only enable PLL */
1145                         snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
1146                                             DA9055_PLL_EN, DA9055_PLL_EN);
1147                 }
1148         } else {
1149                 /* Non PLL Mode, disable PLL */
1150                 snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1151         }
1152 
1153         return 0;
1154 }
1155 
1156 /* Set DAI mode and Format */
1157 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1158 {
1159         struct snd_soc_component *component = codec_dai->component;
1160         struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1161         u8 aif_clk_mode, aif_ctrl, mode;
1162 
1163         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1164         case SND_SOC_DAIFMT_CBM_CFM:
1165                 /* DA9055 in I2S Master Mode */
1166                 mode = 1;
1167                 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
1168                 break;
1169         case SND_SOC_DAIFMT_CBS_CFS:
1170                 /* DA9055 in I2S Slave Mode */
1171                 mode = 0;
1172                 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
1173                 break;
1174         default:
1175                 return -EINVAL;
1176         }
1177 
1178         /* Don't allow change of mode if PLL is enabled */
1179         if ((snd_soc_component_read32(component, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
1180             (da9055->master != mode))
1181                 return -EINVAL;
1182 
1183         da9055->master = mode;
1184 
1185         /* Only I2S is supported */
1186         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1187         case SND_SOC_DAIFMT_I2S:
1188                 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
1189                 break;
1190         case SND_SOC_DAIFMT_LEFT_J:
1191                 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
1192                 break;
1193         case SND_SOC_DAIFMT_RIGHT_J:
1194                 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
1195                 break;
1196         case SND_SOC_DAIFMT_DSP_A:
1197                 aif_ctrl = DA9055_AIF_FORMAT_DSP;
1198                 break;
1199         default:
1200                 return -EINVAL;
1201         }
1202 
1203         /* By default only 32 BCLK per WCLK is supported */
1204         aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
1205 
1206         snd_soc_component_update_bits(component, DA9055_AIF_CLK_MODE,
1207                             (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
1208                             aif_clk_mode);
1209         snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
1210                             aif_ctrl);
1211         return 0;
1212 }
1213 
1214 static int da9055_mute(struct snd_soc_dai *dai, int mute)
1215 {
1216         struct snd_soc_component *component = dai->component;
1217 
1218         if (mute) {
1219                 snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1220                                     DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
1221                 snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1222                                     DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
1223         } else {
1224                 snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1225                                     DA9055_DAC_L_MUTE_EN, 0);
1226                 snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1227                                     DA9055_DAC_R_MUTE_EN, 0);
1228         }
1229 
1230         return 0;
1231 }
1232 
1233 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1234                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1235 
1236 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1237                                  int clk_id, unsigned int freq, int dir)
1238 {
1239         struct snd_soc_component *component = codec_dai->component;
1240         struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1241 
1242         switch (clk_id) {
1243         case DA9055_CLKSRC_MCLK:
1244                 switch (freq) {
1245                 case 11289600:
1246                 case 12000000:
1247                 case 12288000:
1248                 case 13000000:
1249                 case 13500000:
1250                 case 14400000:
1251                 case 19200000:
1252                 case 19680000:
1253                 case 19800000:
1254                         da9055->mclk_rate = freq;
1255                         return 0;
1256                 default:
1257                         dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1258                                 freq);
1259                         return -EINVAL;
1260                 }
1261                 break;
1262         default:
1263                 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1264                 return -EINVAL;
1265         }
1266 }
1267 
1268 /*
1269  * da9055_set_dai_pll   : Configure the codec PLL
1270  * @param codec_dai     : Pointer to codec DAI
1271  * @param pll_id        : da9055 has only one pll, so pll_id is always zero
1272  * @param fref          : Input MCLK frequency
1273  * @param fout          : FsDM value
1274  * @return int          : Zero for success, negative error code for error
1275  *
1276  * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1277  *       13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
1278  */
1279 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1280                               int source, unsigned int fref, unsigned int fout)
1281 {
1282         struct snd_soc_component *component = codec_dai->component;
1283         struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1284 
1285         u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
1286 
1287         /* Disable PLL before setting the divisors */
1288         snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1289 
1290         /* In slave mode, there is only one set of divisors */
1291         if (!da9055->master && (fout != 2822400))
1292                 goto pll_err;
1293 
1294         /* Search pll div array for correct divisors */
1295         for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
1296                 /* Check fref, mode  and fout */
1297                 if ((fref == da9055_pll_div[cnt].fref) &&
1298                     (da9055->master ==  da9055_pll_div[cnt].mode) &&
1299                     (fout == da9055_pll_div[cnt].fout)) {
1300                         /* All match, pick up divisors */
1301                         pll_frac_top = da9055_pll_div[cnt].frac_top;
1302                         pll_frac_bot = da9055_pll_div[cnt].frac_bot;
1303                         pll_integer = da9055_pll_div[cnt].integer;
1304                         break;
1305                 }
1306         }
1307         if (cnt >= ARRAY_SIZE(da9055_pll_div))
1308                 goto pll_err;
1309 
1310         /* Write PLL dividers */
1311         snd_soc_component_write(component, DA9055_PLL_FRAC_TOP, pll_frac_top);
1312         snd_soc_component_write(component, DA9055_PLL_FRAC_BOT, pll_frac_bot);
1313         snd_soc_component_write(component, DA9055_PLL_INTEGER, pll_integer);
1314 
1315         return 0;
1316 pll_err:
1317         dev_err(codec_dai->dev, "Error in setting up PLL\n");
1318         return -EINVAL;
1319 }
1320 
1321 /* DAI operations */
1322 static const struct snd_soc_dai_ops da9055_dai_ops = {
1323         .hw_params      = da9055_hw_params,
1324         .set_fmt        = da9055_set_dai_fmt,
1325         .set_sysclk     = da9055_set_dai_sysclk,
1326         .set_pll        = da9055_set_dai_pll,
1327         .digital_mute   = da9055_mute,
1328 };
1329 
1330 static struct snd_soc_dai_driver da9055_dai = {
1331         .name = "da9055-hifi",
1332         /* Playback Capabilities */
1333         .playback = {
1334                 .stream_name = "Playback",
1335                 .channels_min = 1,
1336                 .channels_max = 2,
1337                 .rates = SNDRV_PCM_RATE_8000_96000,
1338                 .formats = DA9055_FORMATS,
1339         },
1340         /* Capture Capabilities */
1341         .capture = {
1342                 .stream_name = "Capture",
1343                 .channels_min = 1,
1344                 .channels_max = 2,
1345                 .rates = SNDRV_PCM_RATE_8000_96000,
1346                 .formats = DA9055_FORMATS,
1347         },
1348         .ops = &da9055_dai_ops,
1349         .symmetric_rates = 1,
1350 };
1351 
1352 static int da9055_set_bias_level(struct snd_soc_component *component,
1353                                  enum snd_soc_bias_level level)
1354 {
1355         switch (level) {
1356         case SND_SOC_BIAS_ON:
1357         case SND_SOC_BIAS_PREPARE:
1358                 break;
1359         case SND_SOC_BIAS_STANDBY:
1360                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1361                         /* Enable VMID reference & master bias */
1362                         snd_soc_component_update_bits(component, DA9055_REFERENCES,
1363                                             DA9055_VMID_EN | DA9055_BIAS_EN,
1364                                             DA9055_VMID_EN | DA9055_BIAS_EN);
1365                 }
1366                 break;
1367         case SND_SOC_BIAS_OFF:
1368                 /* Disable VMID reference & master bias */
1369                 snd_soc_component_update_bits(component, DA9055_REFERENCES,
1370                                     DA9055_VMID_EN | DA9055_BIAS_EN, 0);
1371                 break;
1372         }
1373         return 0;
1374 }
1375 
1376 static int da9055_probe(struct snd_soc_component *component)
1377 {
1378         struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1379 
1380         /* Enable all Gain Ramps */
1381         snd_soc_component_update_bits(component, DA9055_AUX_L_CTRL,
1382                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1383         snd_soc_component_update_bits(component, DA9055_AUX_R_CTRL,
1384                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1385         snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
1386                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1387         snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
1388                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1389         snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
1390                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1391         snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
1392                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1393         snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1394                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1395         snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1396                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1397         snd_soc_component_update_bits(component, DA9055_HP_L_CTRL,
1398                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1399         snd_soc_component_update_bits(component, DA9055_HP_R_CTRL,
1400                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1401         snd_soc_component_update_bits(component, DA9055_LINE_CTRL,
1402                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1403 
1404         /*
1405          * There are two separate control bits for input and output mixers.
1406          * One to enable corresponding amplifier and other to enable its
1407          * output. As amplifier bits are related to power control, they are
1408          * being managed by DAPM while other (non power related) bits are
1409          * enabled here
1410          */
1411         snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
1412                             DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
1413         snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
1414                             DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
1415 
1416         snd_soc_component_update_bits(component, DA9055_MIXOUT_L_CTRL,
1417                             DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
1418         snd_soc_component_update_bits(component, DA9055_MIXOUT_R_CTRL,
1419                             DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
1420 
1421         /* Set this as per your system configuration */
1422         snd_soc_component_write(component, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
1423 
1424         /* Set platform data values */
1425         if (da9055->pdata) {
1426                 /* set mic bias source */
1427                 if (da9055->pdata->micbias_source) {
1428                         snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
1429                                             DA9055_MICBIAS2_EN,
1430                                             DA9055_MICBIAS2_EN);
1431                 } else {
1432                         snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
1433                                             DA9055_MICBIAS2_EN, 0);
1434                 }
1435                 /* set mic bias voltage */
1436                 switch (da9055->pdata->micbias) {
1437                 case DA9055_MICBIAS_2_2V:
1438                 case DA9055_MICBIAS_2_1V:
1439                 case DA9055_MICBIAS_1_8V:
1440                 case DA9055_MICBIAS_1_6V:
1441                         snd_soc_component_update_bits(component, DA9055_MIC_CONFIG,
1442                                             DA9055_MICBIAS_LEVEL_MASK,
1443                                             (da9055->pdata->micbias) << 4);
1444                         break;
1445                 }
1446         }
1447         return 0;
1448 }
1449 
1450 static const struct snd_soc_component_driver soc_component_dev_da9055 = {
1451         .probe                  = da9055_probe,
1452         .set_bias_level         = da9055_set_bias_level,
1453         .controls               = da9055_snd_controls,
1454         .num_controls           = ARRAY_SIZE(da9055_snd_controls),
1455         .dapm_widgets           = da9055_dapm_widgets,
1456         .num_dapm_widgets       = ARRAY_SIZE(da9055_dapm_widgets),
1457         .dapm_routes            = da9055_audio_map,
1458         .num_dapm_routes        = ARRAY_SIZE(da9055_audio_map),
1459         .idle_bias_on           = 1,
1460         .use_pmdown_time        = 1,
1461         .endianness             = 1,
1462         .non_legacy_dai_naming  = 1,
1463 };
1464 
1465 static const struct regmap_config da9055_regmap_config = {
1466         .reg_bits = 8,
1467         .val_bits = 8,
1468 
1469         .reg_defaults = da9055_reg_defaults,
1470         .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
1471         .volatile_reg = da9055_volatile_register,
1472         .cache_type = REGCACHE_RBTREE,
1473 };
1474 
1475 static int da9055_i2c_probe(struct i2c_client *i2c,
1476                             const struct i2c_device_id *id)
1477 {
1478         struct da9055_priv *da9055;
1479         struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
1480         int ret;
1481 
1482         da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
1483                               GFP_KERNEL);
1484         if (!da9055)
1485                 return -ENOMEM;
1486 
1487         if (pdata)
1488                 da9055->pdata = pdata;
1489 
1490         i2c_set_clientdata(i2c, da9055);
1491 
1492         da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
1493         if (IS_ERR(da9055->regmap)) {
1494                 ret = PTR_ERR(da9055->regmap);
1495                 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1496                 return ret;
1497         }
1498 
1499         ret = devm_snd_soc_register_component(&i2c->dev,
1500                         &soc_component_dev_da9055, &da9055_dai, 1);
1501         if (ret < 0) {
1502                 dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",
1503                         ret);
1504         }
1505         return ret;
1506 }
1507 
1508 /*
1509  * DO NOT change the device Ids. The naming is intentionally specific as both
1510  * the CODEC and PMIC parts of this chip are instantiated separately as I2C
1511  * devices (both have configurable I2C addresses, and are to all intents and
1512  * purposes separate). As a result there are specific DA9055 Ids for CODEC
1513  * and PMIC, which must be different to operate together.
1514  */
1515 static const struct i2c_device_id da9055_i2c_id[] = {
1516         { "da9055-codec", 0 },
1517         { }
1518 };
1519 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
1520 
1521 static const struct of_device_id da9055_of_match[] = {
1522         { .compatible = "dlg,da9055-codec", },
1523         { }
1524 };
1525 MODULE_DEVICE_TABLE(of, da9055_of_match);
1526 
1527 /* I2C codec control layer */
1528 static struct i2c_driver da9055_i2c_driver = {
1529         .driver = {
1530                 .name = "da9055-codec",
1531                 .of_match_table = of_match_ptr(da9055_of_match),
1532         },
1533         .probe          = da9055_i2c_probe,
1534         .id_table       = da9055_i2c_id,
1535 };
1536 
1537 module_i2c_driver(da9055_i2c_driver);
1538 
1539 MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
1540 MODULE_AUTHOR("David Chen, Ashish Chavan");
1541 MODULE_LICENSE("GPL");
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root/sound/soc/codecs/da9055.c

DEFINITIONS
