root/arch/mips/sibyte/sb1250/irq.c

DEFINITIONS

1. sb1250_mask_irq
2. sb1250_unmask_irq
3. sb1250_set_affinity
4. disable_sb1250_irq
5. enable_sb1250_irq
6. ack_sb1250_irq
7. init_sb1250_irqs
8. arch_init_irq
9. dispatch_ip2
10. plat_irq_dispatch

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/init.h>
   7 #include <linux/linkage.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/spinlock.h>
  10 #include <linux/smp.h>
  11 #include <linux/mm.h>
  12 #include <linux/kernel_stat.h>
  13 
  14 #include <asm/errno.h>
  15 #include <asm/signal.h>
  16 #include <asm/time.h>
  17 #include <asm/io.h>
  18 
  19 #include <asm/sibyte/sb1250_regs.h>
  20 #include <asm/sibyte/sb1250_int.h>
  21 #include <asm/sibyte/sb1250_uart.h>
  22 #include <asm/sibyte/sb1250_scd.h>
  23 #include <asm/sibyte/sb1250.h>
  24 
  25 /*
  26  * These are the routines that handle all the low level interrupt stuff.
  27  * Actions handled here are: initialization of the interrupt map, requesting of
  28  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  29  * for interrupt lines
  30  */
  31 
  32 #ifdef CONFIG_SIBYTE_HAS_LDT
  33 extern unsigned long ldt_eoi_space;
  34 #endif
  35 
  36 /* Store the CPU id (not the logical number) */
  37 int sb1250_irq_owner[SB1250_NR_IRQS];
  38 
  39 static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
  40 
  41 void sb1250_mask_irq(int cpu, int irq)
  42 {
  43         unsigned long flags;
  44         u64 cur_ints;
  45 
  46         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
  47         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  48                                         R_IMR_INTERRUPT_MASK));
  49         cur_ints |= (((u64) 1) << irq);
  50         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  51                                         R_IMR_INTERRUPT_MASK));
  52         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  53 }
  54 
  55 void sb1250_unmask_irq(int cpu, int irq)
  56 {
  57         unsigned long flags;
  58         u64 cur_ints;
  59 
  60         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
  61         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  62                                         R_IMR_INTERRUPT_MASK));
  63         cur_ints &= ~(((u64) 1) << irq);
  64         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  65                                         R_IMR_INTERRUPT_MASK));
  66         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  67 }
  68 
  69 #ifdef CONFIG_SMP
  70 static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
  71                                bool force)
  72 {
  73         int i = 0, old_cpu, cpu, int_on;
  74         unsigned int irq = d->irq;
  75         u64 cur_ints;
  76         unsigned long flags;
  77 
  78         i = cpumask_first_and(mask, cpu_online_mask);
  79 
  80         /* Convert logical CPU to physical CPU */
  81         cpu = cpu_logical_map(i);
  82 
  83         /* Protect against other affinity changers and IMR manipulation */
  84         raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
  85 
  86         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
  87         old_cpu = sb1250_irq_owner[irq];
  88         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
  89                                         R_IMR_INTERRUPT_MASK));
  90         int_on = !(cur_ints & (((u64) 1) << irq));
  91         if (int_on) {
  92                 /* If it was on, mask it */
  93                 cur_ints |= (((u64) 1) << irq);
  94                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
  95                                         R_IMR_INTERRUPT_MASK));
  96         }
  97         sb1250_irq_owner[irq] = cpu;
  98         if (int_on) {
  99                 /* unmask for the new CPU */
 100                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 101                                         R_IMR_INTERRUPT_MASK));
 102                 cur_ints &= ~(((u64) 1) << irq);
 103                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 104                                         R_IMR_INTERRUPT_MASK));
 105         }
 106         raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 107 
 108         return 0;
 109 }
 110 #endif
 111 
 112 static void disable_sb1250_irq(struct irq_data *d)
 113 {
 114         unsigned int irq = d->irq;
 115 
 116         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 117 }
 118 
 119 static void enable_sb1250_irq(struct irq_data *d)
 120 {
 121         unsigned int irq = d->irq;
 122 
 123         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 124 }
 125 
 126 
 127 static void ack_sb1250_irq(struct irq_data *d)
 128 {
 129         unsigned int irq = d->irq;
 130 #ifdef CONFIG_SIBYTE_HAS_LDT
 131         u64 pending;
 132 
 133         /*
 134          * If the interrupt was an HT interrupt, now is the time to
 135          * clear it.  NOTE: we assume the HT bridge was set up to
 136          * deliver the interrupts to all CPUs (which makes affinity
 137          * changing easier for us)
 138          */
 139         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 140                                                     R_IMR_LDT_INTERRUPT)));
 141         pending &= ((u64)1 << (irq));
 142         if (pending) {
 143                 int i;
 144                 for (i=0; i<NR_CPUS; i++) {
 145                         int cpu;
 146 #ifdef CONFIG_SMP
 147                         cpu = cpu_logical_map(i);
 148 #else
 149                         cpu = i;
 150 #endif
 151                         /*
 152                          * Clear for all CPUs so an affinity switch
 153                          * doesn't find an old status
 154                          */
 155                         __raw_writeq(pending,
 156                                      IOADDR(A_IMR_REGISTER(cpu,
 157                                                 R_IMR_LDT_INTERRUPT_CLR)));
 158                 }
 159 
 160                 /*
 161                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 162                  * Pass 2, the LDT world may be edge-triggered, but
 163                  * this EOI shouldn't hurt.  If they are
 164                  * level-sensitive, the EOI is required.
 165                  */
 166                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 167         }
 168 #endif
 169         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 170 }
 171 
 172 static struct irq_chip sb1250_irq_type = {
 173         .name = "SB1250-IMR",
 174         .irq_mask_ack = ack_sb1250_irq,
 175         .irq_unmask = enable_sb1250_irq,
 176         .irq_mask = disable_sb1250_irq,
 177 #ifdef CONFIG_SMP
 178         .irq_set_affinity = sb1250_set_affinity
 179 #endif
 180 };
 181 
 182 void __init init_sb1250_irqs(void)
 183 {
 184         int i;
 185 
 186         for (i = 0; i < SB1250_NR_IRQS; i++) {
 187                 irq_set_chip_and_handler(i, &sb1250_irq_type,
 188                                          handle_level_irq);
 189                 sb1250_irq_owner[i] = 0;
 190         }
 191 }
 192 
 193 
 194 /*
 195  *  arch_init_irq is called early in the boot sequence from init/main.c via
 196  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 197  *  installing the handler that will be responsible for dispatching interrupts
 198  *  to the "right" place.
 199  */
 200 /*
 201  * For now, map all interrupts to IP[2].  We could save
 202  * some cycles by parceling out system interrupts to different
 203  * IP lines, but keep it simple for bringup.  We'll also direct
 204  * all interrupts to a single CPU; we should probably route
 205  * PCI and LDT to one cpu and everything else to the other
 206  * to balance the load a bit.
 207  *
 208  * On the second cpu, everything is set to IP5, which is
 209  * ignored, EXCEPT the mailbox interrupt.  That one is
 210  * set to IP[2] so it is handled.  This is needed so we
 211  * can do cross-cpu function calls, as required by SMP
 212  */
 213 
 214 #define IMR_IP2_VAL     K_INT_MAP_I0
 215 #define IMR_IP3_VAL     K_INT_MAP_I1
 216 #define IMR_IP4_VAL     K_INT_MAP_I2
 217 #define IMR_IP5_VAL     K_INT_MAP_I3
 218 #define IMR_IP6_VAL     K_INT_MAP_I4
 219 
 220 void __init arch_init_irq(void)
 221 {
 222 
 223         unsigned int i;
 224         u64 tmp;
 225         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 226                 STATUSF_IP1 | STATUSF_IP0;
 227 
 228         /* Default everything to IP2 */
 229         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 230                 __raw_writeq(IMR_IP2_VAL,
 231                              IOADDR(A_IMR_REGISTER(0,
 232                                                    R_IMR_INTERRUPT_MAP_BASE) +
 233                                     (i << 3)));
 234                 __raw_writeq(IMR_IP2_VAL,
 235                              IOADDR(A_IMR_REGISTER(1,
 236                                                    R_IMR_INTERRUPT_MAP_BASE) +
 237                                     (i << 3)));
 238         }
 239 
 240         init_sb1250_irqs();
 241 
 242         /*
 243          * Map the high 16 bits of the mailbox registers to IP[3], for
 244          * inter-cpu messages
 245          */
 246         /* Was I1 */
 247         __raw_writeq(IMR_IP3_VAL,
 248                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 249                             (K_INT_MBOX_0 << 3)));
 250         __raw_writeq(IMR_IP3_VAL,
 251                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 252                             (K_INT_MBOX_0 << 3)));
 253 
 254         /* Clear the mailboxes.  The firmware may leave them dirty */
 255         __raw_writeq(0xffffffffffffffffULL,
 256                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 257         __raw_writeq(0xffffffffffffffffULL,
 258                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 259 
 260         /* Mask everything except the mailbox registers for both cpus */
 261         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 262         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 263         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 264 
 265         /*
 266          * Note that the timer interrupts are also mapped, but this is
 267          * done in sb1250_time_init().  Also, the profiling driver
 268          * does its own management of IP7.
 269          */
 270 
 271         /* Enable necessary IPs, disable the rest */
 272         change_c0_status(ST0_IM, imask);
 273 }
 274 
 275 extern void sb1250_mailbox_interrupt(void);
 276 
 277 static inline void dispatch_ip2(void)
 278 {
 279         unsigned int cpu = smp_processor_id();
 280         unsigned long long mask;
 281 
 282         /*
 283          * Default...we've hit an IP[2] interrupt, which means we've got to
 284          * check the 1250 interrupt registers to figure out what to do.  Need
 285          * to detect which CPU we're on, now that smp_affinity is supported.
 286          */
 287         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
 288                                   R_IMR_INTERRUPT_STATUS_BASE)));
 289         if (mask)
 290                 do_IRQ(fls64(mask) - 1);
 291 }
 292 
 293 asmlinkage void plat_irq_dispatch(void)
 294 {
 295         unsigned int cpu = smp_processor_id();
 296         unsigned int pending;
 297 
 298         /*
 299          * What a pain. We have to be really careful saving the upper 32 bits
 300          * of any * register across function calls if we don't want them
 301          * trashed--since were running in -o32, the calling routing never saves
 302          * the full 64 bits of a register across a function call.  Being the
 303          * interrupt handler, we're guaranteed that interrupts are disabled
 304          * during this code so we don't have to worry about random interrupts
 305          * blasting the high 32 bits.
 306          */
 307 
 308         pending = read_c0_cause() & read_c0_status() & ST0_IM;
 309 
 310         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
 311                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 312         else if (pending & CAUSEF_IP4)
 313                 do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 314 
 315 #ifdef CONFIG_SMP
 316         else if (pending & CAUSEF_IP3)
 317                 sb1250_mailbox_interrupt();
 318 #endif
 319 
 320         else if (pending & CAUSEF_IP2)
 321                 dispatch_ip2();
 322         else
 323                 spurious_interrupt();
 324 }