arch/mips/pci/pci-xtalk-bridge.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
ioc3_cfg_rd
ioc3_cfg_wr
bridge_disable_swapping
pci_conf0_read_config
pci_conf1_read_config
pci_read_config
pci_conf0_write_config
pci_conf1_write_config
pci_write_config
bridge_set_affinity
bridge_domain_alloc
bridge_domain_free
bridge_domain_activate
bridge_domain_deactivate
bridge_map_irq
bridge_probe
bridge_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
   4  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
   5  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/export.h>
   9 #include <linux/pci.h>
  10 #include <linux/smp.h>
  11 #include <linux/dma-direct.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/platform_data/xtalk-bridge.h>
  14 
  15 #include <asm/pci/bridge.h>
  16 #include <asm/paccess.h>
  17 #include <asm/sn/irq_alloc.h>
  18 
  19 /*
  20  * Most of the IOC3 PCI config register aren't present
  21  * we emulate what is needed for a normal PCI enumeration
  22  */
  23 static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value)
  24 {
  25         u32 cf, shift, mask;
  26 
  27         switch (where & ~3) {
  28         case 0x00 ... 0x10:
  29         case 0x40 ... 0x44:
  30                 if (get_dbe(cf, (u32 *)addr))
  31                         return PCIBIOS_DEVICE_NOT_FOUND;
  32                 break;
  33         case 0x3c:
  34                 /* emulate sane interrupt pin value */
  35                 cf = 0x00000100;
  36                 break;
  37         default:
  38                 cf = 0;
  39                 break;
  40         }
  41         shift = (where & 3) << 3;
  42         mask = 0xffffffffU >> ((4 - size) << 3);
  43         *value = (cf >> shift) & mask;
  44 
  45         return PCIBIOS_SUCCESSFUL;
  46 }
  47 
  48 static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
  49 {
  50         u32 cf, shift, mask, smask;
  51 
  52         if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
  53                 return PCIBIOS_SUCCESSFUL;
  54 
  55         if (get_dbe(cf, (u32 *)addr))
  56                 return PCIBIOS_DEVICE_NOT_FOUND;
  57 
  58         shift = ((where & 3) << 3);
  59         mask = (0xffffffffU >> ((4 - size) << 3));
  60         smask = mask << shift;
  61 
  62         cf = (cf & ~smask) | ((value & mask) << shift);
  63         if (put_dbe(cf, (u32 *)addr))
  64                 return PCIBIOS_DEVICE_NOT_FOUND;
  65 
  66         return PCIBIOS_SUCCESSFUL;
  67 }
  68 
  69 static void bridge_disable_swapping(struct pci_dev *dev)
  70 {
  71         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
  72         int slot = PCI_SLOT(dev->devfn);
  73 
  74         /* Turn off byte swapping */
  75         bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
  76         bridge_read(bc, b_widget.w_tflush);     /* Flush */
  77 }
  78 
  79 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
  80         bridge_disable_swapping);
  81 
  82 
  83 /*
  84  * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
  85  * not really documented, so right now I can't write code which uses it.
  86  * Therefore we use type 0 accesses for now even though they won't work
  87  * correctly for PCI-to-PCI bridges.
  88  *
  89  * The function is complicated by the ultimate brokenness of the IOC3 chip
  90  * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
  91  * accesses and does only decode parts of it's address space.
  92  */
  93 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
  94                                  int where, int size, u32 *value)
  95 {
  96         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
  97         struct bridge_regs *bridge = bc->base;
  98         int slot = PCI_SLOT(devfn);
  99         int fn = PCI_FUNC(devfn);
 100         void *addr;
 101         u32 cf;
 102         int res;
 103 
 104         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
 105         if (get_dbe(cf, (u32 *)addr))
 106                 return PCIBIOS_DEVICE_NOT_FOUND;
 107 
 108         /*
 109          * IOC3 is broken beyond belief ...  Don't even give the
 110          * generic PCI code a chance to look at it for real ...
 111          */
 112         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
 113                 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 114                 return ioc3_cfg_rd(addr, where, size, value);
 115         }
 116 
 117         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
 118 
 119         if (size == 1)
 120                 res = get_dbe(*value, (u8 *)addr);
 121         else if (size == 2)
 122                 res = get_dbe(*value, (u16 *)addr);
 123         else
 124                 res = get_dbe(*value, (u32 *)addr);
 125 
 126         return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 127 }
 128 
 129 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
 130                                  int where, int size, u32 *value)
 131 {
 132         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 133         struct bridge_regs *bridge = bc->base;
 134         int busno = bus->number;
 135         int slot = PCI_SLOT(devfn);
 136         int fn = PCI_FUNC(devfn);
 137         void *addr;
 138         u32 cf;
 139         int res;
 140 
 141         bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
 142         addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
 143         if (get_dbe(cf, (u32 *)addr))
 144                 return PCIBIOS_DEVICE_NOT_FOUND;
 145 
 146         /*
 147          * IOC3 is broken beyond belief ...  Don't even give the
 148          * generic PCI code a chance to look at it for real ...
 149          */
 150         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
 151                 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
 152                 return ioc3_cfg_rd(addr, where, size, value);
 153         }
 154 
 155         addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
 156 
 157         if (size == 1)
 158                 res = get_dbe(*value, (u8 *)addr);
 159         else if (size == 2)
 160                 res = get_dbe(*value, (u16 *)addr);
 161         else
 162                 res = get_dbe(*value, (u32 *)addr);
 163 
 164         return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 165 }
 166 
 167 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
 168                            int where, int size, u32 *value)
 169 {
 170         if (!pci_is_root_bus(bus))
 171                 return pci_conf1_read_config(bus, devfn, where, size, value);
 172 
 173         return pci_conf0_read_config(bus, devfn, where, size, value);
 174 }
 175 
 176 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
 177                                   int where, int size, u32 value)
 178 {
 179         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 180         struct bridge_regs *bridge = bc->base;
 181         int slot = PCI_SLOT(devfn);
 182         int fn = PCI_FUNC(devfn);
 183         void *addr;
 184         u32 cf;
 185         int res;
 186 
 187         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
 188         if (get_dbe(cf, (u32 *)addr))
 189                 return PCIBIOS_DEVICE_NOT_FOUND;
 190 
 191         /*
 192          * IOC3 is broken beyond belief ...  Don't even give the
 193          * generic PCI code a chance to look at it for real ...
 194          */
 195         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
 196                 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 197                 return ioc3_cfg_wr(addr, where, size, value);
 198         }
 199 
 200         addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
 201 
 202         if (size == 1)
 203                 res = put_dbe(value, (u8 *)addr);
 204         else if (size == 2)
 205                 res = put_dbe(value, (u16 *)addr);
 206         else
 207                 res = put_dbe(value, (u32 *)addr);
 208 
 209         if (res)
 210                 return PCIBIOS_DEVICE_NOT_FOUND;
 211 
 212         return PCIBIOS_SUCCESSFUL;
 213 }
 214 
 215 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
 216                                   int where, int size, u32 value)
 217 {
 218         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 219         struct bridge_regs *bridge = bc->base;
 220         int slot = PCI_SLOT(devfn);
 221         int fn = PCI_FUNC(devfn);
 222         int busno = bus->number;
 223         void *addr;
 224         u32 cf;
 225         int res;
 226 
 227         bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
 228         addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
 229         if (get_dbe(cf, (u32 *)addr))
 230                 return PCIBIOS_DEVICE_NOT_FOUND;
 231 
 232         /*
 233          * IOC3 is broken beyond belief ...  Don't even give the
 234          * generic PCI code a chance to look at it for real ...
 235          */
 236         if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
 237                 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
 238                 return ioc3_cfg_wr(addr, where, size, value);
 239         }
 240 
 241         addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
 242 
 243         if (size == 1)
 244                 res = put_dbe(value, (u8 *)addr);
 245         else if (size == 2)
 246                 res = put_dbe(value, (u16 *)addr);
 247         else
 248                 res = put_dbe(value, (u32 *)addr);
 249 
 250         if (res)
 251                 return PCIBIOS_DEVICE_NOT_FOUND;
 252 
 253         return PCIBIOS_SUCCESSFUL;
 254 }
 255 
 256 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
 257         int where, int size, u32 value)
 258 {
 259         if (!pci_is_root_bus(bus))
 260                 return pci_conf1_write_config(bus, devfn, where, size, value);
 261 
 262         return pci_conf0_write_config(bus, devfn, where, size, value);
 263 }
 264 
 265 static struct pci_ops bridge_pci_ops = {
 266         .read    = pci_read_config,
 267         .write   = pci_write_config,
 268 };
 269 
 270 struct bridge_irq_chip_data {
 271         struct bridge_controller *bc;
 272         nasid_t nasid;
 273 };
 274 
 275 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
 276                                bool force)
 277 {
 278 #ifdef CONFIG_NUMA
 279         struct bridge_irq_chip_data *data = d->chip_data;
 280         int bit = d->parent_data->hwirq;
 281         int pin = d->hwirq;
 282         int ret, cpu;
 283 
 284         ret = irq_chip_set_affinity_parent(d, mask, force);
 285         if (ret >= 0) {
 286                 cpu = cpumask_first_and(mask, cpu_online_mask);
 287                 data->nnasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
 288                 bridge_write(data->bc, b_int_addr[pin].addr,
 289                              (((data->bc->intr_addr >> 30) & 0x30000) |
 290                               bit | (data->nasid << 8)));
 291                 bridge_read(data->bc, b_wid_tflush);
 292         }
 293         return ret;
 294 #else
 295         return irq_chip_set_affinity_parent(d, mask, force);
 296 #endif
 297 }
 298 
 299 struct irq_chip bridge_irq_chip = {
 300         .name             = "BRIDGE",
 301         .irq_mask         = irq_chip_mask_parent,
 302         .irq_unmask       = irq_chip_unmask_parent,
 303         .irq_set_affinity = bridge_set_affinity
 304 };
 305 
 306 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
 307                                unsigned int nr_irqs, void *arg)
 308 {
 309         struct bridge_irq_chip_data *data;
 310         struct irq_alloc_info *info = arg;
 311         int ret;
 312 
 313         if (nr_irqs > 1 || !info)
 314                 return -EINVAL;
 315 
 316         data = kzalloc(sizeof(*data), GFP_KERNEL);
 317         if (!data)
 318                 return -ENOMEM;
 319 
 320         ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
 321         if (ret >= 0) {
 322                 data->bc = info->ctrl;
 323                 data->nasid = info->nasid;
 324                 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
 325                                     data, handle_level_irq, NULL, NULL);
 326         } else {
 327                 kfree(data);
 328         }
 329 
 330         return ret;
 331 }
 332 
 333 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
 334                                unsigned int nr_irqs)
 335 {
 336         struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
 337 
 338         if (nr_irqs)
 339                 return;
 340 
 341         kfree(irqd->chip_data);
 342         irq_domain_free_irqs_top(domain, virq, nr_irqs);
 343 }
 344 
 345 static int bridge_domain_activate(struct irq_domain *domain,
 346                                   struct irq_data *irqd, bool reserve)
 347 {
 348         struct bridge_irq_chip_data *data = irqd->chip_data;
 349         struct bridge_controller *bc = data->bc;
 350         int bit = irqd->parent_data->hwirq;
 351         int pin = irqd->hwirq;
 352         u32 device;
 353 
 354         bridge_write(bc, b_int_addr[pin].addr,
 355                      (((bc->intr_addr >> 30) & 0x30000) |
 356                       bit | (data->nasid << 8)));
 357         bridge_set(bc, b_int_enable, (1 << pin));
 358         bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
 359 
 360         /*
 361          * Enable sending of an interrupt clear packt to the hub on a high to
 362          * low transition of the interrupt pin.
 363          *
 364          * IRIX sets additional bits in the address which are documented as
 365          * reserved in the bridge docs.
 366          */
 367         bridge_set(bc, b_int_mode, (1UL << pin));
 368 
 369         /*
 370          * We assume the bridge to have a 1:1 mapping between devices
 371          * (slots) and intr pins.
 372          */
 373         device = bridge_read(bc, b_int_device);
 374         device &= ~(7 << (pin*3));
 375         device |= (pin << (pin*3));
 376         bridge_write(bc, b_int_device, device);
 377 
 378         bridge_read(bc, b_wid_tflush);
 379         return 0;
 380 }
 381 
 382 static void bridge_domain_deactivate(struct irq_domain *domain,
 383                                      struct irq_data *irqd)
 384 {
 385         struct bridge_irq_chip_data *data = irqd->chip_data;
 386 
 387         bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
 388         bridge_read(data->bc, b_wid_tflush);
 389 }
 390 
 391 static const struct irq_domain_ops bridge_domain_ops = {
 392         .alloc      = bridge_domain_alloc,
 393         .free       = bridge_domain_free,
 394         .activate   = bridge_domain_activate,
 395         .deactivate = bridge_domain_deactivate
 396 };
 397 
 398 /*
 399  * All observed requests have pin == 1. We could have a global here, that
 400  * gets incremented and returned every time - unfortunately, pci_map_irq
 401  * may be called on the same device over and over, and need to return the
 402  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
 403  *
 404  * A given PCI device, in general, should be able to intr any of the cpus
 405  * on any one of the hubs connected to its xbow.
 406  */
 407 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 408 {
 409         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 410         struct irq_alloc_info info;
 411         int irq;
 412 
 413         irq = bc->pci_int[slot];
 414         if (irq == -1) {
 415                 info.ctrl = bc;
 416                 info.nasid = bc->nasid;
 417                 info.pin = slot;
 418 
 419                 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
 420                 if (irq < 0)
 421                         return irq;
 422 
 423                 bc->pci_int[slot] = irq;
 424         }
 425         return irq;
 426 }
 427 
 428 static int bridge_probe(struct platform_device *pdev)
 429 {
 430         struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
 431         struct device *dev = &pdev->dev;
 432         struct bridge_controller *bc;
 433         struct pci_host_bridge *host;
 434         struct irq_domain *domain, *parent;
 435         struct fwnode_handle *fn;
 436         int slot;
 437         int err;
 438 
 439         parent = irq_get_default_host();
 440         if (!parent)
 441                 return -ENODEV;
 442         fn = irq_domain_alloc_named_fwnode("BRIDGE");
 443         if (!fn)
 444                 return -ENOMEM;
 445         domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
 446                                              &bridge_domain_ops, NULL);
 447         irq_domain_free_fwnode(fn);
 448         if (!domain)
 449                 return -ENOMEM;
 450 
 451         pci_set_flags(PCI_PROBE_ONLY);
 452 
 453         host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
 454         if (!host) {
 455                 err = -ENOMEM;
 456                 goto err_remove_domain;
 457         }
 458 
 459         bc = pci_host_bridge_priv(host);
 460 
 461         bc->busn.name           = "Bridge PCI busn";
 462         bc->busn.start          = 0;
 463         bc->busn.end            = 0xff;
 464         bc->busn.flags          = IORESOURCE_BUS;
 465 
 466         bc->domain              = domain;
 467 
 468         pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
 469         pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
 470         pci_add_resource(&host->windows, &bc->busn);
 471 
 472         err = devm_request_pci_bus_resources(dev, &host->windows);
 473         if (err < 0)
 474                 goto err_free_resource;
 475 
 476         bc->nasid = bd->nasid;
 477 
 478         bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
 479         bc->base = (struct bridge_regs *)bd->bridge_addr;
 480         bc->intr_addr = bd->intr_addr;
 481 
 482         /*
 483          * Clear all pending interrupts.
 484          */
 485         bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
 486 
 487         /*
 488          * Until otherwise set up, assume all interrupts are from slot 0
 489          */
 490         bridge_write(bc, b_int_device, 0x0);
 491 
 492         /*
 493          * disable swapping for big windows
 494          */
 495         bridge_clr(bc, b_wid_control,
 496                    BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
 497 #ifdef CONFIG_PAGE_SIZE_4KB
 498         bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
 499 #else /* 16kB or larger */
 500         bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
 501 #endif
 502 
 503         /*
 504          * Hmm...  IRIX sets additional bits in the address which
 505          * are documented as reserved in the bridge docs.
 506          */
 507         bridge_write(bc, b_wid_int_upper,
 508                      ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
 509         bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
 510         bridge_write(bc, b_dir_map, (bd->masterwid << 20));     /* DMA */
 511         bridge_write(bc, b_int_enable, 0);
 512 
 513         for (slot = 0; slot < 8; slot++) {
 514                 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
 515                 bc->pci_int[slot] = -1;
 516         }
 517         bridge_read(bc, b_wid_tflush);    /* wait until Bridge PIO complete */
 518 
 519         host->dev.parent = dev;
 520         host->sysdata = bc;
 521         host->busnr = 0;
 522         host->ops = &bridge_pci_ops;
 523         host->map_irq = bridge_map_irq;
 524         host->swizzle_irq = pci_common_swizzle;
 525 
 526         err = pci_scan_root_bus_bridge(host);
 527         if (err < 0)
 528                 goto err_free_resource;
 529 
 530         pci_bus_claim_resources(host->bus);
 531         pci_bus_add_devices(host->bus);
 532 
 533         platform_set_drvdata(pdev, host->bus);
 534 
 535         return 0;
 536 
 537 err_free_resource:
 538         pci_free_resource_list(&host->windows);
 539 err_remove_domain:
 540         irq_domain_remove(domain);
 541         return err;
 542 }
 543 
 544 static int bridge_remove(struct platform_device *pdev)
 545 {
 546         struct pci_bus *bus = platform_get_drvdata(pdev);
 547         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 548 
 549         irq_domain_remove(bc->domain);
 550         pci_lock_rescan_remove();
 551         pci_stop_root_bus(bus);
 552         pci_remove_root_bus(bus);
 553         pci_unlock_rescan_remove();
 554 
 555         return 0;
 556 }
 557 
 558 static struct platform_driver bridge_driver = {
 559         .probe  = bridge_probe,
 560         .remove = bridge_remove,
 561         .driver = {
 562                 .name = "xtalk-bridge",
 563         }
 564 };
 565 
 566 builtin_platform_driver(bridge_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/arch/mips/pci/pci-xtalk-bridge.c

DEFINITIONS
