root/arch/sparc/include/asm/obio.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. bw_get_intr_mask
  2. bw_clear_intr_mask
  3. bw_get_prof_limit
  4. bw_set_prof_limit
  5. bw_get_ctrl
  6. bw_set_ctrl
  7. cc_get_ipen
  8. cc_set_iclr
  9. cc_get_imsk
  10. cc_set_imsk
  11. cc_get_imsk_other
  12. cc_set_imsk_other
  13. cc_set_igen
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * obio.h:  Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
   4  *
   5  * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
   6  */
   7 
   8 #ifndef _SPARC_OBIO_H
   9 #define _SPARC_OBIO_H
  10 
  11 #include <asm/asi.h>
  12 
  13 /* This weird monster likes to use the very upper parts of
  14    36bit PA for these things :) */
  15    
  16 /* CSR space (for each XDBUS)
  17  *  ------------------------------------------------------------------------
  18  *  |   0xFE  |   DEVID    |                | XDBUS ID |                   |
  19  *  ------------------------------------------------------------------------
  20  *  35      28 27        20 19            10 9        8 7                 0
  21  */
  22    
  23 #define CSR_BASE_ADDR           0xe0000000
  24 #define CSR_CPU_SHIFT           (32 - 4 - 5)
  25 #define CSR_XDBUS_SHIFT         8
  26 
  27 #define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
  28 
  29 /* ECSR space (not for each XDBUS)
  30  *  ------------------------------------------------------------------------
  31  *  |   0xF  | DEVID[7:1] |                                                |
  32  *  ------------------------------------------------------------------------
  33  *  35     32 31        25 24                                             0
  34  */
  35    
  36 #define ECSR_BASE_ADDR          0x00000000
  37 #define ECSR_CPU_SHIFT          (32 - 5)
  38 #define ECSR_DEV_SHIFT          (32 - 8)
  39 
  40 #define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
  41 #define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT) 
  42 
  43 /* Bus Watcher */
  44 #define BW_LOCAL_BASE           0xfff00000
  45 
  46 #define BW_CID                  0x00000000
  47 #define BW_DBUS_CTRL            0x00000008
  48 #define BW_DBUS_DATA            0x00000010
  49 #define BW_CTRL                 0x00001000
  50 #define BW_INTR_TABLE           0x00001040
  51 #define BW_INTR_TABLE_CLEAR     0x00001080
  52 #define BW_PRESCALER            0x000010c0
  53 #define BW_PTIMER_LIMIT         0x00002000
  54 #define BW_PTIMER_COUNTER2      0x00002004
  55 #define BW_PTIMER_NDLIMIT       0x00002008
  56 #define BW_PTIMER_CTRL          0x0000200c
  57 #define BW_PTIMER_COUNTER       0x00002010
  58 #define BW_TIMER_LIMIT          0x00003000
  59 #define BW_TIMER_COUNTER2       0x00003004
  60 #define BW_TIMER_NDLIMIT        0x00003008
  61 #define BW_TIMER_CTRL           0x0000300c
  62 #define BW_TIMER_COUNTER        0x00003010
  63 
  64 /* BW Control */
  65 #define BW_CTRL_USER_TIMER      0x00000004      /* Is User Timer Free run enabled */
  66 
  67 /* Boot Bus */
  68 #define BB_LOCAL_BASE           0xf0000000
  69 
  70 #define BB_STAT1                0x00100000
  71 #define BB_STAT2                0x00120000
  72 #define BB_STAT3                0x00140000
  73 #define BB_LEDS                 0x002e0000
  74 
  75 /* Bits in BB_STAT2 */
  76 #define BB_STAT2_AC_INTR        0x04    /* Aiee! 5ms and power is gone... */
  77 #define BB_STAT2_TMP_INTR       0x10    /* My Penguins are burning. Are you able to smell it? */
  78 #define BB_STAT2_FAN_INTR       0x20    /* My fan refuses to work */
  79 #define BB_STAT2_PWR_INTR       0x40    /* On SC2000, one of the two ACs died. Ok, we go on... */
  80 #define BB_STAT2_MASK           (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
  81 
  82 /* Cache Controller */
  83 #define CC_BASE         0x1F00000
  84 #define CC_DATSTREAM    0x1F00000  /* Data stream register */
  85 #define CC_DATSIZE      0x1F0003F  /* Size */
  86 #define CC_SRCSTREAM    0x1F00100  /* Source stream register */
  87 #define CC_DESSTREAM    0x1F00200  /* Destination stream register */
  88 #define CC_RMCOUNT      0x1F00300  /* Count of references and misses */
  89 #define CC_IPEN         0x1F00406  /* Pending Interrupts */
  90 #define CC_IMSK         0x1F00506  /* Interrupt Mask */
  91 #define CC_ICLR         0x1F00606  /* Clear pending Interrupts */
  92 #define CC_IGEN         0x1F00704  /* Generate Interrupt register */
  93 #define CC_STEST        0x1F00804  /* Internal self-test */
  94 #define CC_CREG         0x1F00A04  /* Control register */
  95 #define CC_SREG         0x1F00B00  /* Status register */
  96 #define CC_RREG         0x1F00C04  /* Reset register */
  97 #define CC_EREG         0x1F00E00  /* Error code register */
  98 #define CC_CID          0x1F00F04  /* Component ID */
  99 
 100 #ifndef __ASSEMBLY__
 101 
 102 static inline int bw_get_intr_mask(int sbus_level)
 103 {
 104         int mask;
 105         
 106         __asm__ __volatile__ ("lduha [%1] %2, %0" :
 107                               "=r" (mask) :
 108                               "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
 109                               "i" (ASI_M_CTL));
 110         return mask;
 111 }
 112 
 113 static inline void bw_clear_intr_mask(int sbus_level, int mask)
 114 {
 115         __asm__ __volatile__ ("stha %0, [%1] %2" : :
 116                               "r" (mask),
 117                               "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
 118                               "i" (ASI_M_CTL));
 119 }
 120 
 121 static inline unsigned int bw_get_prof_limit(int cpu)
 122 {
 123         unsigned int limit;
 124         
 125         __asm__ __volatile__ ("lda [%1] %2, %0" :
 126                               "=r" (limit) :
 127                               "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
 128                               "i" (ASI_M_CTL));
 129         return limit;
 130 }
 131 
 132 static inline void bw_set_prof_limit(int cpu, unsigned int limit)
 133 {
 134         __asm__ __volatile__ ("sta %0, [%1] %2" : :
 135                               "r" (limit),
 136                               "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
 137                               "i" (ASI_M_CTL));
 138 }
 139 
 140 static inline unsigned int bw_get_ctrl(int cpu)
 141 {
 142         unsigned int ctrl;
 143         
 144         __asm__ __volatile__ ("lda [%1] %2, %0" :
 145                               "=r" (ctrl) :
 146                               "r" (CSR_BASE(cpu) + BW_CTRL),
 147                               "i" (ASI_M_CTL));
 148         return ctrl;
 149 }
 150 
 151 static inline void bw_set_ctrl(int cpu, unsigned int ctrl)
 152 {
 153         __asm__ __volatile__ ("sta %0, [%1] %2" : :
 154                               "r" (ctrl),
 155                               "r" (CSR_BASE(cpu) + BW_CTRL),
 156                               "i" (ASI_M_CTL));
 157 }
 158 
 159 static inline unsigned int cc_get_ipen(void)
 160 {
 161         unsigned int pending;
 162         
 163         __asm__ __volatile__ ("lduha [%1] %2, %0" :
 164                               "=r" (pending) :
 165                               "r" (CC_IPEN),
 166                               "i" (ASI_M_MXCC));
 167         return pending;
 168 }
 169 
 170 static inline void cc_set_iclr(unsigned int clear)
 171 {
 172         __asm__ __volatile__ ("stha %0, [%1] %2" : :
 173                               "r" (clear),
 174                               "r" (CC_ICLR),
 175                               "i" (ASI_M_MXCC));
 176 }
 177 
 178 static inline unsigned int cc_get_imsk(void)
 179 {
 180         unsigned int mask;
 181         
 182         __asm__ __volatile__ ("lduha [%1] %2, %0" :
 183                               "=r" (mask) :
 184                               "r" (CC_IMSK),
 185                               "i" (ASI_M_MXCC));
 186         return mask;
 187 }
 188 
 189 static inline void cc_set_imsk(unsigned int mask)
 190 {
 191         __asm__ __volatile__ ("stha %0, [%1] %2" : :
 192                               "r" (mask),
 193                               "r" (CC_IMSK),
 194                               "i" (ASI_M_MXCC));
 195 }
 196 
 197 static inline unsigned int cc_get_imsk_other(int cpuid)
 198 {
 199         unsigned int mask;
 200         
 201         __asm__ __volatile__ ("lduha [%1] %2, %0" :
 202                               "=r" (mask) :
 203                               "r" (ECSR_BASE(cpuid) | CC_IMSK),
 204                               "i" (ASI_M_CTL));
 205         return mask;
 206 }
 207 
 208 static inline void cc_set_imsk_other(int cpuid, unsigned int mask)
 209 {
 210         __asm__ __volatile__ ("stha %0, [%1] %2" : :
 211                               "r" (mask),
 212                               "r" (ECSR_BASE(cpuid) | CC_IMSK),
 213                               "i" (ASI_M_CTL));
 214 }
 215 
 216 static inline void cc_set_igen(unsigned int gen)
 217 {
 218         __asm__ __volatile__ ("sta %0, [%1] %2" : :
 219                               "r" (gen),
 220                               "r" (CC_IGEN),
 221                               "i" (ASI_M_MXCC));
 222 }
 223 
 224 #endif /* !__ASSEMBLY__ */
 225 
 226 #endif /* !(_SPARC_OBIO_H) */
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