1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * sbi.h: SBI (Sbus Interface on sun4d) definitions
4 *
5 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
6 */
7
8 #ifndef _SPARC_SBI_H
9 #define _SPARC_SBI_H
10
11 #include <asm/obio.h>
12
13 /* SBI */
14 struct sbi_regs {
15 /* 0x0000 */ u32 cid; /* Component ID */
16 /* 0x0004 */ u32 ctl; /* Control */
17 /* 0x0008 */ u32 status; /* Status */
18 u32 _unused1;
19
20 /* 0x0010 */ u32 cfg0; /* Slot0 config reg */
21 /* 0x0014 */ u32 cfg1; /* Slot1 config reg */
22 /* 0x0018 */ u32 cfg2; /* Slot2 config reg */
23 /* 0x001c */ u32 cfg3; /* Slot3 config reg */
24
25 /* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
26 /* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
27 /* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
28 /* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
29
30 /* 0x0030 */ u32 intr_state; /* Interrupt state */
31 /* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
32 /* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
33 };
34
35 #define SBI_CID 0x02800000
36 #define SBI_CTL 0x02800004
37 #define SBI_STATUS 0x02800008
38 #define SBI_CFG0 0x02800010
39 #define SBI_CFG1 0x02800014
40 #define SBI_CFG2 0x02800018
41 #define SBI_CFG3 0x0280001c
42 #define SBI_STB0 0x02800020
43 #define SBI_STB1 0x02800024
44 #define SBI_STB2 0x02800028
45 #define SBI_STB3 0x0280002c
46 #define SBI_INTR_STATE 0x02800030
47 #define SBI_INTR_TID 0x02800034
48 #define SBI_INTR_DIAG 0x02800038
49
50 /* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
51 #define SBI_CFG_BURST_MASK 0x0000001e
52
53 /* How to make devid from sbi no */
54 #define SBI2DEVID(sbino) ((sbino<<4)|2)
55
56 /* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
57 *
58 * +-------+-------+-------+-------+-------+-------+-------+-------+
59 * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
61 * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
62 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
63 * Bits 31 27 23 19 15 11 7 3 0
64 */
65
66
67 #ifndef __ASSEMBLY__
68
69 static inline int acquire_sbi(int devid, int mask)
70 {
71 __asm__ __volatile__ ("swapa [%2] %3, %0" :
72 "=r" (mask) :
73 "0" (mask),
74 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
75 "i" (ASI_M_CTL));
76 return mask;
77 }
78
79 static inline void release_sbi(int devid, int mask)
80 {
81 __asm__ __volatile__ ("sta %0, [%1] %2" : :
82 "r" (mask),
83 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
84 "i" (ASI_M_CTL));
85 }
86
87 static inline void set_sbi_tid(int devid, int targetid)
88 {
89 __asm__ __volatile__ ("sta %0, [%1] %2" : :
90 "r" (targetid),
91 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
92 "i" (ASI_M_CTL));
93 }
94
95 static inline int get_sbi_ctl(int devid, int cfgno)
96 {
97 int cfg;
98
99 __asm__ __volatile__ ("lda [%1] %2, %0" :
100 "=r" (cfg) :
101 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
102 "i" (ASI_M_CTL));
103 return cfg;
104 }
105
106 static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
107 {
108 __asm__ __volatile__ ("sta %0, [%1] %2" : :
109 "r" (cfg),
110 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
111 "i" (ASI_M_CTL));
112 }
113
114 #endif /* !__ASSEMBLY__ */
115
116 #endif /* !(_SPARC_SBI_H) */