drivers/infiniband/hw/qib/qib

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This source file includes following definitions.
qib_ibsd_ucode_loaded
qib_sd7220_clr_ibpar
qib_resync_ibepb
qib_ibsd_reset
qib_sd_trimdone_monitor
qib_sd7220_init
epb_access
epb_trans
qib_sd7220_reg_mod
qib_sd7220_ram_xfer
qib_sd7220_prog_ld
qib_sd7220_prog_vfy
qib_sd7220_ib_load
qib_sd7220_ib_vfy
qib_sd_trimdone_poll
qib_sd_setvals
ibsd_mod_allchnls
set_dds_vals
set_rxeq_vals
qib_internal_presets
qib_sd7220_presets
qib_sd_trimself
qib_sd_early
qib_sd_dactrim
toggle_7220_rclkrls
shutdown_7220_relock_poll
qib_run_relock
set_7220_relock_poll
   1 /*
   2  * Copyright (c) 2013 Intel Corporation. All rights reserved.
   3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
   4  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34 /*
  35  * This file contains all of the code that is specific to the SerDes
  36  * on the QLogic_IB 7220 chip.
  37  */
  38 
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/module.h>
  42 #include <linux/firmware.h>
  43 
  44 #include "qib.h"
  45 #include "qib_7220.h"
  46 
  47 #define SD7220_FW_NAME "qlogic/sd7220.fw"
  48 MODULE_FIRMWARE(SD7220_FW_NAME);
  49 
  50 /*
  51  * Same as in qib_iba7220.c, but just the registers needed here.
  52  * Could move whole set to qib_7220.h, but decided better to keep
  53  * local.
  54  */
  55 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
  56 #define kr_hwerrclear KREG_IDX(HwErrClear)
  57 #define kr_hwerrmask KREG_IDX(HwErrMask)
  58 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
  59 #define kr_ibcstatus KREG_IDX(IBCStatus)
  60 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
  61 #define kr_scratch KREG_IDX(Scratch)
  62 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
  63 /* these are used only here, not in qib_iba7220.c */
  64 #define kr_ibsd_epb_access_ctrl KREG_IDX(ibsd_epb_access_ctrl)
  65 #define kr_ibsd_epb_transaction_reg KREG_IDX(ibsd_epb_transaction_reg)
  66 #define kr_pciesd_epb_transaction_reg KREG_IDX(pciesd_epb_transaction_reg)
  67 #define kr_pciesd_epb_access_ctrl KREG_IDX(pciesd_epb_access_ctrl)
  68 #define kr_serdes_ddsrxeq0 KREG_IDX(SerDes_DDSRXEQ0)
  69 
  70 /*
  71  * The IBSerDesMappTable is a memory that holds values to be stored in
  72  * various SerDes registers by IBC.
  73  */
  74 #define kr_serdes_maptable KREG_IDX(IBSerDesMappTable)
  75 
  76 /*
  77  * Below used for sdnum parameter, selecting one of the two sections
  78  * used for PCIe, or the single SerDes used for IB.
  79  */
  80 #define PCIE_SERDES0 0
  81 #define PCIE_SERDES1 1
  82 
  83 /*
  84  * The EPB requires addressing in a particular form. EPB_LOC() is intended
  85  * to make #definitions a little more readable.
  86  */
  87 #define EPB_ADDR_SHF 8
  88 #define EPB_LOC(chn, elt, reg) \
  89         (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \
  90          EPB_ADDR_SHF)
  91 #define EPB_IB_QUAD0_CS_SHF (25)
  92 #define EPB_IB_QUAD0_CS (1U <<  EPB_IB_QUAD0_CS_SHF)
  93 #define EPB_IB_UC_CS_SHF (26)
  94 #define EPB_PCIE_UC_CS_SHF (27)
  95 #define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8))
  96 
  97 /* Forward declarations. */
  98 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
  99                               u32 data, u32 mask);
 100 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
 101                              int mask);
 102 static int qib_sd_trimdone_poll(struct qib_devdata *dd);
 103 static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where);
 104 static int qib_sd_setvals(struct qib_devdata *dd);
 105 static int qib_sd_early(struct qib_devdata *dd);
 106 static int qib_sd_dactrim(struct qib_devdata *dd);
 107 static int qib_internal_presets(struct qib_devdata *dd);
 108 /* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */
 109 static int qib_sd_trimself(struct qib_devdata *dd, int val);
 110 static int epb_access(struct qib_devdata *dd, int sdnum, int claim);
 111 static int qib_sd7220_ib_load(struct qib_devdata *dd,
 112                               const struct firmware *fw);
 113 static int qib_sd7220_ib_vfy(struct qib_devdata *dd,
 114                              const struct firmware *fw);
 115 
 116 /*
 117  * Below keeps track of whether the "once per power-on" initialization has
 118  * been done, because uC code Version 1.32.17 or higher allows the uC to
 119  * be reset at will, and Automatic Equalization may require it. So the
 120  * state of the reset "pin", is no longer valid. Instead, we check for the
 121  * actual uC code having been loaded.
 122  */
 123 static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd,
 124                                  const struct firmware *fw)
 125 {
 126         struct qib_devdata *dd = ppd->dd;
 127 
 128         if (!dd->cspec->serdes_first_init_done &&
 129             qib_sd7220_ib_vfy(dd, fw) > 0)
 130                 dd->cspec->serdes_first_init_done = 1;
 131         return dd->cspec->serdes_first_init_done;
 132 }
 133 
 134 /* repeat #define for local use. "Real" #define is in qib_iba7220.c */
 135 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR      0x0000004000000000ULL
 136 #define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF))
 137 #define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF))
 138 #define UC_PAR_CLR_D 8
 139 #define UC_PAR_CLR_M 0xC
 140 #define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS)
 141 #define START_EQ1(chan) EPB_LOC(chan, 7, 0x27)
 142 
 143 void qib_sd7220_clr_ibpar(struct qib_devdata *dd)
 144 {
 145         int ret;
 146 
 147         /* clear, then re-enable parity errs */
 148         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6,
 149                 UC_PAR_CLR_D, UC_PAR_CLR_M);
 150         if (ret < 0) {
 151                 qib_dev_err(dd, "Failed clearing IBSerDes Parity err\n");
 152                 goto bail;
 153         }
 154         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0,
 155                 UC_PAR_CLR_M);
 156 
 157         qib_read_kreg32(dd, kr_scratch);
 158         udelay(4);
 159         qib_write_kreg(dd, kr_hwerrclear,
 160                 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
 161         qib_read_kreg32(dd, kr_scratch);
 162 bail:
 163         return;
 164 }
 165 
 166 /*
 167  * After a reset or other unusual event, the epb interface may need
 168  * to be re-synchronized, between the host and the uC.
 169  * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected)
 170  */
 171 #define IBSD_RESYNC_TRIES 3
 172 #define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS)
 173 #define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS)
 174 
 175 static int qib_resync_ibepb(struct qib_devdata *dd)
 176 {
 177         int ret, pat, tries, chn;
 178         u32 loc;
 179 
 180         ret = -1;
 181         chn = 0;
 182         for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) {
 183                 loc = IB_PGUDP(chn);
 184                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
 185                 if (ret < 0) {
 186                         qib_dev_err(dd, "Failed read in resync\n");
 187                         continue;
 188                 }
 189                 if (ret != 0xF0 && ret != 0x55 && tries == 0)
 190                         qib_dev_err(dd, "unexpected pattern in resync\n");
 191                 pat = ret ^ 0xA5; /* alternate F0 and 55 */
 192                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF);
 193                 if (ret < 0) {
 194                         qib_dev_err(dd, "Failed write in resync\n");
 195                         continue;
 196                 }
 197                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
 198                 if (ret < 0) {
 199                         qib_dev_err(dd, "Failed re-read in resync\n");
 200                         continue;
 201                 }
 202                 if (ret != pat) {
 203                         qib_dev_err(dd, "Failed compare1 in resync\n");
 204                         continue;
 205                 }
 206                 loc = IB_CMUDONE(chn);
 207                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
 208                 if (ret < 0) {
 209                         qib_dev_err(dd, "Failed CMUDONE rd in resync\n");
 210                         continue;
 211                 }
 212                 if ((ret & 0x70) != ((chn << 4) | 0x40)) {
 213                         qib_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n",
 214                                     ret, chn);
 215                         continue;
 216                 }
 217                 if (++chn == 4)
 218                         break;  /* Success */
 219         }
 220         return (ret > 0) ? 0 : ret;
 221 }
 222 
 223 /*
 224  * Localize the stuff that should be done to change IB uC reset
 225  * returns <0 for errors.
 226  */
 227 static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst)
 228 {
 229         u64 rst_val;
 230         int ret = 0;
 231         unsigned long flags;
 232 
 233         rst_val = qib_read_kreg64(dd, kr_ibserdesctrl);
 234         if (assert_rst) {
 235                 /*
 236                  * Vendor recommends "interrupting" uC before reset, to
 237                  * minimize possible glitches.
 238                  */
 239                 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
 240                 epb_access(dd, IB_7220_SERDES, 1);
 241                 rst_val |= 1ULL;
 242                 /* Squelch possible parity error from _asserting_ reset */
 243                 qib_write_kreg(dd, kr_hwerrmask,
 244                                dd->cspec->hwerrmask &
 245                                ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
 246                 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
 247                 /* flush write, delay to ensure it took effect */
 248                 qib_read_kreg32(dd, kr_scratch);
 249                 udelay(2);
 250                 /* once it's reset, can remove interrupt */
 251                 epb_access(dd, IB_7220_SERDES, -1);
 252                 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
 253         } else {
 254                 /*
 255                  * Before we de-assert reset, we need to deal with
 256                  * possible glitch on the Parity-error line.
 257                  * Suppress it around the reset, both in chip-level
 258                  * hwerrmask and in IB uC control reg. uC will allow
 259                  * it again during startup.
 260                  */
 261                 u64 val;
 262 
 263                 rst_val &= ~(1ULL);
 264                 qib_write_kreg(dd, kr_hwerrmask,
 265                                dd->cspec->hwerrmask &
 266                                ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
 267 
 268                 ret = qib_resync_ibepb(dd);
 269                 if (ret < 0)
 270                         qib_dev_err(dd, "unable to re-sync IB EPB\n");
 271 
 272                 /* set uC control regs to suppress parity errs */
 273                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1);
 274                 if (ret < 0)
 275                         goto bail;
 276                 /* IB uC code past Version 1.32.17 allow suppression of wdog */
 277                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80,
 278                         0x80);
 279                 if (ret < 0) {
 280                         qib_dev_err(dd, "Failed to set WDOG disable\n");
 281                         goto bail;
 282                 }
 283                 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
 284                 /* flush write, delay for startup */
 285                 qib_read_kreg32(dd, kr_scratch);
 286                 udelay(1);
 287                 /* clear, then re-enable parity errs */
 288                 qib_sd7220_clr_ibpar(dd);
 289                 val = qib_read_kreg64(dd, kr_hwerrstatus);
 290                 if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) {
 291                         qib_dev_err(dd, "IBUC Parity still set after RST\n");
 292                         dd->cspec->hwerrmask &=
 293                                 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
 294                 }
 295                 qib_write_kreg(dd, kr_hwerrmask,
 296                         dd->cspec->hwerrmask);
 297         }
 298 
 299 bail:
 300         return ret;
 301 }
 302 
 303 static void qib_sd_trimdone_monitor(struct qib_devdata *dd,
 304         const char *where)
 305 {
 306         int ret, chn, baduns;
 307         u64 val;
 308 
 309         if (!where)
 310                 where = "?";
 311 
 312         /* give time for reset to settle out in EPB */
 313         udelay(2);
 314 
 315         ret = qib_resync_ibepb(dd);
 316         if (ret < 0)
 317                 qib_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where);
 318 
 319         /* Do "sacrificial read" to get EPB in sane state after reset */
 320         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0);
 321         if (ret < 0)
 322                 qib_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where);
 323 
 324         /* Check/show "summary" Trim-done bit in IBCStatus */
 325         val = qib_read_kreg64(dd, kr_ibcstatus);
 326         if (!(val & (1ULL << 11)))
 327                 qib_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where);
 328         /*
 329          * Do "dummy read/mod/wr" to get EPB in sane state after reset
 330          * The default value for MPREG6 is 0.
 331          */
 332         udelay(2);
 333 
 334         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80);
 335         if (ret < 0)
 336                 qib_dev_err(dd, "Failed Dummy RMW, (%s)\n", where);
 337         udelay(10);
 338 
 339         baduns = 0;
 340 
 341         for (chn = 3; chn >= 0; --chn) {
 342                 /* Read CTRL reg for each channel to check TRIMDONE */
 343                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
 344                         IB_CTRL2(chn), 0, 0);
 345                 if (ret < 0)
 346                         qib_dev_err(dd,
 347                                 "Failed checking TRIMDONE, chn %d (%s)\n",
 348                                 chn, where);
 349 
 350                 if (!(ret & 0x10)) {
 351                         int probe;
 352 
 353                         baduns |= (1 << chn);
 354                         qib_dev_err(dd,
 355                                 "TRIMDONE cleared on chn %d (%02X). (%s)\n",
 356                                 chn, ret, where);
 357                         probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
 358                                 IB_PGUDP(0), 0, 0);
 359                         qib_dev_err(dd, "probe is %d (%02X)\n",
 360                                 probe, probe);
 361                         probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
 362                                 IB_CTRL2(chn), 0, 0);
 363                         qib_dev_err(dd, "re-read: %d (%02X)\n",
 364                                 probe, probe);
 365                         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
 366                                 IB_CTRL2(chn), 0x10, 0x10);
 367                         if (ret < 0)
 368                                 qib_dev_err(dd,
 369                                         "Err on TRIMDONE rewrite1\n");
 370                 }
 371         }
 372         for (chn = 3; chn >= 0; --chn) {
 373                 /* Read CTRL reg for each channel to check TRIMDONE */
 374                 if (baduns & (1 << chn)) {
 375                         qib_dev_err(dd,
 376                                 "Resetting TRIMDONE on chn %d (%s)\n",
 377                                 chn, where);
 378                         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
 379                                 IB_CTRL2(chn), 0x10, 0x10);
 380                         if (ret < 0)
 381                                 qib_dev_err(dd,
 382                                         "Failed re-setting TRIMDONE, chn %d (%s)\n",
 383                                         chn, where);
 384                 }
 385         }
 386 }
 387 
 388 /*
 389  * Below is portion of IBA7220-specific bringup_serdes() that actually
 390  * deals with registers and memory within the SerDes itself.
 391  * Post IB uC code version 1.32.17, was_reset being 1 is not really
 392  * informative, so we double-check.
 393  */
 394 int qib_sd7220_init(struct qib_devdata *dd)
 395 {
 396         const struct firmware *fw;
 397         int ret = 1; /* default to failure */
 398         int first_reset, was_reset;
 399 
 400         /* SERDES MPU reset recorded in D0 */
 401         was_reset = (qib_read_kreg64(dd, kr_ibserdesctrl) & 1);
 402         if (!was_reset) {
 403                 /* entered with reset not asserted, we need to do it */
 404                 qib_ibsd_reset(dd, 1);
 405                 qib_sd_trimdone_monitor(dd, "Driver-reload");
 406         }
 407 
 408         ret = request_firmware(&fw, SD7220_FW_NAME, &dd->pcidev->dev);
 409         if (ret) {
 410                 qib_dev_err(dd, "Failed to load IB SERDES image\n");
 411                 goto done;
 412         }
 413 
 414         /* Substitute our deduced value for was_reset */
 415         ret = qib_ibsd_ucode_loaded(dd->pport, fw);
 416         if (ret < 0)
 417                 goto bail;
 418 
 419         first_reset = !ret; /* First reset if IBSD uCode not yet loaded */
 420         /*
 421          * Alter some regs per vendor latest doc, reset-defaults
 422          * are not right for IB.
 423          */
 424         ret = qib_sd_early(dd);
 425         if (ret < 0) {
 426                 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n");
 427                 goto bail;
 428         }
 429         /*
 430          * Set DAC manual trim IB.
 431          * We only do this once after chip has been reset (usually
 432          * same as once per system boot).
 433          */
 434         if (first_reset) {
 435                 ret = qib_sd_dactrim(dd);
 436                 if (ret < 0) {
 437                         qib_dev_err(dd, "Failed IB SERDES DAC trim\n");
 438                         goto bail;
 439                 }
 440         }
 441         /*
 442          * Set various registers (DDS and RXEQ) that will be
 443          * controlled by IBC (in 1.2 mode) to reasonable preset values
 444          * Calling the "internal" version avoids the "check for needed"
 445          * and "trimdone monitor" that might be counter-productive.
 446          */
 447         ret = qib_internal_presets(dd);
 448         if (ret < 0) {
 449                 qib_dev_err(dd, "Failed to set IB SERDES presets\n");
 450                 goto bail;
 451         }
 452         ret = qib_sd_trimself(dd, 0x80);
 453         if (ret < 0) {
 454                 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n");
 455                 goto bail;
 456         }
 457 
 458         /* Load image, then try to verify */
 459         ret = 0;        /* Assume success */
 460         if (first_reset) {
 461                 int vfy;
 462                 int trim_done;
 463 
 464                 ret = qib_sd7220_ib_load(dd, fw);
 465                 if (ret < 0) {
 466                         qib_dev_err(dd, "Failed to load IB SERDES image\n");
 467                         goto bail;
 468                 } else {
 469                         /* Loaded image, try to verify */
 470                         vfy = qib_sd7220_ib_vfy(dd, fw);
 471                         if (vfy != ret) {
 472                                 qib_dev_err(dd, "SERDES PRAM VFY failed\n");
 473                                 goto bail;
 474                         } /* end if verified */
 475                 } /* end if loaded */
 476 
 477                 /*
 478                  * Loaded and verified. Almost good...
 479                  * hold "success" in ret
 480                  */
 481                 ret = 0;
 482                 /*
 483                  * Prev steps all worked, continue bringup
 484                  * De-assert RESET to uC, only in first reset, to allow
 485                  * trimming.
 486                  *
 487                  * Since our default setup sets START_EQ1 to
 488                  * PRESET, we need to clear that for this very first run.
 489                  */
 490                 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38);
 491                 if (ret < 0) {
 492                         qib_dev_err(dd, "Failed clearing START_EQ1\n");
 493                         goto bail;
 494                 }
 495 
 496                 qib_ibsd_reset(dd, 0);
 497                 /*
 498                  * If this is not the first reset, trimdone should be set
 499                  * already. We may need to check about this.
 500                  */
 501                 trim_done = qib_sd_trimdone_poll(dd);
 502                 /*
 503                  * Whether or not trimdone succeeded, we need to put the
 504                  * uC back into reset to avoid a possible fight with the
 505                  * IBC state-machine.
 506                  */
 507                 qib_ibsd_reset(dd, 1);
 508 
 509                 if (!trim_done) {
 510                         qib_dev_err(dd, "No TRIMDONE seen\n");
 511                         goto bail;
 512                 }
 513                 /*
 514                  * DEBUG: check each time we reset if trimdone bits have
 515                  * gotten cleared, and re-set them.
 516                  */
 517                 qib_sd_trimdone_monitor(dd, "First-reset");
 518                 /* Remember so we do not re-do the load, dactrim, etc. */
 519                 dd->cspec->serdes_first_init_done = 1;
 520         }
 521         /*
 522          * setup for channel training and load values for
 523          * RxEq and DDS in tables used by IBC in IB1.2 mode
 524          */
 525         ret = 0;
 526         if (qib_sd_setvals(dd) >= 0)
 527                 goto done;
 528 bail:
 529         ret = 1;
 530 done:
 531         /* start relock timer regardless, but start at 1 second */
 532         set_7220_relock_poll(dd, -1);
 533 
 534         release_firmware(fw);
 535         return ret;
 536 }
 537 
 538 #define EPB_ACC_REQ 1
 539 #define EPB_ACC_GNT 0x100
 540 #define EPB_DATA_MASK 0xFF
 541 #define EPB_RD (1ULL << 24)
 542 #define EPB_TRANS_RDY (1ULL << 31)
 543 #define EPB_TRANS_ERR (1ULL << 30)
 544 #define EPB_TRANS_TRIES 5
 545 
 546 /*
 547  * query, claim, release ownership of the EPB (External Parallel Bus)
 548  * for a specified SERDES.
 549  * the "claim" parameter is >0 to claim, <0 to release, 0 to query.
 550  * Returns <0 for errors, >0 if we had ownership, else 0.
 551  */
 552 static int epb_access(struct qib_devdata *dd, int sdnum, int claim)
 553 {
 554         u16 acc;
 555         u64 accval;
 556         int owned = 0;
 557         u64 oct_sel = 0;
 558 
 559         switch (sdnum) {
 560         case IB_7220_SERDES:
 561                 /*
 562                  * The IB SERDES "ownership" is fairly simple. A single each
 563                  * request/grant.
 564                  */
 565                 acc = kr_ibsd_epb_access_ctrl;
 566                 break;
 567 
 568         case PCIE_SERDES0:
 569         case PCIE_SERDES1:
 570                 /* PCIe SERDES has two "octants", need to select which */
 571                 acc = kr_pciesd_epb_access_ctrl;
 572                 oct_sel = (2 << (sdnum - PCIE_SERDES0));
 573                 break;
 574 
 575         default:
 576                 return 0;
 577         }
 578 
 579         /* Make sure any outstanding transaction was seen */
 580         qib_read_kreg32(dd, kr_scratch);
 581         udelay(15);
 582 
 583         accval = qib_read_kreg32(dd, acc);
 584 
 585         owned = !!(accval & EPB_ACC_GNT);
 586         if (claim < 0) {
 587                 /* Need to release */
 588                 u64 pollval;
 589                 /*
 590                  * The only writeable bits are the request and CS.
 591                  * Both should be clear
 592                  */
 593                 u64 newval = 0;
 594 
 595                 qib_write_kreg(dd, acc, newval);
 596                 /* First read after write is not trustworthy */
 597                 pollval = qib_read_kreg32(dd, acc);
 598                 udelay(5);
 599                 pollval = qib_read_kreg32(dd, acc);
 600                 if (pollval & EPB_ACC_GNT)
 601                         owned = -1;
 602         } else if (claim > 0) {
 603                 /* Need to claim */
 604                 u64 pollval;
 605                 u64 newval = EPB_ACC_REQ | oct_sel;
 606 
 607                 qib_write_kreg(dd, acc, newval);
 608                 /* First read after write is not trustworthy */
 609                 pollval = qib_read_kreg32(dd, acc);
 610                 udelay(5);
 611                 pollval = qib_read_kreg32(dd, acc);
 612                 if (!(pollval & EPB_ACC_GNT))
 613                         owned = -1;
 614         }
 615         return owned;
 616 }
 617 
 618 /*
 619  * Lemma to deal with race condition of write..read to epb regs
 620  */
 621 static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp)
 622 {
 623         int tries;
 624         u64 transval;
 625 
 626         qib_write_kreg(dd, reg, i_val);
 627         /* Throw away first read, as RDY bit may be stale */
 628         transval = qib_read_kreg64(dd, reg);
 629 
 630         for (tries = EPB_TRANS_TRIES; tries; --tries) {
 631                 transval = qib_read_kreg32(dd, reg);
 632                 if (transval & EPB_TRANS_RDY)
 633                         break;
 634                 udelay(5);
 635         }
 636         if (transval & EPB_TRANS_ERR)
 637                 return -1;
 638         if (tries > 0 && o_vp)
 639                 *o_vp = transval;
 640         return tries;
 641 }
 642 
 643 /**
 644  * qib_sd7220_reg_mod - modify SERDES register
 645  * @dd: the qlogic_ib device
 646  * @sdnum: which SERDES to access
 647  * @loc: location - channel, element, register, as packed by EPB_LOC() macro.
 648  * @wd: Write Data - value to set in register
 649  * @mask: ones where data should be spliced into reg.
 650  *
 651  * Basic register read/modify/write, with un-needed acesses elided. That is,
 652  * a mask of zero will prevent write, while a mask of 0xFF will prevent read.
 653  * returns current (presumed, if a write was done) contents of selected
 654  * register, or <0 if errors.
 655  */
 656 static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
 657                               u32 wd, u32 mask)
 658 {
 659         u16 trans;
 660         u64 transval;
 661         int owned;
 662         int tries, ret;
 663         unsigned long flags;
 664 
 665         switch (sdnum) {
 666         case IB_7220_SERDES:
 667                 trans = kr_ibsd_epb_transaction_reg;
 668                 break;
 669 
 670         case PCIE_SERDES0:
 671         case PCIE_SERDES1:
 672                 trans = kr_pciesd_epb_transaction_reg;
 673                 break;
 674 
 675         default:
 676                 return -1;
 677         }
 678 
 679         /*
 680          * All access is locked in software (vs other host threads) and
 681          * hardware (vs uC access).
 682          */
 683         spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
 684 
 685         owned = epb_access(dd, sdnum, 1);
 686         if (owned < 0) {
 687                 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
 688                 return -1;
 689         }
 690         ret = 0;
 691         for (tries = EPB_TRANS_TRIES; tries; --tries) {
 692                 transval = qib_read_kreg32(dd, trans);
 693                 if (transval & EPB_TRANS_RDY)
 694                         break;
 695                 udelay(5);
 696         }
 697 
 698         if (tries > 0) {
 699                 tries = 1;      /* to make read-skip work */
 700                 if (mask != 0xFF) {
 701                         /*
 702                          * Not a pure write, so need to read.
 703                          * loc encodes chip-select as well as address
 704                          */
 705                         transval = loc | EPB_RD;
 706                         tries = epb_trans(dd, trans, transval, &transval);
 707                 }
 708                 if (tries > 0 && mask != 0) {
 709                         /*
 710                          * Not a pure read, so need to write.
 711                          */
 712                         wd = (wd & mask) | (transval & ~mask);
 713                         transval = loc | (wd & EPB_DATA_MASK);
 714                         tries = epb_trans(dd, trans, transval, &transval);
 715                 }
 716         }
 717         /* else, failed to see ready, what error-handling? */
 718 
 719         /*
 720          * Release bus. Failure is an error.
 721          */
 722         if (epb_access(dd, sdnum, -1) < 0)
 723                 ret = -1;
 724         else
 725                 ret = transval & EPB_DATA_MASK;
 726 
 727         spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
 728         if (tries <= 0)
 729                 ret = -1;
 730         return ret;
 731 }
 732 
 733 #define EPB_ROM_R (2)
 734 #define EPB_ROM_W (1)
 735 /*
 736  * Below, all uC-related, use appropriate UC_CS, depending
 737  * on which SerDes is used.
 738  */
 739 #define EPB_UC_CTL EPB_LOC(6, 0, 0)
 740 #define EPB_MADDRL EPB_LOC(6, 0, 2)
 741 #define EPB_MADDRH EPB_LOC(6, 0, 3)
 742 #define EPB_ROMDATA EPB_LOC(6, 0, 4)
 743 #define EPB_RAMDATA EPB_LOC(6, 0, 5)
 744 
 745 /* Transfer date to/from uC Program RAM of IB or PCIe SerDes */
 746 static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc,
 747                                u8 *buf, int cnt, int rd_notwr)
 748 {
 749         u16 trans;
 750         u64 transval;
 751         u64 csbit;
 752         int owned;
 753         int tries;
 754         int sofar;
 755         int addr;
 756         int ret;
 757         unsigned long flags;
 758 
 759         /* Pick appropriate transaction reg and "Chip select" for this serdes */
 760         switch (sdnum) {
 761         case IB_7220_SERDES:
 762                 csbit = 1ULL << EPB_IB_UC_CS_SHF;
 763                 trans = kr_ibsd_epb_transaction_reg;
 764                 break;
 765 
 766         case PCIE_SERDES0:
 767         case PCIE_SERDES1:
 768                 /* PCIe SERDES has uC "chip select" in different bit, too */
 769                 csbit = 1ULL << EPB_PCIE_UC_CS_SHF;
 770                 trans = kr_pciesd_epb_transaction_reg;
 771                 break;
 772 
 773         default:
 774                 return -1;
 775         }
 776 
 777         spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
 778 
 779         owned = epb_access(dd, sdnum, 1);
 780         if (owned < 0) {
 781                 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
 782                 return -1;
 783         }
 784 
 785         /*
 786          * In future code, we may need to distinguish several address ranges,
 787          * and select various memories based on this. For now, just trim
 788          * "loc" (location including address and memory select) to
 789          * "addr" (address within memory). we will only support PRAM
 790          * The memory is 8KB.
 791          */
 792         addr = loc & 0x1FFF;
 793         for (tries = EPB_TRANS_TRIES; tries; --tries) {
 794                 transval = qib_read_kreg32(dd, trans);
 795                 if (transval & EPB_TRANS_RDY)
 796                         break;
 797                 udelay(5);
 798         }
 799 
 800         sofar = 0;
 801         if (tries > 0) {
 802                 /*
 803                  * Every "memory" access is doubly-indirect.
 804                  * We set two bytes of address, then read/write
 805                  * one or mores bytes of data.
 806                  */
 807 
 808                 /* First, we set control to "Read" or "Write" */
 809                 transval = csbit | EPB_UC_CTL |
 810                         (rd_notwr ? EPB_ROM_R : EPB_ROM_W);
 811                 tries = epb_trans(dd, trans, transval, &transval);
 812                 while (tries > 0 && sofar < cnt) {
 813                         if (!sofar) {
 814                                 /* Only set address at start of chunk */
 815                                 int addrbyte = (addr + sofar) >> 8;
 816 
 817                                 transval = csbit | EPB_MADDRH | addrbyte;
 818                                 tries = epb_trans(dd, trans, transval,
 819                                                   &transval);
 820                                 if (tries <= 0)
 821                                         break;
 822                                 addrbyte = (addr + sofar) & 0xFF;
 823                                 transval = csbit | EPB_MADDRL | addrbyte;
 824                                 tries = epb_trans(dd, trans, transval,
 825                                                  &transval);
 826                                 if (tries <= 0)
 827                                         break;
 828                         }
 829 
 830                         if (rd_notwr)
 831                                 transval = csbit | EPB_ROMDATA | EPB_RD;
 832                         else
 833                                 transval = csbit | EPB_ROMDATA | buf[sofar];
 834                         tries = epb_trans(dd, trans, transval, &transval);
 835                         if (tries <= 0)
 836                                 break;
 837                         if (rd_notwr)
 838                                 buf[sofar] = transval & EPB_DATA_MASK;
 839                         ++sofar;
 840                 }
 841                 /* Finally, clear control-bit for Read or Write */
 842                 transval = csbit | EPB_UC_CTL;
 843                 tries = epb_trans(dd, trans, transval, &transval);
 844         }
 845 
 846         ret = sofar;
 847         /* Release bus. Failure is an error */
 848         if (epb_access(dd, sdnum, -1) < 0)
 849                 ret = -1;
 850 
 851         spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
 852         if (tries <= 0)
 853                 ret = -1;
 854         return ret;
 855 }
 856 
 857 #define PROG_CHUNK 64
 858 
 859 static int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum,
 860                               const u8 *img, int len, int offset)
 861 {
 862         int cnt, sofar, req;
 863 
 864         sofar = 0;
 865         while (sofar < len) {
 866                 req = len - sofar;
 867                 if (req > PROG_CHUNK)
 868                         req = PROG_CHUNK;
 869                 cnt = qib_sd7220_ram_xfer(dd, sdnum, offset + sofar,
 870                                           (u8 *)img + sofar, req, 0);
 871                 if (cnt < req) {
 872                         sofar = -1;
 873                         break;
 874                 }
 875                 sofar += req;
 876         }
 877         return sofar;
 878 }
 879 
 880 #define VFY_CHUNK 64
 881 #define SD_PRAM_ERROR_LIMIT 42
 882 
 883 static int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum,
 884                                const u8 *img, int len, int offset)
 885 {
 886         int cnt, sofar, req, idx, errors;
 887         unsigned char readback[VFY_CHUNK];
 888 
 889         errors = 0;
 890         sofar = 0;
 891         while (sofar < len) {
 892                 req = len - sofar;
 893                 if (req > VFY_CHUNK)
 894                         req = VFY_CHUNK;
 895                 cnt = qib_sd7220_ram_xfer(dd, sdnum, sofar + offset,
 896                                           readback, req, 1);
 897                 if (cnt < req) {
 898                         /* failed in read itself */
 899                         sofar = -1;
 900                         break;
 901                 }
 902                 for (idx = 0; idx < cnt; ++idx) {
 903                         if (readback[idx] != img[idx+sofar])
 904                                 ++errors;
 905                 }
 906                 sofar += cnt;
 907         }
 908         return errors ? -errors : sofar;
 909 }
 910 
 911 static int
 912 qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw)
 913 {
 914         return qib_sd7220_prog_ld(dd, IB_7220_SERDES, fw->data, fw->size, 0);
 915 }
 916 
 917 static int
 918 qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw)
 919 {
 920         return qib_sd7220_prog_vfy(dd, IB_7220_SERDES, fw->data, fw->size, 0);
 921 }
 922 
 923 /*
 924  * IRQ not set up at this point in init, so we poll.
 925  */
 926 #define IB_SERDES_TRIM_DONE (1ULL << 11)
 927 #define TRIM_TMO (15)
 928 
 929 static int qib_sd_trimdone_poll(struct qib_devdata *dd)
 930 {
 931         int trim_tmo, ret;
 932         uint64_t val;
 933 
 934         /*
 935          * Default to failure, so IBC will not start
 936          * without IB_SERDES_TRIM_DONE.
 937          */
 938         ret = 0;
 939         for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) {
 940                 val = qib_read_kreg64(dd, kr_ibcstatus);
 941                 if (val & IB_SERDES_TRIM_DONE) {
 942                         ret = 1;
 943                         break;
 944                 }
 945                 msleep(20);
 946         }
 947         if (trim_tmo >= TRIM_TMO) {
 948                 qib_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo);
 949                 ret = 0;
 950         }
 951         return ret;
 952 }
 953 
 954 #define TX_FAST_ELT (9)
 955 
 956 /*
 957  * Set the "negotiation" values for SERDES. These are used by the IB1.2
 958  * link negotiation. Macros below are attempt to keep the values a
 959  * little more human-editable.
 960  * First, values related to Drive De-emphasis Settings.
 961  */
 962 
 963 #define NUM_DDS_REGS 6
 964 #define DDS_REG_MAP 0x76A910 /* LSB-first list of regs (in elt 9) to mod */
 965 
 966 #define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \
 967         { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \
 968           (main_d << 3) | 4 | (ipre_d >> 2), \
 969           (main_s << 3) | 4 | (ipre_s >> 2), \
 970           ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \
 971           ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } }
 972 
 973 static struct dds_init {
 974         uint8_t reg_vals[NUM_DDS_REGS];
 975 } dds_init_vals[] = {
 976         /*       DDR(FDR)       SDR(HDR)   */
 977         /* Vendor recommends below for 3m cable */
 978 #define DDS_3M 0
 979         DDS_VAL(31, 19, 12, 0, 29, 22,  9, 0),
 980         DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1),
 981         DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0),
 982         DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0),
 983         DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0),
 984         DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0),
 985         DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0),
 986         DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0),
 987         DDS_VAL(31, 20, 11, 0, 28, 23,  8, 0),
 988         DDS_VAL(31, 21, 10, 0, 27, 24,  7, 0),
 989         DDS_VAL(31, 22,  9, 0, 26, 25,  6, 0),
 990         DDS_VAL(30, 23,  8, 0, 25, 26,  5, 0),
 991         DDS_VAL(29, 24,  7, 0, 23, 27,  4, 0),
 992         /* Vendor recommends below for 1m cable */
 993 #define DDS_1M 13
 994         DDS_VAL(28, 25,  6, 0, 21, 28,  3, 0),
 995         DDS_VAL(27, 26,  5, 0, 19, 29,  2, 0),
 996         DDS_VAL(25, 27,  4, 0, 17, 30,  1, 0)
 997 };
 998 
 999 /*
1000  * Now the RXEQ section of the table.
1001  */
1002 /* Hardware packs an element number and register address thus: */
1003 #define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4))
1004 #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
1005         {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
1006 
1007 #define RXEQ_VAL_ALL(elt, adr, val)  \
1008         {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} }
1009 
1010 #define RXEQ_SDR_DFELTH 0
1011 #define RXEQ_SDR_TLTH 0
1012 #define RXEQ_SDR_G1CNT_Z1CNT 0x11
1013 #define RXEQ_SDR_ZCNT 23
1014 
1015 static struct rxeq_init {
1016         u16 rdesc;      /* in form used in SerDesDDSRXEQ */
1017         u8  rdata[4];
1018 } rxeq_init_vals[] = {
1019         /* Set Rcv Eq. to Preset node */
1020         RXEQ_VAL_ALL(7, 0x27, 0x10),
1021         /* Set DFELTHFDR/HDR thresholds */
1022         RXEQ_VAL(7, 8,    0, 0, 0, 0), /* FDR, was 0, 1, 2, 3 */
1023         RXEQ_VAL(7, 0x21, 0, 0, 0, 0), /* HDR */
1024         /* Set TLTHFDR/HDR theshold */
1025         RXEQ_VAL(7, 9,    2, 2, 2, 2), /* FDR, was 0, 2, 4, 6 */
1026         RXEQ_VAL(7, 0x23, 2, 2, 2, 2), /* HDR, was  0, 1, 2, 3 */
1027         /* Set Preamp setting 2 (ZFR/ZCNT) */
1028         RXEQ_VAL(7, 0x1B, 12, 12, 12, 12), /* FDR, was 12, 16, 20, 24 */
1029         RXEQ_VAL(7, 0x1C, 12, 12, 12, 12), /* HDR, was 12, 16, 20, 24 */
1030         /* Set Preamp DC gain and Setting 1 (GFR/GHR) */
1031         RXEQ_VAL(7, 0x1E, 16, 16, 16, 16), /* FDR, was 16, 17, 18, 20 */
1032         RXEQ_VAL(7, 0x1F, 16, 16, 16, 16), /* HDR, was 16, 17, 18, 20 */
1033         /* Toggle RELOCK (in VCDL_CTRL0) to lock to data */
1034         RXEQ_VAL_ALL(6, 6, 0x20), /* Set D5 High */
1035         RXEQ_VAL_ALL(6, 6, 0), /* Set D5 Low */
1036 };
1037 
1038 /* There are 17 values from vendor, but IBC only accesses the first 16 */
1039 #define DDS_ROWS (16)
1040 #define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals)
1041 
1042 static int qib_sd_setvals(struct qib_devdata *dd)
1043 {
1044         int idx, midx;
1045         int min_idx;     /* Minimum index for this portion of table */
1046         uint32_t dds_reg_map;
1047         u64 __iomem *taddr, *iaddr;
1048         uint64_t data;
1049         uint64_t sdctl;
1050 
1051         taddr = dd->kregbase + kr_serdes_maptable;
1052         iaddr = dd->kregbase + kr_serdes_ddsrxeq0;
1053 
1054         /*
1055          * Init the DDS section of the table.
1056          * Each "row" of the table provokes NUM_DDS_REG writes, to the
1057          * registers indicated in DDS_REG_MAP.
1058          */
1059         sdctl = qib_read_kreg64(dd, kr_ibserdesctrl);
1060         sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8);
1061         sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13);
1062         qib_write_kreg(dd, kr_ibserdesctrl, sdctl);
1063 
1064         /*
1065          * Iterate down table within loop for each register to store.
1066          */
1067         dds_reg_map = DDS_REG_MAP;
1068         for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1069                 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT;
1070                 writeq(data, iaddr + idx);
1071                 qib_read_kreg32(dd, kr_scratch);
1072                 dds_reg_map >>= 4;
1073                 for (midx = 0; midx < DDS_ROWS; ++midx) {
1074                         u64 __iomem *daddr = taddr + ((midx << 4) + idx);
1075 
1076                         data = dds_init_vals[midx].reg_vals[idx];
1077                         writeq(data, daddr);
1078                         qib_read_kreg32(dd, kr_scratch);
1079                 } /* End inner for (vals for this reg, each row) */
1080         } /* end outer for (regs to be stored) */
1081 
1082         /*
1083          * Init the RXEQ section of the table.
1084          * This runs in a different order, as the pattern of
1085          * register references is more complex, but there are only
1086          * four "data" values per register.
1087          */
1088         min_idx = idx; /* RXEQ indices pick up where DDS left off */
1089         taddr += 0x100; /* RXEQ data is in second half of table */
1090         /* Iterate through RXEQ register addresses */
1091         for (idx = 0; idx < RXEQ_ROWS; ++idx) {
1092                 int didx; /* "destination" */
1093                 int vidx;
1094 
1095                 /* didx is offset by min_idx to address RXEQ range of regs */
1096                 didx = idx + min_idx;
1097                 /* Store the next RXEQ register address */
1098                 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx);
1099                 qib_read_kreg32(dd, kr_scratch);
1100                 /* Iterate through RXEQ values */
1101                 for (vidx = 0; vidx < 4; vidx++) {
1102                         data = rxeq_init_vals[idx].rdata[vidx];
1103                         writeq(data, taddr + (vidx << 6) + idx);
1104                         qib_read_kreg32(dd, kr_scratch);
1105                 }
1106         } /* end outer for (Reg-writes for RXEQ) */
1107         return 0;
1108 }
1109 
1110 #define CMUCTRL5 EPB_LOC(7, 0, 0x15)
1111 #define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0)
1112 #define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5)
1113 #define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6)
1114 #define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8)
1115 #define START_EQ2(chan) EPB_LOC(chan, 7, 0x28)
1116 
1117 /*
1118  * Repeat a "store" across all channels of the IB SerDes.
1119  * Although nominally it inherits the "read value" of the last
1120  * channel it modified, the only really useful return is <0 for
1121  * failure, >= 0 for success. The parameter 'loc' is assumed to
1122  * be the location in some channel of the register to be modified
1123  * The caller can specify use of the "gang write" option of EPB,
1124  * in which case we use the specified channel data for any fields
1125  * not explicitely written.
1126  */
1127 static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
1128                              int mask)
1129 {
1130         int ret = -1;
1131         int chnl;
1132 
1133         if (loc & EPB_GLOBAL_WR) {
1134                 /*
1135                  * Our caller has assured us that we can set all four
1136                  * channels at once. Trust that. If mask is not 0xFF,
1137                  * we will read the _specified_ channel for our starting
1138                  * value.
1139                  */
1140                 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1141                 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7;
1142                 if (mask != 0xFF) {
1143                         ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
1144                                                  loc & ~EPB_GLOBAL_WR, 0, 0);
1145                         if (ret < 0) {
1146                                 int sloc = loc >> EPB_ADDR_SHF;
1147 
1148                                 qib_dev_err(dd,
1149                                         "pre-read failed: elt %d, addr 0x%X, chnl %d\n",
1150                                         (sloc & 0xF),
1151                                         (sloc >> 9) & 0x3f, chnl);
1152                                 return ret;
1153                         }
1154                         val = (ret & ~mask) | (val & mask);
1155                 }
1156                 loc &=  ~(7 << (4+EPB_ADDR_SHF));
1157                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1158                 if (ret < 0) {
1159                         int sloc = loc >> EPB_ADDR_SHF;
1160 
1161                         qib_dev_err(dd,
1162                                 "Global WR failed: elt %d, addr 0x%X, val %02X\n",
1163                                 (sloc & 0xF), (sloc >> 9) & 0x3f, val);
1164                 }
1165                 return ret;
1166         }
1167         /* Clear "channel" and set CS so we can simply iterate */
1168         loc &=  ~(7 << (4+EPB_ADDR_SHF));
1169         loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1170         for (chnl = 0; chnl < 4; ++chnl) {
1171                 int cloc = loc | (chnl << (4+EPB_ADDR_SHF));
1172 
1173                 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask);
1174                 if (ret < 0) {
1175                         int sloc = loc >> EPB_ADDR_SHF;
1176 
1177                         qib_dev_err(dd,
1178                                 "Write failed: elt %d, addr 0x%X, chnl %d, val 0x%02X, mask 0x%02X\n",
1179                                 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl,
1180                                 val & 0xFF, mask & 0xFF);
1181                         break;
1182                 }
1183         }
1184         return ret;
1185 }
1186 
1187 /*
1188  * Set the Tx values normally modified by IBC in IB1.2 mode to default
1189  * values, as gotten from first row of init table.
1190  */
1191 static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi)
1192 {
1193         int ret;
1194         int idx, reg, data;
1195         uint32_t regmap;
1196 
1197         regmap = DDS_REG_MAP;
1198         for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1199                 reg = (regmap & 0xF);
1200                 regmap >>= 4;
1201                 data = ddi->reg_vals[idx];
1202                 /* Vendor says RMW not needed for these regs, use 0xFF mask */
1203                 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF);
1204                 if (ret < 0)
1205                         break;
1206         }
1207         return ret;
1208 }
1209 
1210 /*
1211  * Set the Rx values normally modified by IBC in IB1.2 mode to default
1212  * values, as gotten from selected column of init table.
1213  */
1214 static int set_rxeq_vals(struct qib_devdata *dd, int vsel)
1215 {
1216         int ret;
1217         int ridx;
1218         int cnt = ARRAY_SIZE(rxeq_init_vals);
1219 
1220         for (ridx = 0; ridx < cnt; ++ridx) {
1221                 int elt, reg, val, loc;
1222 
1223                 elt = rxeq_init_vals[ridx].rdesc & 0xF;
1224                 reg = rxeq_init_vals[ridx].rdesc >> 4;
1225                 loc = EPB_LOC(0, elt, reg);
1226                 val = rxeq_init_vals[ridx].rdata[vsel];
1227                 /* mask of 0xFF, because hardware does full-byte store. */
1228                 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF);
1229                 if (ret < 0)
1230                         break;
1231         }
1232         return ret;
1233 }
1234 
1235 /*
1236  * Set the default values (row 0) for DDR Driver Demphasis.
1237  * we do this initially and whenever we turn off IB-1.2
1238  *
1239  * The "default" values for Rx equalization are also stored to
1240  * SerDes registers. Formerly (and still default), we used set 2.
1241  * For experimenting with cables and link-partners, we allow changing
1242  * that via a module parameter.
1243  */
1244 static unsigned qib_rxeq_set = 2;
1245 module_param_named(rxeq_default_set, qib_rxeq_set, uint,
1246                    S_IWUSR | S_IRUGO);
1247 MODULE_PARM_DESC(rxeq_default_set,
1248                  "Which set [0..3] of Rx Equalization values is default");
1249 
1250 static int qib_internal_presets(struct qib_devdata *dd)
1251 {
1252         int ret = 0;
1253 
1254         ret = set_dds_vals(dd, dds_init_vals + DDS_3M);
1255 
1256         if (ret < 0)
1257                 qib_dev_err(dd, "Failed to set default DDS values\n");
1258         ret = set_rxeq_vals(dd, qib_rxeq_set & 3);
1259         if (ret < 0)
1260                 qib_dev_err(dd, "Failed to set default RXEQ values\n");
1261         return ret;
1262 }
1263 
1264 int qib_sd7220_presets(struct qib_devdata *dd)
1265 {
1266         int ret = 0;
1267 
1268         if (!dd->cspec->presets_needed)
1269                 return ret;
1270         dd->cspec->presets_needed = 0;
1271         /* Assert uC reset, so we don't clash with it. */
1272         qib_ibsd_reset(dd, 1);
1273         udelay(2);
1274         qib_sd_trimdone_monitor(dd, "link-down");
1275 
1276         ret = qib_internal_presets(dd);
1277         return ret;
1278 }
1279 
1280 static int qib_sd_trimself(struct qib_devdata *dd, int val)
1281 {
1282         int loc = CMUCTRL5 | (1U << EPB_IB_QUAD0_CS_SHF);
1283 
1284         return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1285 }
1286 
1287 static int qib_sd_early(struct qib_devdata *dd)
1288 {
1289         int ret;
1290 
1291         ret = ibsd_mod_allchnls(dd, RXHSCTRL0(0) | EPB_GLOBAL_WR, 0xD4, 0xFF);
1292         if (ret < 0)
1293                 goto bail;
1294         ret = ibsd_mod_allchnls(dd, START_EQ1(0) | EPB_GLOBAL_WR, 0x10, 0xFF);
1295         if (ret < 0)
1296                 goto bail;
1297         ret = ibsd_mod_allchnls(dd, START_EQ2(0) | EPB_GLOBAL_WR, 0x30, 0xFF);
1298 bail:
1299         return ret;
1300 }
1301 
1302 #define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E)
1303 #define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6)
1304 #define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF)
1305 
1306 static int qib_sd_dactrim(struct qib_devdata *dd)
1307 {
1308         int ret;
1309 
1310         ret = ibsd_mod_allchnls(dd, VCDL_DAC2(0) | EPB_GLOBAL_WR, 0x2D, 0xFF);
1311         if (ret < 0)
1312                 goto bail;
1313 
1314         /* more fine-tuning of what will be default */
1315         ret = ibsd_mod_allchnls(dd, VCDL_CTRL2(0), 3, 0xF);
1316         if (ret < 0)
1317                 goto bail;
1318 
1319         ret = ibsd_mod_allchnls(dd, BACTRL(0) | EPB_GLOBAL_WR, 0x40, 0xFF);
1320         if (ret < 0)
1321                 goto bail;
1322 
1323         ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1324         if (ret < 0)
1325                 goto bail;
1326 
1327         ret = ibsd_mod_allchnls(dd, RXHSSTATUS(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1328         if (ret < 0)
1329                 goto bail;
1330 
1331         /*
1332          * Delay for max possible number of steps, with slop.
1333          * Each step is about 4usec.
1334          */
1335         udelay(415);
1336 
1337         ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x00, 0xFF);
1338 
1339 bail:
1340         return ret;
1341 }
1342 
1343 #define RELOCK_FIRST_MS 3
1344 #define RXLSPPM(chan) EPB_LOC(chan, 0, 2)
1345 void toggle_7220_rclkrls(struct qib_devdata *dd)
1346 {
1347         int loc = RXLSPPM(0) | EPB_GLOBAL_WR;
1348         int ret;
1349 
1350         ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1351         if (ret < 0)
1352                 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1353         else {
1354                 udelay(1);
1355                 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1356         }
1357         /* And again for good measure */
1358         udelay(1);
1359         ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1360         if (ret < 0)
1361                 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1362         else {
1363                 udelay(1);
1364                 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1365         }
1366         /* Now reset xgxs and IBC to complete the recovery */
1367         dd->f_xgxs_reset(dd->pport);
1368 }
1369 
1370 /*
1371  * Shut down the timer that polls for relock occasions, if needed
1372  * this is "hooked" from qib_7220_quiet_serdes(), which is called
1373  * just before qib_shutdown_device() in qib_driver.c shuts down all
1374  * the other timers
1375  */
1376 void shutdown_7220_relock_poll(struct qib_devdata *dd)
1377 {
1378         if (dd->cspec->relock_timer_active)
1379                 del_timer_sync(&dd->cspec->relock_timer);
1380 }
1381 
1382 static unsigned qib_relock_by_timer = 1;
1383 module_param_named(relock_by_timer, qib_relock_by_timer, uint,
1384                    S_IWUSR | S_IRUGO);
1385 MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1386 
1387 static void qib_run_relock(struct timer_list *t)
1388 {
1389         struct qib_chip_specific *cs = from_timer(cs, t, relock_timer);
1390         struct qib_devdata *dd = cs->dd;
1391         struct qib_pportdata *ppd = dd->pport;
1392         int timeoff;
1393 
1394         /*
1395          * Check link-training state for "stuck" state, when down.
1396          * if found, try relock and schedule another try at
1397          * exponentially growing delay, maxed at one second.
1398          * if not stuck, our work is done.
1399          */
1400         if ((dd->flags & QIB_INITTED) && !(ppd->lflags &
1401             (QIBL_IB_AUTONEG_INPROG | QIBL_LINKINIT | QIBL_LINKARMED |
1402              QIBL_LINKACTIVE))) {
1403                 if (qib_relock_by_timer) {
1404                         if (!(ppd->lflags & QIBL_IB_LINK_DISABLED))
1405                                 toggle_7220_rclkrls(dd);
1406                 }
1407                 /* re-set timer for next check */
1408                 timeoff = cs->relock_interval << 1;
1409                 if (timeoff > HZ)
1410                         timeoff = HZ;
1411                 cs->relock_interval = timeoff;
1412         } else
1413                 timeoff = HZ;
1414         mod_timer(&cs->relock_timer, jiffies + timeoff);
1415 }
1416 
1417 void set_7220_relock_poll(struct qib_devdata *dd, int ibup)
1418 {
1419         struct qib_chip_specific *cs = dd->cspec;
1420 
1421         if (ibup) {
1422                 /* We are now up, relax timer to 1 second interval */
1423                 if (cs->relock_timer_active) {
1424                         cs->relock_interval = HZ;
1425                         mod_timer(&cs->relock_timer, jiffies + HZ);
1426                 }
1427         } else {
1428                 /* Transition to down, (re-)set timer to short interval. */
1429                 unsigned int timeout;
1430 
1431                 timeout = msecs_to_jiffies(RELOCK_FIRST_MS);
1432                 if (timeout == 0)
1433                         timeout = 1;
1434                 /* If timer has not yet been started, do so. */
1435                 if (!cs->relock_timer_active) {
1436                         cs->relock_timer_active = 1;
1437                         timer_setup(&cs->relock_timer, qib_run_relock, 0);
1438                         cs->relock_interval = timeout;
1439                         cs->relock_timer.expires = jiffies + timeout;
1440                         add_timer(&cs->relock_timer);
1441                 } else {
1442                         cs->relock_interval = timeout;
1443                         mod_timer(&cs->relock_timer, jiffies + timeout);
1444                 }
1445         }
1446 }
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root/drivers/infiniband/hw/qib/qib_sd7220.c

DEFINITIONS
