1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2 /*
3 * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6 #ifndef _EFA_ADMIN_CMDS_H_
7 #define _EFA_ADMIN_CMDS_H_
8
9 #define EFA_ADMIN_API_VERSION_MAJOR 0
10 #define EFA_ADMIN_API_VERSION_MINOR 1
11
12 /* EFA admin queue opcodes */
13 enum efa_admin_aq_opcode {
14 EFA_ADMIN_CREATE_QP = 1,
15 EFA_ADMIN_MODIFY_QP = 2,
16 EFA_ADMIN_QUERY_QP = 3,
17 EFA_ADMIN_DESTROY_QP = 4,
18 EFA_ADMIN_CREATE_AH = 5,
19 EFA_ADMIN_DESTROY_AH = 6,
20 EFA_ADMIN_REG_MR = 7,
21 EFA_ADMIN_DEREG_MR = 8,
22 EFA_ADMIN_CREATE_CQ = 9,
23 EFA_ADMIN_DESTROY_CQ = 10,
24 EFA_ADMIN_GET_FEATURE = 11,
25 EFA_ADMIN_SET_FEATURE = 12,
26 EFA_ADMIN_GET_STATS = 13,
27 EFA_ADMIN_ALLOC_PD = 14,
28 EFA_ADMIN_DEALLOC_PD = 15,
29 EFA_ADMIN_ALLOC_UAR = 16,
30 EFA_ADMIN_DEALLOC_UAR = 17,
31 EFA_ADMIN_MAX_OPCODE = 17,
32 };
33
34 enum efa_admin_aq_feature_id {
35 EFA_ADMIN_DEVICE_ATTR = 1,
36 EFA_ADMIN_AENQ_CONFIG = 2,
37 EFA_ADMIN_NETWORK_ATTR = 3,
38 EFA_ADMIN_QUEUE_ATTR = 4,
39 EFA_ADMIN_HW_HINTS = 5,
40 EFA_ADMIN_FEATURES_OPCODE_NUM = 8,
41 };
42
43 /* QP transport type */
44 enum efa_admin_qp_type {
45 /* Unreliable Datagram */
46 EFA_ADMIN_QP_TYPE_UD = 1,
47 /* Scalable Reliable Datagram */
48 EFA_ADMIN_QP_TYPE_SRD = 2,
49 };
50
51 /* QP state */
52 enum efa_admin_qp_state {
53 EFA_ADMIN_QP_STATE_RESET = 0,
54 EFA_ADMIN_QP_STATE_INIT = 1,
55 EFA_ADMIN_QP_STATE_RTR = 2,
56 EFA_ADMIN_QP_STATE_RTS = 3,
57 EFA_ADMIN_QP_STATE_SQD = 4,
58 EFA_ADMIN_QP_STATE_SQE = 5,
59 EFA_ADMIN_QP_STATE_ERR = 6,
60 };
61
62 enum efa_admin_get_stats_type {
63 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0,
64 };
65
66 enum efa_admin_get_stats_scope {
67 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0,
68 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1,
69 };
70
71 enum efa_admin_modify_qp_mask_bits {
72 EFA_ADMIN_QP_STATE_BIT = 0,
73 EFA_ADMIN_CUR_QP_STATE_BIT = 1,
74 EFA_ADMIN_QKEY_BIT = 2,
75 EFA_ADMIN_SQ_PSN_BIT = 3,
76 EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT = 4,
77 };
78
79 /*
80 * QP allocation sizes, converted by fabric QueuePair (QP) create command
81 * from QP capabilities.
82 */
83 struct efa_admin_qp_alloc_size {
84 /* Send descriptor ring size in bytes */
85 u32 send_queue_ring_size;
86
87 /* Max number of WQEs that can be outstanding on send queue. */
88 u32 send_queue_depth;
89
90 /*
91 * Recv descriptor ring size in bytes, sufficient for user-provided
92 * number of WQEs
93 */
94 u32 recv_queue_ring_size;
95
96 /* Max number of WQEs that can be outstanding on recv queue */
97 u32 recv_queue_depth;
98 };
99
100 struct efa_admin_create_qp_cmd {
101 /* Common Admin Queue descriptor */
102 struct efa_admin_aq_common_desc aq_common_desc;
103
104 /* Protection Domain associated with this QP */
105 u16 pd;
106
107 /* QP type */
108 u8 qp_type;
109
110 /*
111 * 0 : sq_virt - If set, SQ ring base address is
112 * virtual (IOVA returned by MR registration)
113 * 1 : rq_virt - If set, RQ ring base address is
114 * virtual (IOVA returned by MR registration)
115 * 7:2 : reserved - MBZ
116 */
117 u8 flags;
118
119 /*
120 * Send queue (SQ) ring base physical address. This field is not
121 * used if this is a Low Latency Queue(LLQ).
122 */
123 u64 sq_base_addr;
124
125 /* Receive queue (RQ) ring base address. */
126 u64 rq_base_addr;
127
128 /* Index of CQ to be associated with Send Queue completions */
129 u32 send_cq_idx;
130
131 /* Index of CQ to be associated with Recv Queue completions */
132 u32 recv_cq_idx;
133
134 /*
135 * Memory registration key for the SQ ring, used only when not in
136 * LLQ mode and base address is virtual
137 */
138 u32 sq_l_key;
139
140 /*
141 * Memory registration key for the RQ ring, used only when base
142 * address is virtual
143 */
144 u32 rq_l_key;
145
146 /* Requested QP allocation sizes */
147 struct efa_admin_qp_alloc_size qp_alloc_size;
148
149 /* UAR number */
150 u16 uar;
151
152 /* MBZ */
153 u16 reserved;
154
155 /* MBZ */
156 u32 reserved2;
157 };
158
159 struct efa_admin_create_qp_resp {
160 /* Common Admin Queue completion descriptor */
161 struct efa_admin_acq_common_desc acq_common_desc;
162
163 /* Opaque handle to be used for consequent operations on the QP */
164 u32 qp_handle;
165
166 /* QP number in the given EFA virtual device */
167 u16 qp_num;
168
169 /* MBZ */
170 u16 reserved;
171
172 /* Index of sub-CQ for Send Queue completions */
173 u16 send_sub_cq_idx;
174
175 /* Index of sub-CQ for Receive Queue completions */
176 u16 recv_sub_cq_idx;
177
178 /* SQ doorbell address, as offset to PCIe DB BAR */
179 u32 sq_db_offset;
180
181 /* RQ doorbell address, as offset to PCIe DB BAR */
182 u32 rq_db_offset;
183
184 /*
185 * low latency send queue ring base address as an offset to PCIe
186 * MMIO LLQ_MEM BAR
187 */
188 u32 llq_descriptors_offset;
189 };
190
191 struct efa_admin_modify_qp_cmd {
192 /* Common Admin Queue descriptor */
193 struct efa_admin_aq_common_desc aq_common_desc;
194
195 /*
196 * Mask indicating which fields should be updated see enum
197 * efa_admin_modify_qp_mask_bits
198 */
199 u32 modify_mask;
200
201 /* QP handle returned by create_qp command */
202 u32 qp_handle;
203
204 /* QP state */
205 u32 qp_state;
206
207 /* Override current QP state (before applying the transition) */
208 u32 cur_qp_state;
209
210 /* QKey */
211 u32 qkey;
212
213 /* SQ PSN */
214 u32 sq_psn;
215
216 /* Enable async notification when SQ is drained */
217 u8 sq_drained_async_notify;
218
219 /* MBZ */
220 u8 reserved1;
221
222 /* MBZ */
223 u16 reserved2;
224 };
225
226 struct efa_admin_modify_qp_resp {
227 /* Common Admin Queue completion descriptor */
228 struct efa_admin_acq_common_desc acq_common_desc;
229 };
230
231 struct efa_admin_query_qp_cmd {
232 /* Common Admin Queue descriptor */
233 struct efa_admin_aq_common_desc aq_common_desc;
234
235 /* QP handle returned by create_qp command */
236 u32 qp_handle;
237 };
238
239 struct efa_admin_query_qp_resp {
240 /* Common Admin Queue completion descriptor */
241 struct efa_admin_acq_common_desc acq_common_desc;
242
243 /* QP state */
244 u32 qp_state;
245
246 /* QKey */
247 u32 qkey;
248
249 /* SQ PSN */
250 u32 sq_psn;
251
252 /* Indicates that draining is in progress */
253 u8 sq_draining;
254
255 /* MBZ */
256 u8 reserved1;
257
258 /* MBZ */
259 u16 reserved2;
260 };
261
262 struct efa_admin_destroy_qp_cmd {
263 /* Common Admin Queue descriptor */
264 struct efa_admin_aq_common_desc aq_common_desc;
265
266 /* QP handle returned by create_qp command */
267 u32 qp_handle;
268 };
269
270 struct efa_admin_destroy_qp_resp {
271 /* Common Admin Queue completion descriptor */
272 struct efa_admin_acq_common_desc acq_common_desc;
273 };
274
275 /*
276 * Create Address Handle command parameters. Must not be called more than
277 * once for the same destination
278 */
279 struct efa_admin_create_ah_cmd {
280 /* Common Admin Queue descriptor */
281 struct efa_admin_aq_common_desc aq_common_desc;
282
283 /* Destination address in network byte order */
284 u8 dest_addr[16];
285
286 /* PD number */
287 u16 pd;
288
289 u16 reserved;
290 };
291
292 struct efa_admin_create_ah_resp {
293 /* Common Admin Queue completion descriptor */
294 struct efa_admin_acq_common_desc acq_common_desc;
295
296 /* Target interface address handle (opaque) */
297 u16 ah;
298
299 u16 reserved;
300 };
301
302 struct efa_admin_destroy_ah_cmd {
303 /* Common Admin Queue descriptor */
304 struct efa_admin_aq_common_desc aq_common_desc;
305
306 /* Target interface address handle (opaque) */
307 u16 ah;
308
309 /* PD number */
310 u16 pd;
311 };
312
313 struct efa_admin_destroy_ah_resp {
314 /* Common Admin Queue completion descriptor */
315 struct efa_admin_acq_common_desc acq_common_desc;
316 };
317
318 /*
319 * Registration of MemoryRegion, required for QP working with Virtual
320 * Addresses. In standard verbs semantics, region length is limited to 2GB
321 * space, but EFA offers larger MR support for large memory space, to ease
322 * on users working with very large datasets (i.e. full GPU memory mapping).
323 */
324 struct efa_admin_reg_mr_cmd {
325 /* Common Admin Queue descriptor */
326 struct efa_admin_aq_common_desc aq_common_desc;
327
328 /* Protection Domain */
329 u16 pd;
330
331 /* MBZ */
332 u16 reserved16_w1;
333
334 /* Physical Buffer List, each element is page-aligned. */
335 union {
336 /*
337 * Inline array of guest-physical page addresses of user
338 * memory pages (optimization for short region
339 * registrations)
340 */
341 u64 inline_pbl_array[4];
342
343 /* points to PBL (direct or indirect, chained if needed) */
344 struct efa_admin_ctrl_buff_info pbl;
345 } pbl;
346
347 /* Memory region length, in bytes. */
348 u64 mr_length;
349
350 /*
351 * flags and page size
352 * 4:0 : phys_page_size_shift - page size is (1 <<
353 * phys_page_size_shift). Page size is used for
354 * building the Virtual to Physical address mapping
355 * 6:5 : reserved - MBZ
356 * 7 : mem_addr_phy_mode_en - Enable bit for physical
357 * memory registration (no translation), can be used
358 * only by privileged clients. If set, PBL must
359 * contain a single entry.
360 */
361 u8 flags;
362
363 /*
364 * permissions
365 * 0 : local_write_enable - Write permissions: value
366 * of 1 needed for RQ buffers and for RDMA write
367 * 7:1 : reserved1 - remote access flags, etc
368 */
369 u8 permissions;
370
371 u16 reserved16_w5;
372
373 /* number of pages in PBL (redundant, could be calculated) */
374 u32 page_num;
375
376 /*
377 * IO Virtual Address associated with this MR. If
378 * mem_addr_phy_mode_en is set, contains the physical address of
379 * the region.
380 */
381 u64 iova;
382 };
383
384 struct efa_admin_reg_mr_resp {
385 /* Common Admin Queue completion descriptor */
386 struct efa_admin_acq_common_desc acq_common_desc;
387
388 /*
389 * L_Key, to be used in conjunction with local buffer references in
390 * SQ and RQ WQE, or with virtual RQ/CQ rings
391 */
392 u32 l_key;
393
394 /*
395 * R_Key, to be used in RDMA messages to refer to remotely accessed
396 * memory region
397 */
398 u32 r_key;
399 };
400
401 struct efa_admin_dereg_mr_cmd {
402 /* Common Admin Queue descriptor */
403 struct efa_admin_aq_common_desc aq_common_desc;
404
405 /* L_Key, memory region's l_key */
406 u32 l_key;
407 };
408
409 struct efa_admin_dereg_mr_resp {
410 /* Common Admin Queue completion descriptor */
411 struct efa_admin_acq_common_desc acq_common_desc;
412 };
413
414 struct efa_admin_create_cq_cmd {
415 struct efa_admin_aq_common_desc aq_common_desc;
416
417 /*
418 * 4:0 : reserved5
419 * 5 : interrupt_mode_enabled - if set, cq operates
420 * in interrupt mode (i.e. CQ events and MSI-X are
421 * generated), otherwise - polling
422 * 6 : virt - If set, ring base address is virtual
423 * (IOVA returned by MR registration)
424 * 7 : reserved6
425 */
426 u8 cq_caps_1;
427
428 /*
429 * 4:0 : cq_entry_size_words - size of CQ entry in
430 * 32-bit words, valid values: 4, 8.
431 * 7:5 : reserved7
432 */
433 u8 cq_caps_2;
434
435 /* completion queue depth in # of entries. must be power of 2 */
436 u16 cq_depth;
437
438 /* msix vector assigned to this cq */
439 u32 msix_vector_idx;
440
441 /*
442 * CQ ring base address, virtual or physical depending on 'virt'
443 * flag
444 */
445 struct efa_common_mem_addr cq_ba;
446
447 /*
448 * Memory registration key for the ring, used only when base
449 * address is virtual
450 */
451 u32 l_key;
452
453 /*
454 * number of sub cqs - must be equal to sub_cqs_per_cq of queue
455 * attributes.
456 */
457 u16 num_sub_cqs;
458
459 /* UAR number */
460 u16 uar;
461 };
462
463 struct efa_admin_create_cq_resp {
464 struct efa_admin_acq_common_desc acq_common_desc;
465
466 u16 cq_idx;
467
468 /* actual cq depth in number of entries */
469 u16 cq_actual_depth;
470 };
471
472 struct efa_admin_destroy_cq_cmd {
473 struct efa_admin_aq_common_desc aq_common_desc;
474
475 u16 cq_idx;
476
477 u16 reserved1;
478 };
479
480 struct efa_admin_destroy_cq_resp {
481 struct efa_admin_acq_common_desc acq_common_desc;
482 };
483
484 /*
485 * EFA AQ Get Statistics command. Extended statistics are placed in control
486 * buffer pointed by AQ entry
487 */
488 struct efa_admin_aq_get_stats_cmd {
489 struct efa_admin_aq_common_desc aq_common_descriptor;
490
491 union {
492 /* command specific inline data */
493 u32 inline_data_w1[3];
494
495 struct efa_admin_ctrl_buff_info control_buffer;
496 } u;
497
498 /* stats type as defined in enum efa_admin_get_stats_type */
499 u8 type;
500
501 /* stats scope defined in enum efa_admin_get_stats_scope */
502 u8 scope;
503
504 u16 scope_modifier;
505 };
506
507 struct efa_admin_basic_stats {
508 u64 tx_bytes;
509
510 u64 tx_pkts;
511
512 u64 rx_bytes;
513
514 u64 rx_pkts;
515
516 u64 rx_drops;
517 };
518
519 struct efa_admin_acq_get_stats_resp {
520 struct efa_admin_acq_common_desc acq_common_desc;
521
522 struct efa_admin_basic_stats basic_stats;
523 };
524
525 struct efa_admin_get_set_feature_common_desc {
526 /*
527 * 1:0 : select - 0x1 - current value; 0x3 - default
528 * value
529 * 7:3 : reserved3
530 */
531 u8 flags;
532
533 /* as appears in efa_admin_aq_feature_id */
534 u8 feature_id;
535
536 /* MBZ */
537 u16 reserved16;
538 };
539
540 struct efa_admin_feature_device_attr_desc {
541 /* Bitmap of efa_admin_aq_feature_id */
542 u64 supported_features;
543
544 /* Bitmap of supported page sizes in MR registrations */
545 u64 page_size_cap;
546
547 u32 fw_version;
548
549 u32 admin_api_version;
550
551 u32 device_version;
552
553 /* Bar used for SQ and RQ doorbells */
554 u16 db_bar;
555
556 /* Indicates how many bits are used physical address access */
557 u8 phys_addr_width;
558
559 /* Indicates how many bits are used virtual address access */
560 u8 virt_addr_width;
561 };
562
563 struct efa_admin_feature_queue_attr_desc {
564 /* The maximum number of queue pairs supported */
565 u32 max_qp;
566
567 u32 max_sq_depth;
568
569 /* max send wr used in inline-buf */
570 u32 inline_buf_size;
571
572 u32 max_rq_depth;
573
574 /* The maximum number of completion queues supported per VF */
575 u32 max_cq;
576
577 u32 max_cq_depth;
578
579 /* Number of sub-CQs to be created for each CQ */
580 u16 sub_cqs_per_cq;
581
582 u16 reserved;
583
584 /*
585 * Maximum number of SGEs (buffs) allowed for a single send work
586 * queue element (WQE)
587 */
588 u16 max_wr_send_sges;
589
590 /* Maximum number of SGEs allowed for a single recv WQE */
591 u16 max_wr_recv_sges;
592
593 /* The maximum number of memory regions supported */
594 u32 max_mr;
595
596 /* The maximum number of pages can be registered */
597 u32 max_mr_pages;
598
599 /* The maximum number of protection domains supported */
600 u32 max_pd;
601
602 /* The maximum number of address handles supported */
603 u32 max_ah;
604
605 /* The maximum size of LLQ in bytes */
606 u32 max_llq_size;
607 };
608
609 struct efa_admin_feature_aenq_desc {
610 /* bitmask for AENQ groups the device can report */
611 u32 supported_groups;
612
613 /* bitmask for AENQ groups to report */
614 u32 enabled_groups;
615 };
616
617 struct efa_admin_feature_network_attr_desc {
618 /* Raw address data in network byte order */
619 u8 addr[16];
620
621 u32 mtu;
622 };
623
624 /*
625 * When hint value is 0, hints capabilities are not supported or driver
626 * should use its own predefined value
627 */
628 struct efa_admin_hw_hints {
629 /* value in ms */
630 u16 mmio_read_timeout;
631
632 /* value in ms */
633 u16 driver_watchdog_timeout;
634
635 /* value in ms */
636 u16 admin_completion_timeout;
637
638 /* poll interval in ms */
639 u16 poll_interval;
640 };
641
642 struct efa_admin_get_feature_cmd {
643 struct efa_admin_aq_common_desc aq_common_descriptor;
644
645 struct efa_admin_ctrl_buff_info control_buffer;
646
647 struct efa_admin_get_set_feature_common_desc feature_common;
648
649 u32 raw[11];
650 };
651
652 struct efa_admin_get_feature_resp {
653 struct efa_admin_acq_common_desc acq_common_desc;
654
655 union {
656 u32 raw[14];
657
658 struct efa_admin_feature_device_attr_desc device_attr;
659
660 struct efa_admin_feature_aenq_desc aenq;
661
662 struct efa_admin_feature_network_attr_desc network_attr;
663
664 struct efa_admin_feature_queue_attr_desc queue_attr;
665
666 struct efa_admin_hw_hints hw_hints;
667 } u;
668 };
669
670 struct efa_admin_set_feature_cmd {
671 struct efa_admin_aq_common_desc aq_common_descriptor;
672
673 struct efa_admin_ctrl_buff_info control_buffer;
674
675 struct efa_admin_get_set_feature_common_desc feature_common;
676
677 union {
678 u32 raw[11];
679
680 /* AENQ configuration */
681 struct efa_admin_feature_aenq_desc aenq;
682 } u;
683 };
684
685 struct efa_admin_set_feature_resp {
686 struct efa_admin_acq_common_desc acq_common_desc;
687
688 union {
689 u32 raw[14];
690 } u;
691 };
692
693 struct efa_admin_alloc_pd_cmd {
694 struct efa_admin_aq_common_desc aq_common_descriptor;
695 };
696
697 struct efa_admin_alloc_pd_resp {
698 struct efa_admin_acq_common_desc acq_common_desc;
699
700 /* PD number */
701 u16 pd;
702
703 /* MBZ */
704 u16 reserved;
705 };
706
707 struct efa_admin_dealloc_pd_cmd {
708 struct efa_admin_aq_common_desc aq_common_descriptor;
709
710 /* PD number */
711 u16 pd;
712
713 /* MBZ */
714 u16 reserved;
715 };
716
717 struct efa_admin_dealloc_pd_resp {
718 struct efa_admin_acq_common_desc acq_common_desc;
719 };
720
721 struct efa_admin_alloc_uar_cmd {
722 struct efa_admin_aq_common_desc aq_common_descriptor;
723 };
724
725 struct efa_admin_alloc_uar_resp {
726 struct efa_admin_acq_common_desc acq_common_desc;
727
728 /* UAR number */
729 u16 uar;
730
731 /* MBZ */
732 u16 reserved;
733 };
734
735 struct efa_admin_dealloc_uar_cmd {
736 struct efa_admin_aq_common_desc aq_common_descriptor;
737
738 /* UAR number */
739 u16 uar;
740
741 /* MBZ */
742 u16 reserved;
743 };
744
745 struct efa_admin_dealloc_uar_resp {
746 struct efa_admin_acq_common_desc acq_common_desc;
747 };
748
749 /* asynchronous event notification groups */
750 enum efa_admin_aenq_group {
751 EFA_ADMIN_FATAL_ERROR = 1,
752 EFA_ADMIN_WARNING = 2,
753 EFA_ADMIN_NOTIFICATION = 3,
754 EFA_ADMIN_KEEP_ALIVE = 4,
755 EFA_ADMIN_AENQ_GROUPS_NUM = 5,
756 };
757
758 enum efa_admin_aenq_notification_syndrom {
759 EFA_ADMIN_SUSPEND = 0,
760 EFA_ADMIN_RESUME = 1,
761 EFA_ADMIN_UPDATE_HINTS = 2,
762 };
763
764 struct efa_admin_mmio_req_read_less_resp {
765 u16 req_id;
766
767 u16 reg_off;
768
769 /* value is valid when poll is cleared */
770 u32 reg_val;
771 };
772
773 /* create_qp_cmd */
774 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0)
775 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_SHIFT 1
776 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1)
777
778 /* reg_mr_cmd */
779 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)
780 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_SHIFT 7
781 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7)
782 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0)
783
784 /* create_cq_cmd */
785 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
786 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
787 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_SHIFT 6
788 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6)
789 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
790
791 /* get_set_feature_common_desc */
792 #define EFA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
793
794 #endif /* _EFA_ADMIN_CMDS_H_ */