root/drivers/media/platform/s5p-mfc/s5p_mfc_common.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Samsung S5P Multi Format Codec v 5.0
   4  *
   5  * This file contains definitions of enums and structs used by the codec
   6  * driver.
   7  *
   8  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   9  * Kamil Debski, <k.debski@samsung.com>
  10  */
  11 
  12 #ifndef S5P_MFC_COMMON_H_
  13 #define S5P_MFC_COMMON_H_
  14 
  15 #include <linux/platform_device.h>
  16 #include <linux/videodev2.h>
  17 #include <media/v4l2-ctrls.h>
  18 #include <media/v4l2-device.h>
  19 #include <media/v4l2-ioctl.h>
  20 #include <media/videobuf2-v4l2.h>
  21 #include "regs-mfc.h"
  22 #include "regs-mfc-v10.h"
  23 
  24 #define S5P_MFC_NAME            "s5p-mfc"
  25 
  26 /* Definitions related to MFC memory */
  27 
  28 /* Offset base used to differentiate between CAPTURE and OUTPUT
  29 *  while mmaping */
  30 #define DST_QUEUE_OFF_BASE      (1 << 30)
  31 
  32 #define BANK_L_CTX      0
  33 #define BANK_R_CTX      1
  34 #define BANK_CTX_NUM    2
  35 
  36 #define MFC_BANK1_ALIGN_ORDER   13
  37 #define MFC_BANK2_ALIGN_ORDER   13
  38 #define MFC_BASE_ALIGN_ORDER    17
  39 
  40 #define MFC_FW_MAX_VERSIONS     2
  41 
  42 #include <media/videobuf2-dma-contig.h>
  43 
  44 /* MFC definitions */
  45 #define MFC_MAX_EXTRA_DPB       5
  46 #define MFC_MAX_BUFFERS         32
  47 #define MFC_NUM_CONTEXTS        4
  48 /* Interrupt timeout */
  49 #define MFC_INT_TIMEOUT         2000
  50 /* Busy wait timeout */
  51 #define MFC_BW_TIMEOUT          500
  52 /* Watchdog interval */
  53 #define MFC_WATCHDOG_INTERVAL   1000
  54 /* After how many executions watchdog should assume lock up */
  55 #define MFC_WATCHDOG_CNT        10
  56 #define MFC_NO_INSTANCE_SET     -1
  57 #define MFC_ENC_CAP_PLANE_COUNT 1
  58 #define MFC_ENC_OUT_PLANE_COUNT 2
  59 #define STUFF_BYTE              4
  60 #define MFC_MAX_CTRLS           128
  61 
  62 #define S5P_MFC_CODEC_NONE              -1
  63 #define S5P_MFC_CODEC_H264_DEC          0
  64 #define S5P_MFC_CODEC_H264_MVC_DEC      1
  65 #define S5P_MFC_CODEC_VC1_DEC           2
  66 #define S5P_MFC_CODEC_MPEG4_DEC         3
  67 #define S5P_MFC_CODEC_MPEG2_DEC         4
  68 #define S5P_MFC_CODEC_H263_DEC          5
  69 #define S5P_MFC_CODEC_VC1RCV_DEC        6
  70 #define S5P_MFC_CODEC_VP8_DEC           7
  71 #define S5P_MFC_CODEC_HEVC_DEC          17
  72 #define S5P_MFC_CODEC_VP9_DEC           18
  73 
  74 #define S5P_MFC_CODEC_H264_ENC          20
  75 #define S5P_MFC_CODEC_H264_MVC_ENC      21
  76 #define S5P_MFC_CODEC_MPEG4_ENC         22
  77 #define S5P_MFC_CODEC_H263_ENC          23
  78 #define S5P_MFC_CODEC_VP8_ENC           24
  79 #define S5P_MFC_CODEC_HEVC_ENC          26
  80 
  81 #define S5P_MFC_R2H_CMD_EMPTY                   0
  82 #define S5P_MFC_R2H_CMD_SYS_INIT_RET            1
  83 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET       2
  84 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET            3
  85 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET        4
  86 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET      6
  87 #define S5P_MFC_R2H_CMD_SLEEP_RET               7
  88 #define S5P_MFC_R2H_CMD_WAKEUP_RET              8
  89 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET        9
  90 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET           10
  91 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET           11
  92 #define S5P_MFC_R2H_CMD_FW_STATUS_RET           12
  93 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET          13
  94 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET          14
  95 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET          15
  96 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET      16
  97 #define S5P_MFC_R2H_CMD_ERR_RET                 32
  98 
  99 #define MFC_MAX_CLOCKS          4
 100 
 101 #define mfc_read(dev, offset)           readl(dev->regs_base + (offset))
 102 #define mfc_write(dev, data, offset)    writel((data), dev->regs_base + \
 103                                                                 (offset))
 104 
 105 /**
 106  * enum s5p_mfc_fmt_type - type of the pixelformat
 107  */
 108 enum s5p_mfc_fmt_type {
 109         MFC_FMT_DEC,
 110         MFC_FMT_ENC,
 111         MFC_FMT_RAW,
 112 };
 113 
 114 /**
 115  * enum s5p_mfc_inst_type - The type of an MFC instance.
 116  */
 117 enum s5p_mfc_inst_type {
 118         MFCINST_INVALID,
 119         MFCINST_DECODER,
 120         MFCINST_ENCODER,
 121 };
 122 
 123 /**
 124  * enum s5p_mfc_inst_state - The state of an MFC instance.
 125  */
 126 enum s5p_mfc_inst_state {
 127         MFCINST_FREE = 0,
 128         MFCINST_INIT = 100,
 129         MFCINST_GOT_INST,
 130         MFCINST_HEAD_PARSED,
 131         MFCINST_HEAD_PRODUCED,
 132         MFCINST_BUFS_SET,
 133         MFCINST_RUNNING,
 134         MFCINST_FINISHING,
 135         MFCINST_FINISHED,
 136         MFCINST_RETURN_INST,
 137         MFCINST_ERROR,
 138         MFCINST_ABORT,
 139         MFCINST_FLUSH,
 140         MFCINST_RES_CHANGE_INIT,
 141         MFCINST_RES_CHANGE_FLUSH,
 142         MFCINST_RES_CHANGE_END,
 143 };
 144 
 145 /**
 146  * enum s5p_mfc_queue_state - The state of buffer queue.
 147  */
 148 enum s5p_mfc_queue_state {
 149         QUEUE_FREE,
 150         QUEUE_BUFS_REQUESTED,
 151         QUEUE_BUFS_QUERIED,
 152         QUEUE_BUFS_MMAPED,
 153 };
 154 
 155 /**
 156  * enum s5p_mfc_decode_arg - type of frame decoding
 157  */
 158 enum s5p_mfc_decode_arg {
 159         MFC_DEC_FRAME,
 160         MFC_DEC_LAST_FRAME,
 161         MFC_DEC_RES_CHANGE,
 162 };
 163 
 164 enum s5p_mfc_fw_ver {
 165         MFC_FW_V1,
 166         MFC_FW_V2,
 167 };
 168 
 169 #define MFC_BUF_FLAG_USED       (1 << 0)
 170 #define MFC_BUF_FLAG_EOS        (1 << 1)
 171 
 172 struct s5p_mfc_ctx;
 173 
 174 /**
 175  * struct s5p_mfc_buf - MFC buffer
 176  */
 177 struct s5p_mfc_buf {
 178         struct vb2_v4l2_buffer *b;
 179         struct list_head list;
 180         union {
 181                 struct {
 182                         size_t luma;
 183                         size_t chroma;
 184                 } raw;
 185                 size_t stream;
 186         } cookie;
 187         int flags;
 188 };
 189 
 190 /**
 191  * struct s5p_mfc_pm - power management data structure
 192  */
 193 struct s5p_mfc_pm {
 194         struct clk      *clock_gate;
 195         const char * const *clk_names;
 196         struct clk      *clocks[MFC_MAX_CLOCKS];
 197         int             num_clocks;
 198         bool            use_clock_gating;
 199 
 200         struct device   *device;
 201 };
 202 
 203 struct s5p_mfc_buf_size_v5 {
 204         unsigned int h264_ctx;
 205         unsigned int non_h264_ctx;
 206         unsigned int dsc;
 207         unsigned int shm;
 208 };
 209 
 210 struct s5p_mfc_buf_size_v6 {
 211         unsigned int dev_ctx;
 212         unsigned int h264_dec_ctx;
 213         unsigned int other_dec_ctx;
 214         unsigned int h264_enc_ctx;
 215         unsigned int hevc_enc_ctx;
 216         unsigned int other_enc_ctx;
 217 };
 218 
 219 struct s5p_mfc_buf_size {
 220         unsigned int fw;
 221         unsigned int cpb;
 222         void *priv;
 223 };
 224 
 225 struct s5p_mfc_variant {
 226         unsigned int version;
 227         unsigned int port_num;
 228         u32 version_bit;
 229         struct s5p_mfc_buf_size *buf_size;
 230         char    *fw_name[MFC_FW_MAX_VERSIONS];
 231         const char      *clk_names[MFC_MAX_CLOCKS];
 232         int             num_clocks;
 233         bool            use_clock_gating;
 234 };
 235 
 236 /**
 237  * struct s5p_mfc_priv_buf - represents internal used buffer
 238  * @ofs:                offset of each buffer, will be used for MFC
 239  * @virt:               kernel virtual address, only valid when the
 240  *                      buffer accessed by driver
 241  * @dma:                DMA address, only valid when kernel DMA API used
 242  * @size:               size of the buffer
 243  * @ctx:                memory context (bank) used for this allocation
 244  */
 245 struct s5p_mfc_priv_buf {
 246         unsigned long   ofs;
 247         void            *virt;
 248         dma_addr_t      dma;
 249         size_t          size;
 250         unsigned int    ctx;
 251 };
 252 
 253 /**
 254  * struct s5p_mfc_dev - The struct containing driver internal parameters.
 255  *
 256  * @v4l2_dev:           v4l2_device
 257  * @vfd_dec:            video device for decoding
 258  * @vfd_enc:            video device for encoding
 259  * @plat_dev:           platform device
 260  * @mem_dev[]:          child devices of the memory banks
 261  * @regs_base:          base address of the MFC hw registers
 262  * @irq:                irq resource
 263  * @dec_ctrl_handler:   control framework handler for decoding
 264  * @enc_ctrl_handler:   control framework handler for encoding
 265  * @pm:                 power management control
 266  * @variant:            MFC hardware variant information
 267  * @num_inst:           counter of active MFC instances
 268  * @irqlock:            lock for operations on videobuf2 queues
 269  * @condlock:           lock for changing/checking if a context is ready to be
 270  *                      processed
 271  * @mfc_mutex:          lock for video_device
 272  * @int_cond:           variable used by the waitqueue
 273  * @int_type:           type of last interrupt
 274  * @int_err:            error number for last interrupt
 275  * @queue:              waitqueue for waiting for completion of device commands
 276  * @fw_size:            size of firmware
 277  * @fw_virt_addr:       virtual firmware address
 278  * @dma_base[]:         address of the beginning of memory banks
 279  * @hw_lock:            used for hardware locking
 280  * @ctx:                array of driver contexts
 281  * @curr_ctx:           number of the currently running context
 282  * @ctx_work_bits:      used to mark which contexts are waiting for hardware
 283  * @watchdog_cnt:       counter for the watchdog
 284  * @watchdog_workqueue: workqueue for the watchdog
 285  * @watchdog_work:      worker for the watchdog
 286  * @enter_suspend:      flag set when entering suspend
 287  * @ctx_buf:            common context memory (MFCv6)
 288  * @warn_start:         hardware error code from which warnings start
 289  * @mfc_ops:            ops structure holding HW operation function pointers
 290  * @mfc_cmds:           cmd structure holding HW commands function pointers
 291  * @mfc_regs:           structure holding MFC registers
 292  * @fw_ver:             loaded firmware sub-version
 293  * @fw_get_done         flag set when request_firmware() is complete and
 294  *                      copied into fw_buf
 295  * risc_on:             flag indicates RISC is on or off
 296  *
 297  */
 298 struct s5p_mfc_dev {
 299         struct v4l2_device      v4l2_dev;
 300         struct video_device     *vfd_dec;
 301         struct video_device     *vfd_enc;
 302         struct platform_device  *plat_dev;
 303         struct device           *mem_dev[BANK_CTX_NUM];
 304         void __iomem            *regs_base;
 305         int                     irq;
 306         struct v4l2_ctrl_handler dec_ctrl_handler;
 307         struct v4l2_ctrl_handler enc_ctrl_handler;
 308         struct s5p_mfc_pm       pm;
 309         const struct s5p_mfc_variant    *variant;
 310         int num_inst;
 311         spinlock_t irqlock;     /* lock when operating on context */
 312         spinlock_t condlock;    /* lock when changing/checking if a context is
 313                                         ready to be processed */
 314         struct mutex mfc_mutex; /* video_device lock */
 315         int int_cond;
 316         int int_type;
 317         unsigned int int_err;
 318         wait_queue_head_t queue;
 319         struct s5p_mfc_priv_buf fw_buf;
 320         size_t mem_size;
 321         dma_addr_t mem_base;
 322         unsigned long *mem_bitmap;
 323         void *mem_virt;
 324         dma_addr_t dma_base[BANK_CTX_NUM];
 325         unsigned long hw_lock;
 326         struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
 327         int curr_ctx;
 328         unsigned long ctx_work_bits;
 329         atomic_t watchdog_cnt;
 330         struct timer_list watchdog_timer;
 331         struct workqueue_struct *watchdog_workqueue;
 332         struct work_struct watchdog_work;
 333         unsigned long enter_suspend;
 334 
 335         struct s5p_mfc_priv_buf ctx_buf;
 336         int warn_start;
 337         struct s5p_mfc_hw_ops *mfc_ops;
 338         struct s5p_mfc_hw_cmds *mfc_cmds;
 339         const struct s5p_mfc_regs *mfc_regs;
 340         enum s5p_mfc_fw_ver fw_ver;
 341         bool fw_get_done;
 342         bool risc_on; /* indicates if RISC is on or off */
 343 };
 344 
 345 /**
 346  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
 347  */
 348 struct s5p_mfc_h264_enc_params {
 349         enum v4l2_mpeg_video_h264_profile profile;
 350         enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
 351         s8 loop_filter_alpha;
 352         s8 loop_filter_beta;
 353         enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
 354         u8 max_ref_pic;
 355         u8 num_ref_pic_4p;
 356         int _8x8_transform;
 357         int rc_mb_dark;
 358         int rc_mb_smooth;
 359         int rc_mb_static;
 360         int rc_mb_activity;
 361         int vui_sar;
 362         u8 vui_sar_idc;
 363         u16 vui_ext_sar_width;
 364         u16 vui_ext_sar_height;
 365         int open_gop;
 366         u16 open_gop_size;
 367         u8 rc_frame_qp;
 368         u8 rc_min_qp;
 369         u8 rc_max_qp;
 370         u8 rc_p_frame_qp;
 371         u8 rc_b_frame_qp;
 372         enum v4l2_mpeg_video_h264_level level_v4l2;
 373         int level;
 374         u16 cpb_size;
 375         int interlace;
 376         u8 hier_qp;
 377         u8 hier_qp_type;
 378         u8 hier_qp_layer;
 379         u8 hier_qp_layer_qp[7];
 380         u8 sei_frame_packing;
 381         u8 sei_fp_curr_frame_0;
 382         u8 sei_fp_arrangement_type;
 383 
 384         u8 fmo;
 385         u8 fmo_map_type;
 386         u8 fmo_slice_grp;
 387         u8 fmo_chg_dir;
 388         u32 fmo_chg_rate;
 389         u32 fmo_run_len[4];
 390         u8 aso;
 391         u32 aso_slice_order[8];
 392 };
 393 
 394 /**
 395  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
 396  */
 397 struct s5p_mfc_mpeg4_enc_params {
 398         /* MPEG4 Only */
 399         enum v4l2_mpeg_video_mpeg4_profile profile;
 400         int quarter_pixel;
 401         /* Common for MPEG4, H263 */
 402         u16 vop_time_res;
 403         u16 vop_frm_delta;
 404         u8 rc_frame_qp;
 405         u8 rc_min_qp;
 406         u8 rc_max_qp;
 407         u8 rc_p_frame_qp;
 408         u8 rc_b_frame_qp;
 409         enum v4l2_mpeg_video_mpeg4_level level_v4l2;
 410         int level;
 411 };
 412 
 413 /**
 414  * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
 415  */
 416 struct s5p_mfc_vp8_enc_params {
 417         u8 imd_4x4;
 418         enum v4l2_vp8_num_partitions num_partitions;
 419         enum v4l2_vp8_num_ref_frames num_ref;
 420         u8 filter_level;
 421         u8 filter_sharpness;
 422         u32 golden_frame_ref_period;
 423         enum v4l2_vp8_golden_frame_sel golden_frame_sel;
 424         u8 hier_layer;
 425         u8 hier_layer_qp[3];
 426         u8 rc_min_qp;
 427         u8 rc_max_qp;
 428         u8 rc_frame_qp;
 429         u8 rc_p_frame_qp;
 430         u8 profile;
 431 };
 432 
 433 struct s5p_mfc_hevc_enc_params {
 434         enum v4l2_mpeg_video_hevc_profile profile;
 435         int level;
 436         enum v4l2_mpeg_video_h264_level level_v4l2;
 437         u8 tier;
 438         u32 rc_framerate;
 439         u8 rc_min_qp;
 440         u8 rc_max_qp;
 441         u8 rc_lcu_dark;
 442         u8 rc_lcu_smooth;
 443         u8 rc_lcu_static;
 444         u8 rc_lcu_activity;
 445         u8 rc_frame_qp;
 446         u8 rc_p_frame_qp;
 447         u8 rc_b_frame_qp;
 448         u8 max_partition_depth;
 449         u8 num_refs_for_p;
 450         u8 refreshtype;
 451         u16 refreshperiod;
 452         s32 lf_beta_offset_div2;
 453         s32 lf_tc_offset_div2;
 454         u8 loopfilter;
 455         u8 loopfilter_disable;
 456         u8 loopfilter_across;
 457         u8 nal_control_length_filed;
 458         u8 nal_control_user_ref;
 459         u8 nal_control_store_ref;
 460         u8 const_intra_period_enable;
 461         u8 lossless_cu_enable;
 462         u8 wavefront_enable;
 463         u8 enable_ltr;
 464         u8 hier_qp_enable;
 465         enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
 466         u8 num_hier_layer;
 467         u8 hier_qp_layer[7];
 468         u32 hier_bit_layer[7];
 469         u8 sign_data_hiding;
 470         u8 general_pb_enable;
 471         u8 temporal_id_enable;
 472         u8 strong_intra_smooth;
 473         u8 intra_pu_split_disable;
 474         u8 tmv_prediction_disable;
 475         u8 max_num_merge_mv;
 476         u8 eco_mode_enable;
 477         u8 encoding_nostartcode_enable;
 478         u8 size_of_length_field;
 479         u8 prepend_sps_pps_to_idr;
 480 };
 481 
 482 /**
 483  * struct s5p_mfc_enc_params - general encoding parameters
 484  */
 485 struct s5p_mfc_enc_params {
 486         u16 width;
 487         u16 height;
 488         u32 mv_h_range;
 489         u32 mv_v_range;
 490 
 491         u16 gop_size;
 492         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 493         u16 slice_mb;
 494         u32 slice_bit;
 495         u16 intra_refresh_mb;
 496         int pad;
 497         u8 pad_luma;
 498         u8 pad_cb;
 499         u8 pad_cr;
 500         int rc_frame;
 501         int rc_mb;
 502         u32 rc_bitrate;
 503         u16 rc_reaction_coeff;
 504         u16 vbv_size;
 505         u32 vbv_delay;
 506 
 507         enum v4l2_mpeg_video_header_mode seq_hdr_mode;
 508         enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
 509         int fixed_target_bit;
 510 
 511         u8 num_b_frame;
 512         u32 rc_framerate_num;
 513         u32 rc_framerate_denom;
 514 
 515         struct {
 516                 struct s5p_mfc_h264_enc_params h264;
 517                 struct s5p_mfc_mpeg4_enc_params mpeg4;
 518                 struct s5p_mfc_vp8_enc_params vp8;
 519                 struct s5p_mfc_hevc_enc_params hevc;
 520         } codec;
 521 
 522 };
 523 
 524 /**
 525  * struct s5p_mfc_codec_ops - codec ops, used by encoding
 526  */
 527 struct s5p_mfc_codec_ops {
 528         /* initialization routines */
 529         int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
 530         int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
 531         /* execution routines */
 532         int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
 533         int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
 534 };
 535 
 536 #define call_cop(c, op, args...)                                \
 537         (((c)->c_ops->op) ?                                     \
 538                 ((c)->c_ops->op(args)) : 0)
 539 
 540 /**
 541  * struct s5p_mfc_ctx - This struct contains the instance context
 542  *
 543  * @dev:                pointer to the s5p_mfc_dev of the device
 544  * @fh:                 struct v4l2_fh
 545  * @num:                number of the context that this structure describes
 546  * @int_cond:           variable used by the waitqueue
 547  * @int_type:           type of the last interrupt
 548  * @int_err:            error number received from MFC hw in the interrupt
 549  * @queue:              waitqueue that can be used to wait for this context to
 550  *                      finish
 551  * @src_fmt:            source pixelformat information
 552  * @dst_fmt:            destination pixelformat information
 553  * @vq_src:             vb2 queue for source buffers
 554  * @vq_dst:             vb2 queue for destination buffers
 555  * @src_queue:          driver internal queue for source buffers
 556  * @dst_queue:          driver internal queue for destination buffers
 557  * @src_queue_cnt:      number of buffers queued on the source internal queue
 558  * @dst_queue_cnt:      number of buffers queued on the dest internal queue
 559  * @type:               type of the instance - decoder or encoder
 560  * @state:              state of the context
 561  * @inst_no:            number of hw instance associated with the context
 562  * @img_width:          width of the image that is decoded or encoded
 563  * @img_height:         height of the image that is decoded or encoded
 564  * @buf_width:          width of the buffer for processed image
 565  * @buf_height:         height of the buffer for processed image
 566  * @luma_size:          size of a luma plane
 567  * @chroma_size:        size of a chroma plane
 568  * @mv_size:            size of a motion vectors buffer
 569  * @consumed_stream:    number of bytes that have been used so far from the
 570  *                      decoding buffer
 571  * @dpb_flush_flag:     flag used to indicate that a DPB buffers are being
 572  *                      flushed
 573  * @head_processed:     flag mentioning whether the header data is processed
 574  *                      completely or not
 575  * @bank1:              handle to memory allocated for temporary buffers from
 576  *                      memory bank 1
 577  * @bank2:              handle to memory allocated for temporary buffers from
 578  *                      memory bank 2
 579  * @capture_state:      state of the capture buffers queue
 580  * @output_state:       state of the output buffers queue
 581  * @src_bufs:           information on allocated source buffers
 582  * @dst_bufs:           information on allocated destination buffers
 583  * @sequence:           counter for the sequence number for v4l2
 584  * @dec_dst_flag:       flags for buffers queued in the hardware
 585  * @dec_src_buf_size:   size of the buffer for source buffers in decoding
 586  * @codec_mode:         number of codec mode used by MFC hw
 587  * @slice_interface:    slice interface flag
 588  * @loop_filter_mpeg4:  loop filter for MPEG4 flag
 589  * @display_delay:      value of the display delay for H264
 590  * @display_delay_enable:       display delay for H264 enable flag
 591  * @after_packed_pb:    flag used to track buffer when stream is in
 592  *                      Packed PB format
 593  * @sei_fp_parse:       enable/disable parsing of frame packing SEI information
 594  * @dpb_count:          count of the DPB buffers required by MFC hw
 595  * @total_dpb_count:    count of DPB buffers with additional buffers
 596  *                      requested by the application
 597  * @ctx:                context buffer information
 598  * @dsc:                descriptor buffer information
 599  * @shm:                shared memory buffer information
 600  * @mv_count:           number of MV buffers allocated for decoding
 601  * @enc_params:         encoding parameters for MFC
 602  * @enc_dst_buf_size:   size of the buffers for encoder output
 603  * @luma_dpb_size:      dpb buffer size for luma
 604  * @chroma_dpb_size:    dpb buffer size for chroma
 605  * @me_buffer_size:     size of the motion estimation buffer
 606  * @tmv_buffer_size:    size of temporal predictor motion vector buffer
 607  * @frame_type:         used to force the type of the next encoded frame
 608  * @ref_queue:          list of the reference buffers for encoding
 609  * @ref_queue_cnt:      number of the buffers in the reference list
 610  * @c_ops:              ops for encoding
 611  * @ctrls:              array of controls, used when adding controls to the
 612  *                      v4l2 control framework
 613  * @ctrl_handler:       handler for v4l2 framework
 614  */
 615 struct s5p_mfc_ctx {
 616         struct s5p_mfc_dev *dev;
 617         struct v4l2_fh fh;
 618 
 619         int num;
 620 
 621         int int_cond;
 622         int int_type;
 623         unsigned int int_err;
 624         wait_queue_head_t queue;
 625 
 626         struct s5p_mfc_fmt *src_fmt;
 627         struct s5p_mfc_fmt *dst_fmt;
 628 
 629         struct vb2_queue vq_src;
 630         struct vb2_queue vq_dst;
 631 
 632         struct list_head src_queue;
 633         struct list_head dst_queue;
 634 
 635         unsigned int src_queue_cnt;
 636         unsigned int dst_queue_cnt;
 637 
 638         enum s5p_mfc_inst_type type;
 639         enum s5p_mfc_inst_state state;
 640         int inst_no;
 641 
 642         /* Image parameters */
 643         int img_width;
 644         int img_height;
 645         int buf_width;
 646         int buf_height;
 647 
 648         int luma_size;
 649         int chroma_size;
 650         int mv_size;
 651 
 652         unsigned long consumed_stream;
 653 
 654         unsigned int dpb_flush_flag;
 655         unsigned int head_processed;
 656 
 657         struct s5p_mfc_priv_buf bank1;
 658         struct s5p_mfc_priv_buf bank2;
 659 
 660         enum s5p_mfc_queue_state capture_state;
 661         enum s5p_mfc_queue_state output_state;
 662 
 663         struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
 664         int src_bufs_cnt;
 665         struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
 666         int dst_bufs_cnt;
 667 
 668         unsigned int sequence;
 669         unsigned long dec_dst_flag;
 670         size_t dec_src_buf_size;
 671 
 672         /* Control values */
 673         int codec_mode;
 674         int slice_interface;
 675         int loop_filter_mpeg4;
 676         int display_delay;
 677         int display_delay_enable;
 678         int after_packed_pb;
 679         int sei_fp_parse;
 680 
 681         int pb_count;
 682         int total_dpb_count;
 683         int mv_count;
 684         /* Buffers */
 685         struct s5p_mfc_priv_buf ctx;
 686         struct s5p_mfc_priv_buf dsc;
 687         struct s5p_mfc_priv_buf shm;
 688 
 689         struct s5p_mfc_enc_params enc_params;
 690 
 691         size_t enc_dst_buf_size;
 692         size_t luma_dpb_size;
 693         size_t chroma_dpb_size;
 694         size_t me_buffer_size;
 695         size_t tmv_buffer_size;
 696 
 697         enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
 698 
 699         struct list_head ref_queue;
 700         unsigned int ref_queue_cnt;
 701 
 702         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 703         union {
 704                 unsigned int mb;
 705                 unsigned int bits;
 706         } slice_size;
 707 
 708         const struct s5p_mfc_codec_ops *c_ops;
 709 
 710         struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
 711         struct v4l2_ctrl_handler ctrl_handler;
 712         unsigned int frame_tag;
 713         size_t scratch_buf_size;
 714 };
 715 
 716 /*
 717  * struct s5p_mfc_fmt - structure used to store information about pixelformats
 718  *                      used by the MFC
 719  */
 720 struct s5p_mfc_fmt {
 721         u32 fourcc;
 722         u32 codec_mode;
 723         enum s5p_mfc_fmt_type type;
 724         u32 num_planes;
 725         u32 versions;
 726 };
 727 
 728 /**
 729  * struct mfc_control - structure used to store information about MFC controls
 730  *                      it is used to initialize the control framework.
 731  */
 732 struct mfc_control {
 733         __u32                   id;
 734         enum v4l2_ctrl_type     type;
 735         __u8                    name[32];  /* Whatever */
 736         __s32                   minimum;   /* Note signedness */
 737         __s32                   maximum;
 738         __s32                   step;
 739         __u32                   menu_skip_mask;
 740         __s32                   default_value;
 741         __u32                   flags;
 742         __u32                   reserved[2];
 743         __u8                    is_volatile;
 744 };
 745 
 746 /* Macro for making hardware specific calls */
 747 #define s5p_mfc_hw_call(f, op, args...) \
 748         ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
 749 
 750 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
 751 #define ctrl_to_ctx(__ctrl) \
 752         container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
 753 
 754 void clear_work_bit(struct s5p_mfc_ctx *ctx);
 755 void set_work_bit(struct s5p_mfc_ctx *ctx);
 756 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 757 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 758 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
 759 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
 760 
 761 #define HAS_PORTNUM(dev)        (dev ? (dev->variant ? \
 762                                 (dev->variant->port_num ? 1 : 0) : 0) : 0)
 763 #define IS_TWOPORT(dev)         (dev->variant->port_num == 2 ? 1 : 0)
 764 #define IS_MFCV6_PLUS(dev)      (dev->variant->version >= 0x60 ? 1 : 0)
 765 #define IS_MFCV7_PLUS(dev)      (dev->variant->version >= 0x70 ? 1 : 0)
 766 #define IS_MFCV8_PLUS(dev)      (dev->variant->version >= 0x80 ? 1 : 0)
 767 #define IS_MFCV10(dev)          (dev->variant->version >= 0xA0 ? 1 : 0)
 768 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
 769 
 770 #define MFC_V5_BIT      BIT(0)
 771 #define MFC_V6_BIT      BIT(1)
 772 #define MFC_V7_BIT      BIT(2)
 773 #define MFC_V8_BIT      BIT(3)
 774 #define MFC_V10_BIT     BIT(5)
 775 
 776 #define MFC_V5PLUS_BITS         (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
 777                                         MFC_V8_BIT | MFC_V10_BIT)
 778 #define MFC_V6PLUS_BITS         (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
 779                                         MFC_V10_BIT)
 780 #define MFC_V7PLUS_BITS         (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
 781 
 782 #endif /* S5P_MFC_COMMON_H_ */