This source file includes following definitions.
- verve_write_byte
- verve_read_byte
- initGPIO
- uninitGPIO
- afe_write_byte
- afe_read_byte
- cx231xx_afe_init_super_block
- cx231xx_afe_init_channels
- cx231xx_afe_setup_AFE_for_baseband
- cx231xx_afe_set_input_mux
- cx231xx_afe_set_mode
- cx231xx_afe_update_power_control
- cx231xx_afe_adjust_ref_count
- vid_blk_write_byte
- vid_blk_read_byte
- vid_blk_write_word
- vid_blk_read_word
- cx231xx_check_fw
- cx231xx_set_video_input_mux
- cx231xx_set_decoder_video_input
- cx231xx_enable656
- cx231xx_disable656
- cx231xx_do_mode_ctrl_overrides
- cx231xx_unmute_audio
- stopAudioFirmware
- restartAudioFirmware
- cx231xx_set_audio_input
- cx231xx_set_audio_decoder_input
- cx231xx_init_ctrl_pin_status
- cx231xx_set_agc_analog_digital_mux_select
- cx231xx_enable_i2c_port_3
- update_HH_register_after_set_DIF
- cx231xx_dump_HH_reg
- cx231xx_dump_SC_reg
- cx231xx_Setup_AFE_for_LowIF
- cx231xx_set_Colibri_For_LowIF
- cx231xx_Get_Colibri_CarrierOffset
- cx231xx_set_DIF_bandpass
- cx231xx_dif_configure_C2HH_for_low_IF
- cx231xx_dif_set_standard
- cx231xx_tuner_pre_channel_change
- cx231xx_tuner_post_channel_change
- cx231xx_i2s_blk_initialize
- cx231xx_i2s_blk_update_power_control
- cx231xx_i2s_blk_set_audio_input
- cx231xx_set_power_mode
- cx231xx_power_suspend
- cx231xx_start_stream
- cx231xx_stop_stream
- cx231xx_initialize_stream_xfer
- cx231xx_capture_start
- cx231xx_set_gpio_bit
- cx231xx_get_gpio_bit
- cx231xx_set_gpio_direction
- cx231xx_set_gpio_value
- cx231xx_gpio_i2c_start
- cx231xx_gpio_i2c_end
- cx231xx_gpio_i2c_write_byte
- cx231xx_gpio_i2c_read_byte
- cx231xx_gpio_i2c_read_ack
- cx231xx_gpio_i2c_write_ack
- cx231xx_gpio_i2c_write_nak
- cx231xx_gpio_i2c_read
- cx231xx_gpio_i2c_write
1
2
3
4
5
6
7
8
9
10
11
12
13 #include "cx231xx.h"
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/bitmap.h>
19 #include <linux/i2c.h>
20 #include <linux/mm.h>
21 #include <linux/mutex.h>
22 #include <media/tuner.h>
23
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26
27 #include "cx231xx-dif.h"
28
29 #define TUNER_MODE_FM_RADIO 0
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
47 {
48 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
49 saddr, 1, data, 1);
50 }
51
52 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
53 {
54 int status;
55 u32 temp = 0;
56
57 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
58 saddr, 1, &temp, 1);
59 *data = (u8) temp;
60 return status;
61 }
62 void initGPIO(struct cx231xx *dev)
63 {
64 u32 _gpio_direction = 0;
65 u32 value = 0;
66 u8 val = 0;
67
68 _gpio_direction = _gpio_direction & 0xFC0003FF;
69 _gpio_direction = _gpio_direction | 0x03FDFC00;
70 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
71
72 verve_read_byte(dev, 0x07, &val);
73 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
74 verve_write_byte(dev, 0x07, 0xF4);
75 verve_read_byte(dev, 0x07, &val);
76 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
77
78 cx231xx_capture_start(dev, 1, Vbi);
79
80 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
81 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
82
83 }
84 void uninitGPIO(struct cx231xx *dev)
85 {
86 u8 value[4] = { 0, 0, 0, 0 };
87
88 cx231xx_capture_start(dev, 0, Vbi);
89 verve_write_byte(dev, 0x07, 0x14);
90 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
91 0x68, value, 4);
92 }
93
94
95
96
97
98 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
99 {
100 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
101 saddr, 2, data, 1);
102 }
103
104 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
105 {
106 int status;
107 u32 temp = 0;
108
109 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
110 saddr, 2, &temp, 1);
111 *data = (u8) temp;
112 return status;
113 }
114
115 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
116 {
117 int status = 0;
118 u8 temp = 0;
119 u8 afe_power_status = 0;
120 int i = 0;
121
122
123 temp = (u8) (ref_count & 0xff);
124 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
125 if (status < 0)
126 return status;
127
128 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
129 if (status < 0)
130 return status;
131
132 temp = (u8) ((ref_count & 0x300) >> 8);
133 temp |= 0x40;
134 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
135 if (status < 0)
136 return status;
137
138 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
139 if (status < 0)
140 return status;
141
142
143 while (afe_power_status != 0x18) {
144 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
145 if (status < 0) {
146 dev_dbg(dev->dev,
147 "%s: Init Super Block failed in send cmd\n",
148 __func__);
149 break;
150 }
151
152 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
153 afe_power_status &= 0xff;
154 if (status < 0) {
155 dev_dbg(dev->dev,
156 "%s: Init Super Block failed in receive cmd\n",
157 __func__);
158 break;
159 }
160 i++;
161 if (i == 10) {
162 dev_dbg(dev->dev,
163 "%s: Init Super Block force break in loop !!!!\n",
164 __func__);
165 status = -1;
166 break;
167 }
168 }
169
170 if (status < 0)
171 return status;
172
173
174 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
175 if (status < 0)
176 return status;
177
178 msleep(5);
179
180
181 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
182
183 return status;
184 }
185
186 int cx231xx_afe_init_channels(struct cx231xx *dev)
187 {
188 int status = 0;
189
190
191 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
192 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
193 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
194
195
196 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
197
198
199 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
200 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
201 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
202
203
204 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
205 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
206 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
207 msleep(5);
208
209
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
213
214
215 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
216 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
217 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
218
219
220 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
221 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
222 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
223 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
224 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
225 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
226
227
228 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
229 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
230 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
231
232 return status;
233 }
234
235 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
236 {
237 u8 c_value = 0;
238 int status = 0;
239
240 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
241 c_value &= (~(0x50));
242 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
243
244 return status;
245 }
246
247
248
249
250
251
252
253
254
255
256 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
257 {
258 u8 ch1_setting = (u8) input_mux;
259 u8 ch2_setting = (u8) (input_mux >> 8);
260 u8 ch3_setting = (u8) (input_mux >> 16);
261 int status = 0;
262 u8 value = 0;
263
264 if (ch1_setting != 0) {
265 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
266 value &= ~INPUT_SEL_MASK;
267 value |= (ch1_setting - 1) << 4;
268 value &= 0xff;
269 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
270 }
271
272 if (ch2_setting != 0) {
273 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
274 value &= ~INPUT_SEL_MASK;
275 value |= (ch2_setting - 1) << 4;
276 value &= 0xff;
277 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
278 }
279
280
281
282 if (ch3_setting != 0) {
283 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
284 value &= ~INPUT_SEL_MASK;
285 value |= (ch3_setting - 1) << 4;
286 value &= 0xff;
287 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
288 }
289
290 return status;
291 }
292
293 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
294 {
295 int status = 0;
296
297
298
299
300
301
302 switch (mode) {
303 case AFE_MODE_LOW_IF:
304 cx231xx_Setup_AFE_for_LowIF(dev);
305 break;
306 case AFE_MODE_BASEBAND:
307 status = cx231xx_afe_setup_AFE_for_baseband(dev);
308 break;
309 case AFE_MODE_EU_HI_IF:
310
311 break;
312 case AFE_MODE_US_HI_IF:
313
314 break;
315 case AFE_MODE_JAPAN_HI_IF:
316
317 break;
318 }
319
320 if ((mode != dev->afe_mode) &&
321 (dev->video_input == CX231XX_VMUX_TELEVISION))
322 status = cx231xx_afe_adjust_ref_count(dev,
323 CX231XX_VMUX_TELEVISION);
324
325 dev->afe_mode = mode;
326
327 return status;
328 }
329
330 int cx231xx_afe_update_power_control(struct cx231xx *dev,
331 enum AV_MODE avmode)
332 {
333 u8 afe_power_status = 0;
334 int status = 0;
335
336 switch (dev->model) {
337 case CX231XX_BOARD_CNXT_CARRAERA:
338 case CX231XX_BOARD_CNXT_RDE_250:
339 case CX231XX_BOARD_CNXT_SHELBY:
340 case CX231XX_BOARD_CNXT_RDU_250:
341 case CX231XX_BOARD_CNXT_RDE_253S:
342 case CX231XX_BOARD_CNXT_RDU_253S:
343 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
344 case CX231XX_BOARD_HAUPPAUGE_EXETER:
345 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
346 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
347 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
348 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
349 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
350 case CX231XX_BOARD_OTG102:
351 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
352 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
353 FLD_PWRDN_ENABLE_PLL)) {
354 status = afe_write_byte(dev, SUP_BLK_PWRDN,
355 FLD_PWRDN_TUNING_BIAS |
356 FLD_PWRDN_ENABLE_PLL);
357 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
358 &afe_power_status);
359 if (status < 0)
360 break;
361 }
362
363 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
364 0x00);
365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
366 0x00);
367 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
368 0x00);
369 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
370 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
371 0x70);
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
373 0x70);
374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
375 0x70);
376
377 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
378 &afe_power_status);
379 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
380 FLD_PWRDN_PD_BIAS |
381 FLD_PWRDN_PD_TUNECK;
382 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
383 afe_power_status);
384 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
385 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
386 FLD_PWRDN_ENABLE_PLL)) {
387 status = afe_write_byte(dev, SUP_BLK_PWRDN,
388 FLD_PWRDN_TUNING_BIAS |
389 FLD_PWRDN_ENABLE_PLL);
390 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
391 &afe_power_status);
392 if (status < 0)
393 break;
394 }
395
396 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
397 0x00);
398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
399 0x00);
400 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
401 0x00);
402 } else {
403 dev_dbg(dev->dev, "Invalid AV mode input\n");
404 status = -1;
405 }
406 break;
407 default:
408 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
409 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
410 FLD_PWRDN_ENABLE_PLL)) {
411 status = afe_write_byte(dev, SUP_BLK_PWRDN,
412 FLD_PWRDN_TUNING_BIAS |
413 FLD_PWRDN_ENABLE_PLL);
414 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
415 &afe_power_status);
416 if (status < 0)
417 break;
418 }
419
420 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
421 0x40);
422 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
423 0x40);
424 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
425 0x00);
426 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
427 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
428 0x70);
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
430 0x70);
431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
432 0x70);
433
434 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
435 &afe_power_status);
436 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
437 FLD_PWRDN_PD_BIAS |
438 FLD_PWRDN_PD_TUNECK;
439 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
440 afe_power_status);
441 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
442 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
443 FLD_PWRDN_ENABLE_PLL)) {
444 status = afe_write_byte(dev, SUP_BLK_PWRDN,
445 FLD_PWRDN_TUNING_BIAS |
446 FLD_PWRDN_ENABLE_PLL);
447 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
448 &afe_power_status);
449 if (status < 0)
450 break;
451 }
452
453 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
454 0x00);
455 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
456 0x00);
457 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
458 0x40);
459 } else {
460 dev_dbg(dev->dev, "Invalid AV mode input\n");
461 status = -1;
462 }
463 }
464
465 return status;
466 }
467
468 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
469 {
470 u8 input_mode = 0;
471 u8 ntf_mode = 0;
472 int status = 0;
473
474 dev->video_input = video_input;
475
476 if (video_input == CX231XX_VMUX_TELEVISION) {
477 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
478 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
479 &ntf_mode);
480 } else {
481 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
482 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
483 &ntf_mode);
484 }
485
486 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
487
488 switch (input_mode) {
489 case SINGLE_ENDED:
490 dev->afe_ref_count = 0x23C;
491 break;
492 case LOW_IF:
493 dev->afe_ref_count = 0x24C;
494 break;
495 case EU_IF:
496 dev->afe_ref_count = 0x258;
497 break;
498 case US_IF:
499 dev->afe_ref_count = 0x260;
500 break;
501 default:
502 break;
503 }
504
505 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
506
507 return status;
508 }
509
510
511
512
513 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
514 {
515 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
516 saddr, 2, data, 1);
517 }
518
519 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
520 {
521 int status;
522 u32 temp = 0;
523
524 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
525 saddr, 2, &temp, 1);
526 *data = (u8) temp;
527 return status;
528 }
529
530 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
531 {
532 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
533 saddr, 2, data, 4);
534 }
535
536 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
537 {
538 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
539 saddr, 2, data, 4);
540 }
541 int cx231xx_check_fw(struct cx231xx *dev)
542 {
543 u8 temp = 0;
544 int status = 0;
545 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
546 if (status < 0)
547 return status;
548 else
549 return temp;
550
551 }
552
553 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
554 {
555 int status = 0;
556
557 switch (INPUT(input)->type) {
558 case CX231XX_VMUX_COMPOSITE1:
559 case CX231XX_VMUX_SVIDEO:
560 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
561 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
562
563 status = cx231xx_set_power_mode(dev,
564 POLARIS_AVMODE_ENXTERNAL_AV);
565 if (status < 0) {
566 dev_err(dev->dev,
567 "%s: Failed to set Power - errCode [%d]!\n",
568 __func__, status);
569 return status;
570 }
571 }
572 status = cx231xx_set_decoder_video_input(dev,
573 INPUT(input)->type,
574 INPUT(input)->vmux);
575 break;
576 case CX231XX_VMUX_TELEVISION:
577 case CX231XX_VMUX_CABLE:
578 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
579 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
580
581 status = cx231xx_set_power_mode(dev,
582 POLARIS_AVMODE_ANALOGT_TV);
583 if (status < 0) {
584 dev_err(dev->dev,
585 "%s: Failed to set Power - errCode [%d]!\n",
586 __func__, status);
587 return status;
588 }
589 }
590 if (dev->tuner_type == TUNER_NXP_TDA18271)
591 status = cx231xx_set_decoder_video_input(dev,
592 CX231XX_VMUX_TELEVISION,
593 INPUT(input)->vmux);
594 else
595 status = cx231xx_set_decoder_video_input(dev,
596 CX231XX_VMUX_COMPOSITE1,
597 INPUT(input)->vmux);
598
599 break;
600 default:
601 dev_err(dev->dev, "%s: Unknown Input %d !\n",
602 __func__, INPUT(input)->type);
603 break;
604 }
605
606
607 dev->video_input = input;
608
609 return status;
610 }
611
612 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
613 u8 pin_type, u8 input)
614 {
615 int status = 0;
616 u32 value = 0;
617
618 if (pin_type != dev->video_input) {
619 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
620 if (status < 0) {
621 dev_err(dev->dev,
622 "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n",
623 __func__, status);
624 return status;
625 }
626 }
627
628
629 status = cx231xx_afe_set_input_mux(dev, input);
630 if (status < 0) {
631 dev_err(dev->dev,
632 "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n",
633 __func__, status);
634 return status;
635 }
636
637 switch (pin_type) {
638 case CX231XX_VMUX_COMPOSITE1:
639 status = vid_blk_read_word(dev, AFE_CTRL, &value);
640 value |= (0 << 13) | (1 << 4);
641 value &= ~(1 << 5);
642
643
644 value &= (~(0x1ff8000));
645
646 value |= 0x1000000;
647 status = vid_blk_write_word(dev, AFE_CTRL, value);
648
649 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
650 value |= (1 << 7);
651 status = vid_blk_write_word(dev, OUT_CTRL1, value);
652
653
654 status = cx231xx_read_modify_write_i2c_dword(dev,
655 VID_BLK_I2C_ADDRESS,
656 OUT_CTRL1,
657 FLD_OUT_MODE,
658 dev->board.output_mode);
659
660
661 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
662 if (status < 0) {
663 dev_err(dev->dev,
664 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
665 __func__, status);
666 return status;
667 }
668
669
670 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
671
672
673 value |= FLD_VBI_GATE_EN;
674
675
676 value |= FLD_VGA_AUTO_EN;
677
678
679 status = vid_blk_write_word(dev, DFE_CTRL1, value);
680
681
682 status = cx231xx_read_modify_write_i2c_dword(dev,
683 VID_BLK_I2C_ADDRESS,
684 MODE_CTRL, FLD_ACFG_DIS,
685 cx231xx_set_field(FLD_ACFG_DIS, 1));
686
687
688 status = cx231xx_read_modify_write_i2c_dword(dev,
689 VID_BLK_I2C_ADDRESS,
690 MODE_CTRL, FLD_INPUT_MODE,
691 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
692 break;
693 case CX231XX_VMUX_SVIDEO:
694
695
696 status = vid_blk_read_word(dev, AFE_CTRL, &value);
697
698
699 value &= (~(0x1ff8000));
700
701
702 value |= 0x1000010;
703 status = vid_blk_write_word(dev, AFE_CTRL, value);
704
705
706 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
707 if (status < 0) {
708 dev_err(dev->dev,
709 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
710 __func__, status);
711 return status;
712 }
713
714
715 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
716
717
718 value |= FLD_VBI_GATE_EN;
719
720
721 value |= FLD_VGA_AUTO_EN;
722
723
724 status = vid_blk_write_word(dev, DFE_CTRL1, value);
725
726
727 status = cx231xx_read_modify_write_i2c_dword(dev,
728 VID_BLK_I2C_ADDRESS,
729 MODE_CTRL, FLD_ACFG_DIS,
730 cx231xx_set_field(FLD_ACFG_DIS, 1));
731
732
733 status = cx231xx_read_modify_write_i2c_dword(dev,
734 VID_BLK_I2C_ADDRESS,
735 MODE_CTRL,
736 FLD_INPUT_MODE,
737 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
738
739
740 status = vid_blk_read_word(dev, AFE_CTRL, &value);
741 value |= FLD_CHROMA_IN_SEL;
742
743
744
745
746 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
747
748 status = vid_blk_write_word(dev, AFE_CTRL, value);
749
750 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
751 break;
752 case CX231XX_VMUX_TELEVISION:
753 case CX231XX_VMUX_CABLE:
754 default:
755
756 if (dev->board.tuner_type == TUNER_XC5000) {
757
758
759 status = vid_blk_read_word(dev, AFE_CTRL, &value);
760 value |= (0 << 13) | (1 << 4);
761 value &= ~(1 << 5);
762
763
764 value &= (~(0x1FF8000));
765
766 value |= 0x1000000;
767 status = vid_blk_write_word(dev, AFE_CTRL, value);
768
769 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
770 value |= (1 << 7);
771 status = vid_blk_write_word(dev, OUT_CTRL1, value);
772
773
774 status = cx231xx_read_modify_write_i2c_dword(dev,
775 VID_BLK_I2C_ADDRESS,
776 OUT_CTRL1, FLD_OUT_MODE,
777 dev->board.output_mode);
778
779
780 status = cx231xx_dif_set_standard(dev,
781 DIF_USE_BASEBAND);
782 if (status < 0) {
783 dev_err(dev->dev,
784 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
785 __func__, status);
786 return status;
787 }
788
789
790 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
791
792
793 value |= FLD_VBI_GATE_EN;
794
795
796 value |= FLD_VGA_AUTO_EN;
797
798
799 status = vid_blk_write_word(dev, DFE_CTRL1, value);
800
801
802 status = cx231xx_read_modify_write_i2c_dword(dev,
803 VID_BLK_I2C_ADDRESS,
804 MODE_CTRL, FLD_ACFG_DIS,
805 cx231xx_set_field(FLD_ACFG_DIS, 1));
806
807
808 status = cx231xx_read_modify_write_i2c_dword(dev,
809 VID_BLK_I2C_ADDRESS,
810 MODE_CTRL, FLD_INPUT_MODE,
811 cx231xx_set_field(FLD_INPUT_MODE,
812 INPUT_MODE_CVBS_0));
813 } else {
814
815
816
817 status = cx231xx_dif_set_standard(dev, dev->norm);
818 if (status < 0) {
819 dev_err(dev->dev,
820 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
821 __func__, status);
822 return status;
823 }
824
825
826 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
827
828
829 value &= ~FLD_DIF_DIF_BYPASS;
830
831
832 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
833
834
835 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
836
837
838 value &= ~FLD_VBI_GATE_EN;
839
840
841
842 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
843
844
845 status = vid_blk_write_word(dev, DFE_CTRL1, value);
846
847
848 msleep(1);
849
850
851 value &= ~(FLD_VGA_AUTO_EN);
852
853
854 status = vid_blk_write_word(dev, DFE_CTRL1, value);
855
856
857 status = vid_blk_read_word(dev, PIN_CTRL, &value);
858 value |= (FLD_OEF_AGC_RF) |
859 (FLD_OEF_AGC_IFVGA) |
860 (FLD_OEF_AGC_IF);
861 status = vid_blk_write_word(dev, PIN_CTRL, value);
862
863
864 status = cx231xx_read_modify_write_i2c_dword(dev,
865 VID_BLK_I2C_ADDRESS,
866 OUT_CTRL1, FLD_OUT_MODE,
867 dev->board.output_mode);
868
869
870 status = cx231xx_read_modify_write_i2c_dword(dev,
871 VID_BLK_I2C_ADDRESS,
872 MODE_CTRL, FLD_ACFG_DIS,
873 cx231xx_set_field(FLD_ACFG_DIS, 1));
874
875
876 status = cx231xx_read_modify_write_i2c_dword(dev,
877 VID_BLK_I2C_ADDRESS,
878 MODE_CTRL, FLD_INPUT_MODE,
879 cx231xx_set_field(FLD_INPUT_MODE,
880 INPUT_MODE_CVBS_0));
881
882
883
884
885
886
887 status = vid_blk_read_word(dev, AFE_CTRL, &value);
888
889
890 value &= (~(FLD_FUNC_MODE));
891 value |= 0x800000;
892
893 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
894
895 status = vid_blk_write_word(dev, AFE_CTRL, value);
896
897 if (dev->tuner_type == TUNER_NXP_TDA18271) {
898 status = vid_blk_read_word(dev, PIN_CTRL,
899 &value);
900 status = vid_blk_write_word(dev, PIN_CTRL,
901 (value & 0xFFFFFFEF));
902 }
903
904 break;
905
906 }
907 break;
908 }
909
910
911 status = cx231xx_read_modify_write_i2c_dword(dev,
912 VID_BLK_I2C_ADDRESS,
913 OUT_CTRL1, FLD_VBIHACTRAW_EN,
914 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
915
916 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
917 if (value & 0x02) {
918 value |= (1 << 19);
919 status = vid_blk_write_word(dev, OUT_CTRL1, value);
920 }
921
922 return status;
923 }
924
925 void cx231xx_enable656(struct cx231xx *dev)
926 {
927 u8 temp = 0;
928
929
930 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
931
932
933
934 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
935 temp = temp|0x04;
936
937 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
938 }
939 EXPORT_SYMBOL_GPL(cx231xx_enable656);
940
941 void cx231xx_disable656(struct cx231xx *dev)
942 {
943 u8 temp = 0;
944
945 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
946
947 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
948 temp = temp&0xFB;
949
950 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
951 }
952 EXPORT_SYMBOL_GPL(cx231xx_disable656);
953
954
955
956
957
958
959 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
960 {
961 int status = 0;
962
963 dev_dbg(dev->dev, "%s: 0x%x\n",
964 __func__, (unsigned int)dev->norm);
965
966
967 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
968
969 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
970 dev_dbg(dev->dev, "%s: NTSC\n", __func__);
971
972
973
974 status = cx231xx_read_modify_write_i2c_dword(dev,
975 VID_BLK_I2C_ADDRESS,
976 VERT_TIM_CTRL,
977 FLD_VBLANK_CNT, 0x18);
978 status = cx231xx_read_modify_write_i2c_dword(dev,
979 VID_BLK_I2C_ADDRESS,
980 VERT_TIM_CTRL,
981 FLD_VACTIVE_CNT,
982 0x1E7000);
983 status = cx231xx_read_modify_write_i2c_dword(dev,
984 VID_BLK_I2C_ADDRESS,
985 VERT_TIM_CTRL,
986 FLD_V656BLANK_CNT,
987 0x1C000000);
988
989 status = cx231xx_read_modify_write_i2c_dword(dev,
990 VID_BLK_I2C_ADDRESS,
991 HORIZ_TIM_CTRL,
992 FLD_HBLANK_CNT,
993 cx231xx_set_field
994 (FLD_HBLANK_CNT, 0x79));
995
996 } else if (dev->norm & V4L2_STD_SECAM) {
997 dev_dbg(dev->dev, "%s: SECAM\n", __func__);
998 status = cx231xx_read_modify_write_i2c_dword(dev,
999 VID_BLK_I2C_ADDRESS,
1000 VERT_TIM_CTRL,
1001 FLD_VBLANK_CNT, 0x20);
1002 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 VID_BLK_I2C_ADDRESS,
1004 VERT_TIM_CTRL,
1005 FLD_VACTIVE_CNT,
1006 cx231xx_set_field
1007 (FLD_VACTIVE_CNT,
1008 0x244));
1009 status = cx231xx_read_modify_write_i2c_dword(dev,
1010 VID_BLK_I2C_ADDRESS,
1011 VERT_TIM_CTRL,
1012 FLD_V656BLANK_CNT,
1013 cx231xx_set_field
1014 (FLD_V656BLANK_CNT,
1015 0x24));
1016
1017 status = cx231xx_read_modify_write_i2c_dword(dev,
1018 VID_BLK_I2C_ADDRESS,
1019 HORIZ_TIM_CTRL,
1020 FLD_HBLANK_CNT,
1021 cx231xx_set_field
1022 (FLD_HBLANK_CNT, 0x85));
1023 } else {
1024 dev_dbg(dev->dev, "%s: PAL\n", __func__);
1025 status = cx231xx_read_modify_write_i2c_dword(dev,
1026 VID_BLK_I2C_ADDRESS,
1027 VERT_TIM_CTRL,
1028 FLD_VBLANK_CNT, 0x20);
1029 status = cx231xx_read_modify_write_i2c_dword(dev,
1030 VID_BLK_I2C_ADDRESS,
1031 VERT_TIM_CTRL,
1032 FLD_VACTIVE_CNT,
1033 cx231xx_set_field
1034 (FLD_VACTIVE_CNT,
1035 0x244));
1036 status = cx231xx_read_modify_write_i2c_dword(dev,
1037 VID_BLK_I2C_ADDRESS,
1038 VERT_TIM_CTRL,
1039 FLD_V656BLANK_CNT,
1040 cx231xx_set_field
1041 (FLD_V656BLANK_CNT,
1042 0x24));
1043
1044 status = cx231xx_read_modify_write_i2c_dword(dev,
1045 VID_BLK_I2C_ADDRESS,
1046 HORIZ_TIM_CTRL,
1047 FLD_HBLANK_CNT,
1048 cx231xx_set_field
1049 (FLD_HBLANK_CNT, 0x85));
1050
1051 }
1052
1053 return status;
1054 }
1055
1056 int cx231xx_unmute_audio(struct cx231xx *dev)
1057 {
1058 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1059 }
1060 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1061
1062 static int stopAudioFirmware(struct cx231xx *dev)
1063 {
1064 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1065 }
1066
1067 static int restartAudioFirmware(struct cx231xx *dev)
1068 {
1069 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1070 }
1071
1072 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1073 {
1074 int status = 0;
1075 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1076
1077 switch (INPUT(input)->amux) {
1078 case CX231XX_AMUX_VIDEO:
1079 ainput = AUDIO_INPUT_TUNER_TV;
1080 break;
1081 case CX231XX_AMUX_LINE_IN:
1082 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1083 ainput = AUDIO_INPUT_LINE;
1084 break;
1085 default:
1086 break;
1087 }
1088
1089 status = cx231xx_set_audio_decoder_input(dev, ainput);
1090
1091 return status;
1092 }
1093
1094 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1095 enum AUDIO_INPUT audio_input)
1096 {
1097 u32 dwval;
1098 int status;
1099 u8 gen_ctrl;
1100 u32 value = 0;
1101
1102
1103 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1104 gen_ctrl |= 1;
1105 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1106
1107 switch (audio_input) {
1108 case AUDIO_INPUT_LINE:
1109
1110 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1111 AUD_CHAN_SRC_PARALLEL);
1112 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1113
1114
1115
1116
1117 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1118
1119 status = vid_blk_write_word(dev, AC97_CTL,
1120 (dwval | FLD_AC97_UP2X_BYPASS));
1121
1122
1123 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1124 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1125 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1126 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1127
1128
1129
1130 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1131 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1132
1133
1134 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1135 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1136 (dwval | FLD_PATH1_AVC_THRESHOLD));
1137
1138
1139 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1140 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1141 (dwval | FLD_PATH1_SC_THRESHOLD));
1142 break;
1143
1144 case AUDIO_INPUT_TUNER_TV:
1145 default:
1146 status = stopAudioFirmware(dev);
1147
1148 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1149 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1150 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1151 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1152 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1153 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1154 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1155 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1156 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1157 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1158 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1159 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1160 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1161 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1162
1163
1164 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1165 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1166 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1167 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1168 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1169 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1170
1171 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1172
1173
1174 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1175
1176 status = restartAudioFirmware(dev);
1177
1178 switch (dev->board.tuner_type) {
1179 case TUNER_XC5000:
1180
1181 status = cx231xx_read_modify_write_i2c_dword(dev,
1182 VID_BLK_I2C_ADDRESS,
1183 CHIP_CTRL,
1184 FLD_SIF_EN,
1185 cx231xx_set_field(FLD_SIF_EN, 1));
1186 break;
1187 case TUNER_NXP_TDA18271:
1188
1189 status = cx231xx_read_modify_write_i2c_dword(dev,
1190 VID_BLK_I2C_ADDRESS,
1191 CHIP_CTRL,
1192 FLD_SIF_EN,
1193 cx231xx_set_field(FLD_SIF_EN, 0));
1194 break;
1195 default:
1196
1197
1198
1199 dev_info(dev->dev,
1200 "Unknown tuner type configuring SIF");
1201 break;
1202 }
1203 break;
1204
1205 case AUDIO_INPUT_TUNER_FM:
1206
1207
1208
1209
1210 break;
1211
1212 case AUDIO_INPUT_MUTE:
1213 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1214 break;
1215 }
1216
1217
1218 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1219 gen_ctrl &= ~1;
1220 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1221
1222 return status;
1223 }
1224
1225
1226
1227
1228 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1229 {
1230 u32 value;
1231 int status = 0;
1232
1233 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1234 value |= (~dev->board.ctl_pin_status_mask);
1235 status = vid_blk_write_word(dev, PIN_CTRL, value);
1236
1237 return status;
1238 }
1239
1240 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1241 u8 analog_or_digital)
1242 {
1243 int status = 0;
1244
1245
1246 status = cx231xx_set_gpio_direction(dev,
1247 dev->board.
1248 agc_analog_digital_select_gpio, 1);
1249
1250
1251 status = cx231xx_set_gpio_value(dev,
1252 dev->board.agc_analog_digital_select_gpio,
1253 analog_or_digital);
1254
1255 if (status < 0)
1256 return status;
1257
1258 return 0;
1259 }
1260
1261 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1262 {
1263 u8 value[4] = { 0, 0, 0, 0 };
1264 int status = 0;
1265 bool current_is_port_3;
1266
1267
1268
1269
1270
1271
1272
1273
1274 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1275 PWR_CTL_EN, value, 4);
1276 if (status < 0)
1277 return status;
1278
1279 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1280
1281
1282 if (current_is_port_3 == is_port_3)
1283 return 0;
1284
1285 if (is_port_3)
1286 value[0] |= I2C_DEMOD_EN;
1287 else
1288 value[0] &= ~I2C_DEMOD_EN;
1289
1290 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1291 PWR_CTL_EN, value, 4);
1292
1293
1294 if (status >= 0)
1295 dev->port_3_switch_enabled = is_port_3;
1296
1297 return status;
1298
1299 }
1300 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1301
1302 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1303 {
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316 }
1317
1318 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1319 {
1320 u32 value = 0;
1321 u16 i = 0;
1322
1323 value = 0x45005390;
1324 vid_blk_write_word(dev, 0x104, value);
1325
1326 for (i = 0x100; i < 0x140; i++) {
1327 vid_blk_read_word(dev, i, &value);
1328 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
1329 i = i+3;
1330 }
1331
1332 for (i = 0x300; i < 0x400; i++) {
1333 vid_blk_read_word(dev, i, &value);
1334 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
1335 i = i+3;
1336 }
1337
1338 for (i = 0x400; i < 0x440; i++) {
1339 vid_blk_read_word(dev, i, &value);
1340 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
1341 i = i+3;
1342 }
1343
1344 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1345 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1346 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1347 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1348 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1349 }
1350
1351 #if 0
1352 static void cx231xx_dump_SC_reg(struct cx231xx *dev)
1353 {
1354 u8 value[4] = { 0, 0, 0, 0 };
1355 dev_dbg(dev->dev, "%s!\n", __func__);
1356
1357 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1358 value, 4);
1359 dev_dbg(dev->dev,
1360 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1361 value[1], value[2], value[3]);
1362 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1363 value, 4);
1364 dev_dbg(dev->dev,
1365 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1366 value[1], value[2], value[3]);
1367 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1368 value, 4);
1369 dev_dbg(dev->dev,
1370 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1371 value[1], value[2], value[3]);
1372 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1373 value, 4);
1374 dev_dbg(dev->dev,
1375 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1376 value[1], value[2], value[3]);
1377
1378 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1379 value, 4);
1380 dev_dbg(dev->dev,
1381 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1382 value[1], value[2], value[3]);
1383 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1384 value, 4);
1385 dev_dbg(dev->dev,
1386 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1387 value[1], value[2], value[3]);
1388 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1389 value, 4);
1390 dev_dbg(dev->dev,
1391 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1392 value[1], value[2], value[3]);
1393 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1394 value, 4);
1395 dev_dbg(dev->dev,
1396 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1397 value[1], value[2], value[3]);
1398
1399 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1400 value, 4);
1401 dev_dbg(dev->dev,
1402 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1403 value[1], value[2], value[3]);
1404 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1405 value, 4);
1406 dev_dbg(dev->dev,
1407 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1408 value[1], value[2], value[3]);
1409 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1410 value, 4);
1411 dev_dbg(dev->dev,
1412 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1413 value[1], value[2], value[3]);
1414 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1415 value, 4);
1416 dev_dbg(dev->dev,
1417 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1418 value[1], value[2], value[3]);
1419
1420 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1421 value, 4);
1422 dev_dbg(dev->dev,
1423 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1424 value[1], value[2], value[3]);
1425 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1426 value, 4);
1427 dev_dbg(dev->dev,
1428 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1429 value[1], value[2], value[3]);
1430 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1431 value, 4);
1432 dev_dbg(dev->dev,
1433 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1434 value[1], value[2], value[3]);
1435 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1436 value, 4);
1437 dev_dbg(dev->dev,
1438 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1439 value[1], value[2], value[3]);
1440
1441 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1442 value, 4);
1443 dev_dbg(dev->dev,
1444 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1445 value[1], value[2], value[3]);
1446 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1447 value, 4);
1448 dev_dbg(dev->dev,
1449 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1450 value[1], value[2], value[3]);
1451 }
1452 #endif
1453
1454 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1455
1456 {
1457 u8 value = 0;
1458
1459 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1460 value = (value & 0xFE)|0x01;
1461 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1462
1463 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1464 value = (value & 0xFE)|0x00;
1465 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1478 value = (value & 0xFC)|0x00;
1479 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1480
1481 afe_read_byte(dev, ADC_INPUT_CH3, &value);
1482 value = (value & 0xF9)|0x02;
1483 afe_write_byte(dev, ADC_INPUT_CH3, value);
1484
1485 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1486 value = (value & 0xFB)|0x04;
1487 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1488
1489 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1490 value = (value & 0xFC)|0x03;
1491 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1492
1493 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1494 value = (value & 0xFB)|0x04;
1495 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1496
1497 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1498 value = (value & 0xF8)|0x06;
1499 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1500
1501 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1502 value = (value & 0x8F)|0x40;
1503 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1504
1505 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1506 value = (value & 0xDF)|0x20;
1507 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1508 }
1509
1510 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1511 u8 spectral_invert, u32 mode)
1512 {
1513 u32 colibri_carrier_offset = 0;
1514 u32 func_mode = 0x01;
1515 u32 standard = 0;
1516 u8 value[4] = { 0, 0, 0, 0 };
1517
1518 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n");
1519 value[0] = (u8) 0x6F;
1520 value[1] = (u8) 0x6F;
1521 value[2] = (u8) 0x6F;
1522 value[3] = (u8) 0x6F;
1523 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1524 PWR_CTL_EN, value, 4);
1525
1526
1527 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1528
1529
1530 standard = dev->norm;
1531 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1532 func_mode, standard);
1533
1534
1535 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1536 standard);
1537
1538 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n",
1539 colibri_carrier_offset, standard);
1540
1541
1542 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1543 spectral_invert, mode);
1544 }
1545
1546 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1547 {
1548 u32 colibri_carrier_offset = 0;
1549
1550 if (mode == TUNER_MODE_FM_RADIO) {
1551 colibri_carrier_offset = 1100000;
1552 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
1553 colibri_carrier_offset = 4832000;
1554 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1555 colibri_carrier_offset = 2700000;
1556 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1557 | V4L2_STD_SECAM)) {
1558 colibri_carrier_offset = 2100000;
1559 }
1560
1561 return colibri_carrier_offset;
1562 }
1563
1564 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1565 u8 spectral_invert, u32 mode)
1566 {
1567 unsigned long pll_freq_word;
1568 u32 dif_misc_ctrl_value = 0;
1569 u64 pll_freq_u64 = 0;
1570 u32 i = 0;
1571
1572 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1573 if_freq, spectral_invert, mode);
1574
1575
1576 if (mode == TUNER_MODE_FM_RADIO) {
1577 pll_freq_word = 0x905A1CAC;
1578 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1579
1580 } else {
1581
1582 pll_freq_word = if_freq;
1583 pll_freq_u64 = (u64)pll_freq_word << 28L;
1584 do_div(pll_freq_u64, 50000000);
1585 pll_freq_word = (u32)pll_freq_u64;
1586
1587 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1588
1589 if (spectral_invert) {
1590 if_freq -= 400000;
1591
1592 vid_blk_read_word(dev, DIF_MISC_CTRL,
1593 &dif_misc_ctrl_value);
1594 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1595 vid_blk_write_word(dev, DIF_MISC_CTRL,
1596 dif_misc_ctrl_value);
1597 } else {
1598 if_freq += 400000;
1599
1600 vid_blk_read_word(dev, DIF_MISC_CTRL,
1601 &dif_misc_ctrl_value);
1602 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1603 vid_blk_write_word(dev, DIF_MISC_CTRL,
1604 dif_misc_ctrl_value);
1605 }
1606
1607 if_freq = (if_freq / 100000) * 100000;
1608
1609 if (if_freq < 3000000)
1610 if_freq = 3000000;
1611
1612 if (if_freq > 16000000)
1613 if_freq = 16000000;
1614 }
1615
1616 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array));
1617 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
1618 if (Dif_set_array[i].if_freq == if_freq) {
1619 vid_blk_write_word(dev,
1620 Dif_set_array[i].register_address, Dif_set_array[i].value);
1621 }
1622 }
1623 }
1624
1625
1626
1627
1628 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1629 u32 function_mode, u32 standard)
1630 {
1631 int status = 0;
1632
1633
1634 if (mode == V4L2_TUNER_RADIO) {
1635
1636
1637 status = cx231xx_reg_mask_write(dev,
1638 VID_BLK_I2C_ADDRESS, 32,
1639 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1640
1641 status = cx231xx_reg_mask_write(dev,
1642 VID_BLK_I2C_ADDRESS, 32,
1643 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1644
1645 status = cx231xx_reg_mask_write(dev,
1646 VID_BLK_I2C_ADDRESS, 32,
1647 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1648
1649 status = cx231xx_reg_mask_write(dev,
1650 VID_BLK_I2C_ADDRESS, 32,
1651 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1652 } else if (standard != DIF_USE_BASEBAND) {
1653 if (standard & V4L2_STD_MN) {
1654
1655 status = cx231xx_reg_mask_write(dev,
1656 VID_BLK_I2C_ADDRESS, 32,
1657 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1658
1659 status = cx231xx_reg_mask_write(dev,
1660 VID_BLK_I2C_ADDRESS, 32,
1661 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1662 function_mode);
1663
1664 status = cx231xx_reg_mask_write(dev,
1665 VID_BLK_I2C_ADDRESS, 32,
1666 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1667
1668 status = cx231xx_reg_mask_write(dev,
1669 VID_BLK_I2C_ADDRESS, 32,
1670 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1671
1672 status = cx231xx_reg_mask_write(dev,
1673 VID_BLK_I2C_ADDRESS, 32,
1674 AUD_IO_CTRL, 0, 31, 0x00000003);
1675 } else if ((standard == V4L2_STD_PAL_I) |
1676 (standard & V4L2_STD_PAL_D) |
1677 (standard & V4L2_STD_SECAM)) {
1678
1679
1680 status = cx231xx_reg_mask_write(dev,
1681 VID_BLK_I2C_ADDRESS, 32,
1682 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1683
1684 status = cx231xx_reg_mask_write(dev,
1685 VID_BLK_I2C_ADDRESS, 32,
1686 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1687 function_mode);
1688
1689 status = cx231xx_reg_mask_write(dev,
1690 VID_BLK_I2C_ADDRESS, 32,
1691 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1692
1693 status = cx231xx_reg_mask_write(dev,
1694 VID_BLK_I2C_ADDRESS, 32,
1695 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1696 } else {
1697
1698
1699
1700 status = cx231xx_reg_mask_write(dev,
1701 VID_BLK_I2C_ADDRESS, 32,
1702 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1703
1704 status = cx231xx_reg_mask_write(dev,
1705 VID_BLK_I2C_ADDRESS, 32,
1706 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1707 function_mode);
1708
1709 status = cx231xx_reg_mask_write(dev,
1710 VID_BLK_I2C_ADDRESS, 32,
1711 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1712
1713 status = cx231xx_reg_mask_write(dev,
1714 VID_BLK_I2C_ADDRESS, 32,
1715 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1716 }
1717 }
1718
1719 return status;
1720 }
1721
1722 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1723 {
1724 int status = 0;
1725 u32 dif_misc_ctrl_value = 0;
1726 u32 func_mode = 0;
1727
1728 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard);
1729
1730 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1731 if (standard != DIF_USE_BASEBAND)
1732 dev->norm = standard;
1733
1734 switch (dev->model) {
1735 case CX231XX_BOARD_CNXT_CARRAERA:
1736 case CX231XX_BOARD_CNXT_RDE_250:
1737 case CX231XX_BOARD_CNXT_SHELBY:
1738 case CX231XX_BOARD_CNXT_RDU_250:
1739 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1740 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1741 case CX231XX_BOARD_OTG102:
1742 func_mode = 0x03;
1743 break;
1744 case CX231XX_BOARD_CNXT_RDE_253S:
1745 case CX231XX_BOARD_CNXT_RDU_253S:
1746 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
1747 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
1748 func_mode = 0x01;
1749 break;
1750 default:
1751 func_mode = 0x01;
1752 }
1753
1754 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1755 func_mode, standard);
1756
1757 if (standard == DIF_USE_BASEBAND) {
1758
1759
1760 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1761 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1762 &dif_misc_ctrl_value);
1763 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1764 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1765 dif_misc_ctrl_value);
1766 } else if (standard & V4L2_STD_PAL_D) {
1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1774 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1777 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1784 DIF_AGC_IF_INT_CURRENT, 0, 31,
1785 0x26001700);
1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787 DIF_AGC_RF_CURRENT, 0, 31,
1788 0x00002660);
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 DIF_VIDEO_AGC_CTRL, 0, 31,
1791 0x72500800);
1792 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1793 DIF_VID_AUD_OVERRIDE, 0, 31,
1794 0x27000100);
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1798 DIF_COMP_FLT_CTRL, 0, 31,
1799 0x00000000);
1800 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1801 DIF_SRC_PHASE_INC, 0, 31,
1802 0x1befbf06);
1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1804 DIF_SRC_GAIN_CONTROL, 0, 31,
1805 0x000035e8);
1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1808
1809 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1810 dif_misc_ctrl_value |= 0x3a023F11;
1811 } else if (standard & V4L2_STD_PAL_I) {
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1822 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1829 DIF_AGC_IF_INT_CURRENT, 0, 31,
1830 0x26001700);
1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832 DIF_AGC_RF_CURRENT, 0, 31,
1833 0x00002660);
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 DIF_VIDEO_AGC_CTRL, 0, 31,
1836 0x72500800);
1837 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1838 DIF_VID_AUD_OVERRIDE, 0, 31,
1839 0x27000100);
1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1842 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1843 DIF_COMP_FLT_CTRL, 0, 31,
1844 0x00000000);
1845 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1846 DIF_SRC_PHASE_INC, 0, 31,
1847 0x1befbf06);
1848 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1849 DIF_SRC_GAIN_CONTROL, 0, 31,
1850 0x000035e8);
1851 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1852 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1853
1854 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1855 dif_misc_ctrl_value |= 0x3a033F11;
1856 } else if (standard & V4L2_STD_PAL_M) {
1857
1858 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1859 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1860 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1861 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1862 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1863 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1864 0x26001700);
1865 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1866 0x00002660);
1867 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1868 0x72500800);
1869 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1870 0x27000100);
1871 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1872 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1873 0x009f50c1);
1874 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1875 0x1befbf06);
1876 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1877 0x000035e8);
1878 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1879 0x00000000);
1880
1881 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1882 dif_misc_ctrl_value |= 0x3A0A3F10;
1883 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1884
1885 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1886 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1887 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1888 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1889 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1890 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1891 0x26001700);
1892 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1893 0x00002660);
1894 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1895 0x72500800);
1896 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1897 0x27000100);
1898 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1899 0x012c405d);
1900 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1901 0x009f50c1);
1902 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1903 0x1befbf06);
1904 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1905 0x000035e8);
1906 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1907 0x00000000);
1908
1909 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1910 dif_misc_ctrl_value = 0x3A093F10;
1911 } else if (standard &
1912 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1913 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1914
1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1916 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1922 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1926 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 DIF_AGC_IF_INT_CURRENT, 0, 31,
1933 0x26001700);
1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935 DIF_AGC_RF_CURRENT, 0, 31,
1936 0x00002660);
1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1938 DIF_VID_AUD_OVERRIDE, 0, 31,
1939 0x27000100);
1940 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1942 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1943 DIF_COMP_FLT_CTRL, 0, 31,
1944 0x00000000);
1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1946 DIF_SRC_PHASE_INC, 0, 31,
1947 0x1befbf06);
1948 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1949 DIF_SRC_GAIN_CONTROL, 0, 31,
1950 0x000035e8);
1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1954 DIF_VIDEO_AGC_CTRL, 0, 31,
1955 0xf4000000);
1956
1957
1958 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1959 dif_misc_ctrl_value |= 0x3a023F11;
1960 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1961
1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1969 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1973 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 DIF_AGC_IF_INT_CURRENT, 0, 31,
1980 0x26001700);
1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982 DIF_AGC_RF_CURRENT, 0, 31,
1983 0x00002660);
1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1985 DIF_VID_AUD_OVERRIDE, 0, 31,
1986 0x27000100);
1987 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1989 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1990 DIF_COMP_FLT_CTRL, 0, 31,
1991 0x00000000);
1992 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1993 DIF_SRC_PHASE_INC, 0, 31,
1994 0x1befbf06);
1995 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1996 DIF_SRC_GAIN_CONTROL, 0, 31,
1997 0x000035e8);
1998 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1999 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2000 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2001 DIF_VIDEO_AGC_CTRL, 0, 31,
2002 0xf2560000);
2003
2004
2005 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2006 dif_misc_ctrl_value |= 0x3a023F11;
2007
2008 } else if (standard & V4L2_STD_NTSC_M) {
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2019 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2020 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2021 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2022 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2023 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2024 0x26001700);
2025 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2026 0x00002660);
2027 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2028 0x04000800);
2029 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2030 0x27000100);
2031 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2032
2033 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2034 0x009f50c1);
2035 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2036 0x1befbf06);
2037 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2038 0x000035e8);
2039
2040 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2041 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2042 0xC2262600);
2043 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2044
2045
2046 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2047 dif_misc_ctrl_value |= 0x3a003F10;
2048 } else {
2049
2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2051 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2057 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2060 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2067 DIF_AGC_IF_INT_CURRENT, 0, 31,
2068 0x26001700);
2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070 DIF_AGC_RF_CURRENT, 0, 31,
2071 0x00002660);
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 DIF_VIDEO_AGC_CTRL, 0, 31,
2074 0x72500800);
2075 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2076 DIF_VID_AUD_OVERRIDE, 0, 31,
2077 0x27000100);
2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2080 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2081 DIF_COMP_FLT_CTRL, 0, 31,
2082 0x00A653A8);
2083 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2084 DIF_SRC_PHASE_INC, 0, 31,
2085 0x1befbf06);
2086 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2087 DIF_SRC_GAIN_CONTROL, 0, 31,
2088 0x000035e8);
2089 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2090 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2091
2092 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2093 dif_misc_ctrl_value |= 0x3a013F11;
2094 }
2095
2096
2097
2098 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2099
2100
2101
2102
2103 if (dev->active_mode == V4L2_TUNER_RADIO)
2104 dif_misc_ctrl_value = 0x7a080000;
2105
2106
2107 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2108
2109 return status;
2110 }
2111
2112 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2113 {
2114 int status = 0;
2115 u32 dwval;
2116
2117
2118 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2119 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2120 dwval |= 0x33000000;
2121
2122 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2123
2124 return status;
2125 }
2126
2127 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2128 {
2129 int status = 0;
2130 u32 dwval;
2131 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n",
2132 __func__, dev->tuner_type);
2133
2134
2135 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2136 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2137
2138 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2139 V4L2_STD_SECAM_D)) {
2140 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2141 dwval &= ~FLD_DIF_IF_REF;
2142 dwval |= 0x88000300;
2143 } else
2144 dwval |= 0x88000000;
2145 } else {
2146 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2147 dwval &= ~FLD_DIF_IF_REF;
2148 dwval |= 0xCC000300;
2149 } else
2150 dwval |= 0x44000000;
2151 }
2152
2153 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2154
2155 return status == sizeof(dwval) ? 0 : -EIO;
2156 }
2157
2158
2159
2160
2161 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2162 {
2163 int status = 0;
2164 u32 value;
2165
2166 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2167 CH_PWR_CTRL1, 1, &value, 1);
2168
2169 value |= 0x80;
2170 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2171 CH_PWR_CTRL1, 1, value, 1);
2172
2173 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2174 CH_PWR_CTRL2, 1, 0x00, 1);
2175
2176 return status;
2177 }
2178
2179 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2180 enum AV_MODE avmode)
2181 {
2182 int status = 0;
2183 u32 value = 0;
2184
2185 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2186 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2187 CH_PWR_CTRL2, 1, &value, 1);
2188 value |= 0xfe;
2189 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2190 CH_PWR_CTRL2, 1, value, 1);
2191 } else {
2192 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2193 CH_PWR_CTRL2, 1, 0x00, 1);
2194 }
2195
2196 return status;
2197 }
2198
2199
2200 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2201 {
2202 int status = 0;
2203
2204 switch (audio_input) {
2205 case CX231XX_AMUX_LINE_IN:
2206 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2207 CH_PWR_CTRL2, 1, 0x00, 1);
2208 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2209 CH_PWR_CTRL1, 1, 0x80, 1);
2210 break;
2211 case CX231XX_AMUX_VIDEO:
2212 default:
2213 break;
2214 }
2215
2216 dev->ctl_ainput = audio_input;
2217
2218 return status;
2219 }
2220
2221
2222
2223
2224 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2225 {
2226 u8 value[4] = { 0, 0, 0, 0 };
2227 u32 tmp = 0;
2228 int status = 0;
2229
2230 if (dev->power_mode != mode)
2231 dev->power_mode = mode;
2232 else {
2233 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n",
2234 __func__, mode);
2235 return 0;
2236 }
2237
2238 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2239 4);
2240 if (status < 0)
2241 return status;
2242
2243 tmp = le32_to_cpu(*((__le32 *) value));
2244
2245 switch (mode) {
2246 case POLARIS_AVMODE_ENXTERNAL_AV:
2247
2248 tmp &= (~PWR_MODE_MASK);
2249
2250 tmp |= PWR_AV_EN;
2251 value[0] = (u8) tmp;
2252 value[1] = (u8) (tmp >> 8);
2253 value[2] = (u8) (tmp >> 16);
2254 value[3] = (u8) (tmp >> 24);
2255 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2256 PWR_CTL_EN, value, 4);
2257 msleep(PWR_SLEEP_INTERVAL);
2258
2259 tmp |= PWR_ISO_EN;
2260 value[0] = (u8) tmp;
2261 value[1] = (u8) (tmp >> 8);
2262 value[2] = (u8) (tmp >> 16);
2263 value[3] = (u8) (tmp >> 24);
2264 status =
2265 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2266 value, 4);
2267 msleep(PWR_SLEEP_INTERVAL);
2268
2269 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2270 value[0] = (u8) tmp;
2271 value[1] = (u8) (tmp >> 8);
2272 value[2] = (u8) (tmp >> 16);
2273 value[3] = (u8) (tmp >> 24);
2274 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2275 PWR_CTL_EN, value, 4);
2276
2277
2278 dev->xc_fw_load_done = 0;
2279 break;
2280
2281 case POLARIS_AVMODE_ANALOGT_TV:
2282
2283 tmp |= PWR_DEMOD_EN;
2284 value[0] = (u8) tmp;
2285 value[1] = (u8) (tmp >> 8);
2286 value[2] = (u8) (tmp >> 16);
2287 value[3] = (u8) (tmp >> 24);
2288 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2289 PWR_CTL_EN, value, 4);
2290 msleep(PWR_SLEEP_INTERVAL);
2291
2292 if (!(tmp & PWR_TUNER_EN)) {
2293 tmp |= (PWR_TUNER_EN);
2294 value[0] = (u8) tmp;
2295 value[1] = (u8) (tmp >> 8);
2296 value[2] = (u8) (tmp >> 16);
2297 value[3] = (u8) (tmp >> 24);
2298 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2299 PWR_CTL_EN, value, 4);
2300 msleep(PWR_SLEEP_INTERVAL);
2301 }
2302
2303 if (!(tmp & PWR_AV_EN)) {
2304 tmp |= PWR_AV_EN;
2305 value[0] = (u8) tmp;
2306 value[1] = (u8) (tmp >> 8);
2307 value[2] = (u8) (tmp >> 16);
2308 value[3] = (u8) (tmp >> 24);
2309 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2310 PWR_CTL_EN, value, 4);
2311 msleep(PWR_SLEEP_INTERVAL);
2312 }
2313 if (!(tmp & PWR_ISO_EN)) {
2314 tmp |= PWR_ISO_EN;
2315 value[0] = (u8) tmp;
2316 value[1] = (u8) (tmp >> 8);
2317 value[2] = (u8) (tmp >> 16);
2318 value[3] = (u8) (tmp >> 24);
2319 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2320 PWR_CTL_EN, value, 4);
2321 msleep(PWR_SLEEP_INTERVAL);
2322 }
2323
2324 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2325 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2326 value[0] = (u8) tmp;
2327 value[1] = (u8) (tmp >> 8);
2328 value[2] = (u8) (tmp >> 16);
2329 value[3] = (u8) (tmp >> 24);
2330 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2331 PWR_CTL_EN, value, 4);
2332 msleep(PWR_SLEEP_INTERVAL);
2333 }
2334
2335 if (dev->board.tuner_type != TUNER_ABSENT) {
2336
2337 if (dev->board.tuner_gpio)
2338 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2339
2340 if (dev->cx231xx_reset_analog_tuner)
2341 dev->cx231xx_reset_analog_tuner(dev);
2342 }
2343
2344 break;
2345
2346 case POLARIS_AVMODE_DIGITAL:
2347 if (!(tmp & PWR_TUNER_EN)) {
2348 tmp |= (PWR_TUNER_EN);
2349 value[0] = (u8) tmp;
2350 value[1] = (u8) (tmp >> 8);
2351 value[2] = (u8) (tmp >> 16);
2352 value[3] = (u8) (tmp >> 24);
2353 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2354 PWR_CTL_EN, value, 4);
2355 msleep(PWR_SLEEP_INTERVAL);
2356 }
2357 if (!(tmp & PWR_AV_EN)) {
2358 tmp |= PWR_AV_EN;
2359 value[0] = (u8) tmp;
2360 value[1] = (u8) (tmp >> 8);
2361 value[2] = (u8) (tmp >> 16);
2362 value[3] = (u8) (tmp >> 24);
2363 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2364 PWR_CTL_EN, value, 4);
2365 msleep(PWR_SLEEP_INTERVAL);
2366 }
2367 if (!(tmp & PWR_ISO_EN)) {
2368 tmp |= PWR_ISO_EN;
2369 value[0] = (u8) tmp;
2370 value[1] = (u8) (tmp >> 8);
2371 value[2] = (u8) (tmp >> 16);
2372 value[3] = (u8) (tmp >> 24);
2373 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2374 PWR_CTL_EN, value, 4);
2375 msleep(PWR_SLEEP_INTERVAL);
2376 }
2377
2378 tmp &= (~PWR_AV_MODE);
2379 tmp |= POLARIS_AVMODE_DIGITAL;
2380 value[0] = (u8) tmp;
2381 value[1] = (u8) (tmp >> 8);
2382 value[2] = (u8) (tmp >> 16);
2383 value[3] = (u8) (tmp >> 24);
2384 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2385 PWR_CTL_EN, value, 4);
2386 msleep(PWR_SLEEP_INTERVAL);
2387
2388 if (!(tmp & PWR_DEMOD_EN)) {
2389 tmp |= PWR_DEMOD_EN;
2390 value[0] = (u8) tmp;
2391 value[1] = (u8) (tmp >> 8);
2392 value[2] = (u8) (tmp >> 16);
2393 value[3] = (u8) (tmp >> 24);
2394 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2395 PWR_CTL_EN, value, 4);
2396 msleep(PWR_SLEEP_INTERVAL);
2397 }
2398
2399 if (dev->board.tuner_type != TUNER_ABSENT) {
2400
2401 if (dev->board.tuner_gpio)
2402 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2403
2404 if (dev->cx231xx_reset_analog_tuner)
2405 dev->cx231xx_reset_analog_tuner(dev);
2406 }
2407 break;
2408
2409 default:
2410 break;
2411 }
2412
2413 msleep(PWR_SLEEP_INTERVAL);
2414
2415
2416
2417 if (mode == POLARIS_AVMODE_DIGITAL) {
2418 tmp |= PWR_RESETOUT_EN;
2419 value[0] = (u8) tmp;
2420 value[1] = (u8) (tmp >> 8);
2421 value[2] = (u8) (tmp >> 16);
2422 value[3] = (u8) (tmp >> 24);
2423 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2424 PWR_CTL_EN, value, 4);
2425 msleep(PWR_SLEEP_INTERVAL);
2426 }
2427
2428
2429 status = cx231xx_afe_update_power_control(dev, mode);
2430
2431
2432 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2433
2434 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2435 4);
2436
2437 return status;
2438 }
2439
2440 int cx231xx_power_suspend(struct cx231xx *dev)
2441 {
2442 u8 value[4] = { 0, 0, 0, 0 };
2443 u32 tmp = 0;
2444 int status = 0;
2445
2446 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2447 value, 4);
2448 if (status > 0)
2449 return status;
2450
2451 tmp = le32_to_cpu(*((__le32 *) value));
2452 tmp &= (~PWR_MODE_MASK);
2453
2454 value[0] = (u8) tmp;
2455 value[1] = (u8) (tmp >> 8);
2456 value[2] = (u8) (tmp >> 16);
2457 value[3] = (u8) (tmp >> 24);
2458 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2459 value, 4);
2460
2461 return status;
2462 }
2463
2464
2465
2466
2467 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2468 {
2469 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2470 u32 tmp = 0;
2471 int status = 0;
2472
2473 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
2474 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2475 value, 4);
2476 if (status < 0)
2477 return status;
2478
2479 tmp = le32_to_cpu(*((__le32 *) value));
2480 tmp |= ep_mask;
2481 value[0] = (u8) tmp;
2482 value[1] = (u8) (tmp >> 8);
2483 value[2] = (u8) (tmp >> 16);
2484 value[3] = (u8) (tmp >> 24);
2485
2486 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2487 value, 4);
2488
2489 return status;
2490 }
2491
2492 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2493 {
2494 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2495 u32 tmp = 0;
2496 int status = 0;
2497
2498 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
2499 status =
2500 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2501 if (status < 0)
2502 return status;
2503
2504 tmp = le32_to_cpu(*((__le32 *) value));
2505 tmp &= (~ep_mask);
2506 value[0] = (u8) tmp;
2507 value[1] = (u8) (tmp >> 8);
2508 value[2] = (u8) (tmp >> 16);
2509 value[3] = (u8) (tmp >> 24);
2510
2511 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2512 value, 4);
2513
2514 return status;
2515 }
2516
2517 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2518 {
2519 int status = 0;
2520 u32 value = 0;
2521 u8 val[4] = { 0, 0, 0, 0 };
2522
2523 if (dev->udev->speed == USB_SPEED_HIGH) {
2524 switch (media_type) {
2525 case Audio:
2526 dev_dbg(dev->dev,
2527 "%s: Audio enter HANC\n", __func__);
2528 status =
2529 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2530 break;
2531
2532 case Vbi:
2533 dev_dbg(dev->dev,
2534 "%s: set vanc registers\n", __func__);
2535 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2536 break;
2537
2538 case Sliced_cc:
2539 dev_dbg(dev->dev,
2540 "%s: set hanc registers\n", __func__);
2541 status =
2542 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2543 break;
2544
2545 case Raw_Video:
2546 dev_dbg(dev->dev,
2547 "%s: set video registers\n", __func__);
2548 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2549 break;
2550
2551 case TS1_serial_mode:
2552 dev_dbg(dev->dev,
2553 "%s: set ts1 registers", __func__);
2554
2555 if (dev->board.has_417) {
2556 dev_dbg(dev->dev,
2557 "%s: MPEG\n", __func__);
2558 value &= 0xFFFFFFFC;
2559 value |= 0x3;
2560
2561 status = cx231xx_mode_register(dev,
2562 TS_MODE_REG, value);
2563
2564 val[0] = 0x04;
2565 val[1] = 0xA3;
2566 val[2] = 0x3B;
2567 val[3] = 0x00;
2568 status = cx231xx_write_ctrl_reg(dev,
2569 VRT_SET_REGISTER,
2570 TS1_CFG_REG, val, 4);
2571
2572 val[0] = 0x00;
2573 val[1] = 0x08;
2574 val[2] = 0x00;
2575 val[3] = 0x08;
2576 status = cx231xx_write_ctrl_reg(dev,
2577 VRT_SET_REGISTER,
2578 TS1_LENGTH_REG, val, 4);
2579 } else {
2580 dev_dbg(dev->dev, "%s: BDA\n", __func__);
2581 status = cx231xx_mode_register(dev,
2582 TS_MODE_REG, 0x101);
2583 status = cx231xx_mode_register(dev,
2584 TS1_CFG_REG, 0x010);
2585 }
2586 break;
2587
2588 case TS1_parallel_mode:
2589 dev_dbg(dev->dev,
2590 "%s: set ts1 parallel mode registers\n",
2591 __func__);
2592 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2593 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2594 break;
2595 }
2596 } else {
2597 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2598 }
2599
2600 return status;
2601 }
2602
2603 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2604 {
2605 int rc = -1;
2606 u32 ep_mask = -1;
2607 struct pcb_config *pcb_config;
2608
2609
2610 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2611
2612 if (pcb_config->config_num) {
2613 switch (media_type) {
2614 case Raw_Video:
2615 ep_mask = ENABLE_EP4;
2616 break;
2617 case Audio:
2618 ep_mask = ENABLE_EP3;
2619 break;
2620 case Vbi:
2621 ep_mask = ENABLE_EP5;
2622 break;
2623 case Sliced_cc:
2624 ep_mask = ENABLE_EP6;
2625 break;
2626 case TS1_serial_mode:
2627 case TS1_parallel_mode:
2628 ep_mask = ENABLE_EP1;
2629 break;
2630 case TS2:
2631 ep_mask = ENABLE_EP2;
2632 break;
2633 }
2634 }
2635
2636 if (start) {
2637 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2638
2639 if (rc < 0)
2640 return rc;
2641
2642
2643 if (ep_mask > 0)
2644 rc = cx231xx_start_stream(dev, ep_mask);
2645 } else {
2646
2647 if (ep_mask > 0)
2648 rc = cx231xx_stop_stream(dev, ep_mask);
2649 }
2650
2651 return rc;
2652 }
2653 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2654
2655
2656
2657
2658 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
2659 {
2660 int status = 0;
2661
2662 gpio_val = (__force u32)cpu_to_le32(gpio_val);
2663 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
2664
2665 return status;
2666 }
2667
2668 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
2669 {
2670 __le32 tmp;
2671 int status = 0;
2672
2673 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2674 *gpio_val = le32_to_cpu(tmp);
2675
2676 return status;
2677 }
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2691 int pin_number, int pin_value)
2692 {
2693 int status = 0;
2694 u32 value = 0;
2695
2696
2697 if (pin_number >= 32)
2698 return -EINVAL;
2699
2700
2701 if (pin_value == 0)
2702 value = dev->gpio_dir & (~(1 << pin_number));
2703 else
2704 value = dev->gpio_dir | (1 << pin_number);
2705
2706 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
2707
2708
2709 dev->gpio_dir = value;
2710
2711 return status;
2712 }
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2726 {
2727 int status = 0;
2728 u32 value = 0;
2729
2730
2731 if (pin_number >= 32)
2732 return -EINVAL;
2733
2734
2735 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2736
2737 value = dev->gpio_dir | (1 << pin_number);
2738 dev->gpio_dir = value;
2739 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2740 dev->gpio_val);
2741 value = 0;
2742 }
2743
2744 if (pin_value == 0)
2745 value = dev->gpio_val & (~(1 << pin_number));
2746 else
2747 value = dev->gpio_val | (1 << pin_number);
2748
2749
2750 dev->gpio_val = value;
2751
2752
2753 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2754
2755 return status;
2756 }
2757
2758
2759
2760
2761 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2762 {
2763 int status = 0;
2764
2765
2766 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2767 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2768 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2769 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2770
2771 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2772 if (status < 0)
2773 return -EINVAL;
2774
2775
2776 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2777 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2778
2779 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2780 if (status < 0)
2781 return -EINVAL;
2782
2783
2784 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2785 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2786
2787 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2788 if (status < 0)
2789 return -EINVAL;
2790
2791 return status;
2792 }
2793
2794 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2795 {
2796 int status = 0;
2797
2798
2799 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2800 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2801
2802 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2803 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2804
2805 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2806 if (status < 0)
2807 return -EINVAL;
2808
2809
2810 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2811 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2812
2813 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2814 if (status < 0)
2815 return -EINVAL;
2816
2817
2818
2819 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2820 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2821
2822 status =
2823 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2824 if (status < 0)
2825 return -EINVAL;
2826
2827 return status;
2828 }
2829
2830 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2831 {
2832 int status = 0;
2833 u8 i;
2834
2835
2836 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2837 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2838
2839 for (i = 0; i < 8; i++) {
2840 if (((data << i) & 0x80) == 0) {
2841
2842 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2843 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2844 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2845 dev->gpio_val);
2846
2847
2848 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2849 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2850 dev->gpio_val);
2851
2852
2853 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2854 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2855 dev->gpio_val);
2856 } else {
2857
2858 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2859 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2860 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2861 dev->gpio_val);
2862
2863
2864 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2865 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2866 dev->gpio_val);
2867
2868
2869 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2870 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2871 dev->gpio_val);
2872 }
2873 }
2874 return status;
2875 }
2876
2877 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2878 {
2879 u8 value = 0;
2880 int status = 0;
2881 u32 gpio_logic_value = 0;
2882 u8 i;
2883
2884
2885 for (i = 0; i < 8; i++) {
2886
2887
2888 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2889 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2890 dev->gpio_val);
2891
2892
2893 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2894 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2895 dev->gpio_val);
2896
2897
2898 gpio_logic_value = dev->gpio_val;
2899 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2900 &dev->gpio_val);
2901 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2902 value |= (1 << (8 - i - 1));
2903
2904 dev->gpio_val = gpio_logic_value;
2905 }
2906
2907
2908
2909
2910 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2911 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2912
2913
2914 *buf = value & 0xff;
2915
2916 return status;
2917 }
2918
2919 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2920 {
2921 int status = 0;
2922 u32 gpio_logic_value = 0;
2923 int nCnt = 10;
2924 int nInit = nCnt;
2925
2926
2927
2928 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2929 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2930
2931 gpio_logic_value = dev->gpio_val;
2932 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2933
2934 do {
2935 msleep(2);
2936 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2937 &dev->gpio_val);
2938 nCnt--;
2939 } while (((dev->gpio_val &
2940 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2941 (nCnt > 0));
2942
2943 if (nCnt == 0)
2944 dev_dbg(dev->dev,
2945 "No ACK after %d msec -GPIO I2C failed!",
2946 nInit * 10);
2947
2948
2949
2950
2951
2952
2953 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
2954
2955 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2956 dev->gpio_val = gpio_logic_value;
2957 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2958 status = 0;
2959 } else {
2960 dev->gpio_val = gpio_logic_value;
2961 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2962 }
2963
2964
2965
2966 dev->gpio_val = gpio_logic_value;
2967 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2968 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2969 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2970
2971 return status;
2972 }
2973
2974 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2975 {
2976 int status = 0;
2977
2978
2979 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2980 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2981
2982
2983 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2984 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2985 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2986
2987
2988 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2989 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2990
2991
2992 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2993 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2994
2995
2996 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2998
2999 return status;
3000 }
3001
3002 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3003 {
3004 int status = 0;
3005
3006
3007 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3008 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3009 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3010
3011
3012 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3013 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3014
3015
3016 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3017 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3018
3019 return status;
3020 }
3021
3022
3023
3024
3025
3026
3027
3028 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3029 {
3030 int status = 0;
3031 int i = 0;
3032
3033
3034 mutex_lock(&dev->gpio_i2c_lock);
3035
3036
3037 status = cx231xx_gpio_i2c_start(dev);
3038
3039
3040 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3041
3042
3043 status = cx231xx_gpio_i2c_read_ack(dev);
3044
3045
3046 for (i = 0; i < len; i++) {
3047
3048 buf[i] = 0;
3049 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3050
3051 if ((i + 1) != len) {
3052
3053 status = cx231xx_gpio_i2c_write_ack(dev);
3054 }
3055 }
3056
3057
3058 status = cx231xx_gpio_i2c_write_nak(dev);
3059
3060
3061 status = cx231xx_gpio_i2c_end(dev);
3062
3063
3064 mutex_unlock(&dev->gpio_i2c_lock);
3065
3066 return status;
3067 }
3068
3069
3070
3071
3072 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3073 {
3074 int i = 0;
3075
3076
3077 mutex_lock(&dev->gpio_i2c_lock);
3078
3079
3080 cx231xx_gpio_i2c_start(dev);
3081
3082
3083 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3084
3085
3086 cx231xx_gpio_i2c_read_ack(dev);
3087
3088 for (i = 0; i < len; i++) {
3089
3090 cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3091
3092
3093 cx231xx_gpio_i2c_read_ack(dev);
3094 }
3095
3096
3097 cx231xx_gpio_i2c_end(dev);
3098
3099
3100 mutex_unlock(&dev->gpio_i2c_lock);
3101
3102 return 0;
3103 }