drivers/media/rc/mtk-cir.c

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This source file includes following definitions.
mtk_chkdata_reg
mtk_chk_period
mtk_w32_mask
mtk_w32
mtk_r32
mtk_irq_disable
mtk_irq_enable
mtk_ir_irq
mtk_ir_probe
mtk_ir_remove
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Mediatek IR Receiver Controller
   4  *
   5  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   6  */
   7 
   8 #include <linux/clk.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/reset.h>
  13 #include <media/rc-core.h>
  14 
  15 #define MTK_IR_DEV KBUILD_MODNAME
  16 
  17 /* Register to enable PWM and IR */
  18 #define MTK_CONFIG_HIGH_REG       0x0c
  19 
  20 /* Bit to enable IR pulse width detection */
  21 #define MTK_PWM_EN                BIT(13)
  22 
  23 /*
  24  * Register to setting ok count whose unit based on hardware sampling period
  25  * indicating IR receiving completion and then making IRQ fires
  26  */
  27 #define MTK_OK_COUNT(x)           (((x) & GENMASK(23, 16)) << 16)
  28 
  29 /* Bit to enable IR hardware function */
  30 #define MTK_IR_EN                 BIT(0)
  31 
  32 /* Bit to restart IR receiving */
  33 #define MTK_IRCLR                 BIT(0)
  34 
  35 /* Fields containing pulse width data */
  36 #define MTK_WIDTH_MASK            (GENMASK(7, 0))
  37 
  38 /* IR threshold */
  39 #define MTK_IRTHD                0x14
  40 #define MTK_DG_CNT_MASK          (GENMASK(12, 8))
  41 #define MTK_DG_CNT(x)            ((x) << 8)
  42 
  43 /* Bit to enable interrupt */
  44 #define MTK_IRINT_EN              BIT(0)
  45 
  46 /* Bit to clear interrupt status */
  47 #define MTK_IRINT_CLR             BIT(0)
  48 
  49 /* Maximum count of samples */
  50 #define MTK_MAX_SAMPLES           0xff
  51 /* Indicate the end of IR message */
  52 #define MTK_IR_END(v, p)          ((v) == MTK_MAX_SAMPLES && (p) == 0)
  53 /* Number of registers to record the pulse width */
  54 #define MTK_CHKDATA_SZ            17
  55 /* Sample period in ns */
  56 #define MTK_IR_SAMPLE             46000
  57 
  58 enum mtk_fields {
  59         /* Register to setting software sampling period */
  60         MTK_CHK_PERIOD,
  61         /* Register to setting hardware sampling period */
  62         MTK_HW_PERIOD,
  63 };
  64 
  65 enum mtk_regs {
  66         /* Register to clear state of state machine */
  67         MTK_IRCLR_REG,
  68         /* Register containing pulse width data */
  69         MTK_CHKDATA_REG,
  70         /* Register to enable IR interrupt */
  71         MTK_IRINT_EN_REG,
  72         /* Register to ack IR interrupt */
  73         MTK_IRINT_CLR_REG
  74 };
  75 
  76 static const u32 mt7623_regs[] = {
  77         [MTK_IRCLR_REG] =       0x20,
  78         [MTK_CHKDATA_REG] =     0x88,
  79         [MTK_IRINT_EN_REG] =    0xcc,
  80         [MTK_IRINT_CLR_REG] =   0xd0,
  81 };
  82 
  83 static const u32 mt7622_regs[] = {
  84         [MTK_IRCLR_REG] =       0x18,
  85         [MTK_CHKDATA_REG] =     0x30,
  86         [MTK_IRINT_EN_REG] =    0x1c,
  87         [MTK_IRINT_CLR_REG] =   0x20,
  88 };
  89 
  90 struct mtk_field_type {
  91         u32 reg;
  92         u8 offset;
  93         u32 mask;
  94 };
  95 
  96 /*
  97  * struct mtk_ir_data - This is the structure holding all differences among
  98                         various hardwares
  99  * @regs:               The pointer to the array holding registers offset
 100  * @fields:             The pointer to the array holding fields location
 101  * @div:                The internal divisor for the based reference clock
 102  * @ok_count:           The count indicating the completion of IR data
 103  *                      receiving when count is reached
 104  * @hw_period:          The value indicating the hardware sampling period
 105  */
 106 struct mtk_ir_data {
 107         const u32 *regs;
 108         const struct mtk_field_type *fields;
 109         u8 div;
 110         u8 ok_count;
 111         u32 hw_period;
 112 };
 113 
 114 static const struct mtk_field_type mt7623_fields[] = {
 115         [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
 116         [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
 117 };
 118 
 119 static const struct mtk_field_type mt7622_fields[] = {
 120         [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
 121         [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
 122 };
 123 
 124 /*
 125  * struct mtk_ir -      This is the main datasructure for holding the state
 126  *                      of the driver
 127  * @dev:                The device pointer
 128  * @rc:                 The rc instrance
 129  * @base:               The mapped register i/o base
 130  * @irq:                The IRQ that we are using
 131  * @clk:                The clock that IR internal is using
 132  * @bus:                The clock that software decoder is using
 133  * @data:               Holding specific data for vaious platform
 134  */
 135 struct mtk_ir {
 136         struct device   *dev;
 137         struct rc_dev   *rc;
 138         void __iomem    *base;
 139         int             irq;
 140         struct clk      *clk;
 141         struct clk      *bus;
 142         const struct mtk_ir_data *data;
 143 };
 144 
 145 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
 146 {
 147         return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
 148 }
 149 
 150 static inline u32 mtk_chk_period(struct mtk_ir *ir)
 151 {
 152         u32 val;
 153 
 154         /* Period of raw software sampling in ns */
 155         val = DIV_ROUND_CLOSEST(1000000000ul,
 156                                 clk_get_rate(ir->bus) / ir->data->div);
 157 
 158         /*
 159          * Period for software decoder used in the
 160          * unit of raw software sampling
 161          */
 162         val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);
 163 
 164         dev_dbg(ir->dev, "@pwm clk  = \t%lu\n",
 165                 clk_get_rate(ir->bus) / ir->data->div);
 166         dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
 167 
 168         return val;
 169 }
 170 
 171 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
 172 {
 173         u32 tmp;
 174 
 175         tmp = __raw_readl(ir->base + reg);
 176         tmp = (tmp & ~mask) | val;
 177         __raw_writel(tmp, ir->base + reg);
 178 }
 179 
 180 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
 181 {
 182         __raw_writel(val, ir->base + reg);
 183 }
 184 
 185 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
 186 {
 187         return __raw_readl(ir->base + reg);
 188 }
 189 
 190 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
 191 {
 192         u32 val;
 193 
 194         val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
 195         mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
 196 }
 197 
 198 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
 199 {
 200         u32 val;
 201 
 202         val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
 203         mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
 204 }
 205 
 206 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
 207 {
 208         struct mtk_ir *ir = dev_id;
 209         u8  wid = 0;
 210         u32 i, j, val;
 211         struct ir_raw_event rawir = {};
 212 
 213         /*
 214          * Reset decoder state machine explicitly is required
 215          * because 1) the longest duration for space MTK IR hardware
 216          * could record is not safely long. e.g  12ms if rx resolution
 217          * is 46us by default. There is still the risk to satisfying
 218          * every decoder to reset themselves through long enough
 219          * trailing spaces and 2) the IRQ handler guarantees that
 220          * start of IR message is always contained in and starting
 221          * from register mtk_chkdata_reg(ir, i).
 222          */
 223         ir_raw_event_reset(ir->rc);
 224 
 225         /* First message must be pulse */
 226         rawir.pulse = false;
 227 
 228         /* Handle all pulse and space IR controller captures */
 229         for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
 230                 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
 231                 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
 232 
 233                 for (j = 0 ; j < 4 ; j++) {
 234                         wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
 235                         rawir.pulse = !rawir.pulse;
 236                         rawir.duration = wid * (MTK_IR_SAMPLE + 1);
 237                         ir_raw_event_store_with_filter(ir->rc, &rawir);
 238                 }
 239         }
 240 
 241         /*
 242          * The maximum number of edges the IR controller can
 243          * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
 244          * is over the limit, the last incomplete IR message would
 245          * be appended trailing space and still would be sent into
 246          * ir-rc-raw to decode. That helps it is possible that it
 247          * has enough information to decode a scancode even if the
 248          * trailing end of the message is missing.
 249          */
 250         if (!MTK_IR_END(wid, rawir.pulse)) {
 251                 rawir.pulse = false;
 252                 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
 253                 ir_raw_event_store_with_filter(ir->rc, &rawir);
 254         }
 255 
 256         ir_raw_event_handle(ir->rc);
 257 
 258         /*
 259          * Restart controller for the next receive that would
 260          * clear up all CHKDATA registers
 261          */
 262         mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
 263 
 264         /* Clear interrupt status */
 265         mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
 266                      ir->data->regs[MTK_IRINT_CLR_REG]);
 267 
 268         return IRQ_HANDLED;
 269 }
 270 
 271 static const struct mtk_ir_data mt7623_data = {
 272         .regs = mt7623_regs,
 273         .fields = mt7623_fields,
 274         .ok_count = 0xf,
 275         .hw_period = 0xff,
 276         .div    = 4,
 277 };
 278 
 279 static const struct mtk_ir_data mt7622_data = {
 280         .regs = mt7622_regs,
 281         .fields = mt7622_fields,
 282         .ok_count = 0xf,
 283         .hw_period = 0xffff,
 284         .div    = 32,
 285 };
 286 
 287 static const struct of_device_id mtk_ir_match[] = {
 288         { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
 289         { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
 290         {},
 291 };
 292 MODULE_DEVICE_TABLE(of, mtk_ir_match);
 293 
 294 static int mtk_ir_probe(struct platform_device *pdev)
 295 {
 296         struct device *dev = &pdev->dev;
 297         struct device_node *dn = dev->of_node;
 298         struct resource *res;
 299         struct mtk_ir *ir;
 300         u32 val;
 301         int ret = 0;
 302         const char *map_name;
 303 
 304         ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
 305         if (!ir)
 306                 return -ENOMEM;
 307 
 308         ir->dev = dev;
 309         ir->data = of_device_get_match_data(dev);
 310 
 311         ir->clk = devm_clk_get(dev, "clk");
 312         if (IS_ERR(ir->clk)) {
 313                 dev_err(dev, "failed to get a ir clock.\n");
 314                 return PTR_ERR(ir->clk);
 315         }
 316 
 317         ir->bus = devm_clk_get(dev, "bus");
 318         if (IS_ERR(ir->bus)) {
 319                 /*
 320                  * For compatibility with older device trees try unnamed
 321                  * ir->bus uses the same clock as ir->clock.
 322                  */
 323                 ir->bus = ir->clk;
 324         }
 325 
 326         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 327         ir->base = devm_ioremap_resource(dev, res);
 328         if (IS_ERR(ir->base))
 329                 return PTR_ERR(ir->base);
 330 
 331         ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
 332         if (!ir->rc) {
 333                 dev_err(dev, "failed to allocate device\n");
 334                 return -ENOMEM;
 335         }
 336 
 337         ir->rc->priv = ir;
 338         ir->rc->device_name = MTK_IR_DEV;
 339         ir->rc->input_phys = MTK_IR_DEV "/input0";
 340         ir->rc->input_id.bustype = BUS_HOST;
 341         ir->rc->input_id.vendor = 0x0001;
 342         ir->rc->input_id.product = 0x0001;
 343         ir->rc->input_id.version = 0x0001;
 344         map_name = of_get_property(dn, "linux,rc-map-name", NULL);
 345         ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
 346         ir->rc->dev.parent = dev;
 347         ir->rc->driver_name = MTK_IR_DEV;
 348         ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
 349         ir->rc->rx_resolution = MTK_IR_SAMPLE;
 350         ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
 351 
 352         ret = devm_rc_register_device(dev, ir->rc);
 353         if (ret) {
 354                 dev_err(dev, "failed to register rc device\n");
 355                 return ret;
 356         }
 357 
 358         platform_set_drvdata(pdev, ir);
 359 
 360         ir->irq = platform_get_irq(pdev, 0);
 361         if (ir->irq < 0)
 362                 return -ENODEV;
 363 
 364         if (clk_prepare_enable(ir->clk)) {
 365                 dev_err(dev, "try to enable ir_clk failed\n");
 366                 return -EINVAL;
 367         }
 368 
 369         if (clk_prepare_enable(ir->bus)) {
 370                 dev_err(dev, "try to enable ir_clk failed\n");
 371                 ret = -EINVAL;
 372                 goto exit_clkdisable_clk;
 373         }
 374 
 375         /*
 376          * Enable interrupt after proper hardware
 377          * setup and IRQ handler registration
 378          */
 379         mtk_irq_disable(ir, MTK_IRINT_EN);
 380 
 381         ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
 382         if (ret) {
 383                 dev_err(dev, "failed request irq\n");
 384                 goto exit_clkdisable_bus;
 385         }
 386 
 387         /*
 388          * Setup software sample period as the reference of software decoder
 389          */
 390         val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
 391                ir->data->fields[MTK_CHK_PERIOD].mask;
 392         mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
 393                      ir->data->fields[MTK_CHK_PERIOD].reg);
 394 
 395         /*
 396          * Setup hardware sampling period used to setup the proper timeout for
 397          * indicating end of IR receiving completion
 398          */
 399         val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
 400                ir->data->fields[MTK_HW_PERIOD].mask;
 401         mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
 402                      ir->data->fields[MTK_HW_PERIOD].reg);
 403 
 404         /* Set de-glitch counter */
 405         mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
 406 
 407         /* Enable IR and PWM */
 408         val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
 409         val |= MTK_OK_COUNT(ir->data->ok_count) |  MTK_PWM_EN | MTK_IR_EN;
 410         mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
 411 
 412         mtk_irq_enable(ir, MTK_IRINT_EN);
 413 
 414         dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
 415                  DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
 416 
 417         return 0;
 418 
 419 exit_clkdisable_bus:
 420         clk_disable_unprepare(ir->bus);
 421 exit_clkdisable_clk:
 422         clk_disable_unprepare(ir->clk);
 423 
 424         return ret;
 425 }
 426 
 427 static int mtk_ir_remove(struct platform_device *pdev)
 428 {
 429         struct mtk_ir *ir = platform_get_drvdata(pdev);
 430 
 431         /*
 432          * Avoid contention between remove handler and
 433          * IRQ handler so that disabling IR interrupt and
 434          * waiting for pending IRQ handler to complete
 435          */
 436         mtk_irq_disable(ir, MTK_IRINT_EN);
 437         synchronize_irq(ir->irq);
 438 
 439         clk_disable_unprepare(ir->bus);
 440         clk_disable_unprepare(ir->clk);
 441 
 442         return 0;
 443 }
 444 
 445 static struct platform_driver mtk_ir_driver = {
 446         .probe          = mtk_ir_probe,
 447         .remove         = mtk_ir_remove,
 448         .driver = {
 449                 .name = MTK_IR_DEV,
 450                 .of_match_table = mtk_ir_match,
 451         },
 452 };
 453 
 454 module_platform_driver(mtk_ir_driver);
 455 
 456 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
 457 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
 458 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/rc/mtk-cir.c

DEFINITIONS
