1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
4 *
5 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
6 */
7 #include <linux/spinlock.h>
8
9
10 /* hardware address */
11 #define ENE_STATUS 0 /* hardware status - unused */
12 #define ENE_ADDR_HI 1 /* hi byte of register address */
13 #define ENE_ADDR_LO 2 /* low byte of register address */
14 #define ENE_IO 3 /* read/write window */
15 #define ENE_IO_SIZE 4
16
17 /* 8 bytes of samples, divided in 2 packets*/
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
19 #define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
20 #define ENE_FW_PACKET_SIZE 4
21
22 /* first firmware flag register */
23 #define ENE_FW1 0xF8F8 /* flagr */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
25 #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
28 #define ENE_FW1_LED_ON 0x10 /* turn on a led */
29
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
33
34 /* second firmware flag register */
35 #define ENE_FW2 0xF8F9 /* flagw */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
39 #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
40 #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
41
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
43 #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
44
45 /* firmware RX pointer for new style buffer */
46 #define ENE_FW_RX_POINTER 0xF8FA
47
48 /* high parts of samples for fan input (8 samples)*/
49 #define ENE_FW_SMPL_BUF_FAN 0xF8FB
50 #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
51 #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
52 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
53
54 /* transmitter ports */
55 #define ENE_GPIOFS1 0xFC01
56 #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
57 #define ENE_GPIOFS8 0xFC08
58 #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
59
60 /* IRQ registers block (for revision B) */
61 #define ENEB_IRQ 0xFD09 /* IRQ number */
62 #define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
63 #define ENEB_IRQ_STATUS 0xFD80 /* irq status */
64 #define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
65
66 /* fan as input settings */
67 #define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
68 #define ENE_FAN_AS_IN1_EN 0xCD
69 #define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
70 #define ENE_FAN_AS_IN2_EN 0x03
71
72 /* IRQ registers block (for revision C,D) */
73 #define ENE_IRQ 0xFE9B /* new irq settings register */
74 #define ENE_IRQ_MASK 0x0F /* irq number mask */
75 #define ENE_IRQ_UNK_EN 0x10 /* always enabled */
76 #define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
77
78 /* CIR Config register #1 */
79 #define ENE_CIRCFG 0xFEC0
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
81 #define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
82 #define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
83 #define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
84
85 #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
86 #define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
87 #define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
88 #define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
89
90 /* CIR config register #2 */
91 #define ENE_CIRCFG2 0xFEC1
92 #define ENE_CIRCFG2_RLC 0x00
93 #define ENE_CIRCFG2_RC5 0x01
94 #define ENE_CIRCFG2_RC6 0x02
95 #define ENE_CIRCFG2_NEC 0x03
96 #define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
97 #define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
98 #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
99 #define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
100
101 /* Knobs for protocol decoding - will document when/if will use them */
102 #define ENE_CIRPF 0xFEC2
103 #define ENE_CIRHIGH 0xFEC3
104 #define ENE_CIRBIT 0xFEC4
105 #define ENE_CIRSTART 0xFEC5
106 #define ENE_CIRSTART2 0xFEC6
107
108 /* Actual register which contains RLC RX data - read by firmware */
109 #define ENE_CIRDAT_IN 0xFEC7
110
111
112 /* RLC configuration - sample period (1us resolution) + idle mode */
113 #define ENE_CIRRLC_CFG 0xFEC8
114 #define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
115 #define ENE_DEFAULT_SAMPLE_PERIOD 50
116
117 /* Two byte RLC TX buffer */
118 #define ENE_CIRRLC_OUT0 0xFEC9
119 #define ENE_CIRRLC_OUT1 0xFECA
120 #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
121 #define ENE_CIRRLC_OUT_MASK 0x7F
122
123
124 /* Carrier detect setting
125 * Low nibble - number of carrier pulses to average
126 * High nibble - number of initial carrier pulses to discard
127 */
128 #define ENE_CIRCAR_PULS 0xFECB
129
130 /* detected RX carrier period (resolution: 500 ns) */
131 #define ENE_CIRCAR_PRD 0xFECC
132 #define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
133
134 /* detected RX carrier pulse width (resolution: 500 ns) */
135 #define ENE_CIRCAR_HPRD 0xFECD
136
137 /* TX period (resolution: 500 ns, minimum 2)*/
138 #define ENE_CIRMOD_PRD 0xFECE
139 #define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
140
141 #define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
142 #define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
143
144 /* TX pulse width (resolution: 500 ns)*/
145 #define ENE_CIRMOD_HPRD 0xFECF
146
147 /* Hardware versions */
148 #define ENE_ECHV 0xFF00 /* hardware revision */
149 #define ENE_PLLFRH 0xFF16
150 #define ENE_PLLFRL 0xFF17
151 #define ENE_DEFAULT_PLL_FREQ 1000
152
153 #define ENE_ECSTS 0xFF1D
154 #define ENE_ECSTS_RSRVD 0x04
155
156 #define ENE_ECVER_MAJOR 0xFF1E /* chip version */
157 #define ENE_ECVER_MINOR 0xFF1F
158 #define ENE_HW_VER_OLD 0xFD00
159
160 /******************************************************************************/
161
162 #define ENE_DRIVER_NAME "ene_ir"
163
164 #define ENE_IRQ_RX 1
165 #define ENE_IRQ_TX 2
166
167 #define ENE_HW_B 1 /* 3926B */
168 #define ENE_HW_C 2 /* 3926C */
169 #define ENE_HW_D 3 /* 3926D or later */
170
171 #define __dbg(level, format, ...) \
172 do { \
173 if (debug >= level) \
174 pr_info(format "\n", ## __VA_ARGS__); \
175 } while (0)
176
177 #define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
178 #define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
179 #define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
180
181 struct ene_device {
182 struct pnp_dev *pnp_dev;
183 struct rc_dev *rdev;
184
185 /* hw IO settings */
186 long hw_io;
187 int irq;
188 spinlock_t hw_lock;
189
190 /* HW features */
191 int hw_revision; /* hardware revision */
192 bool hw_use_gpio_0a; /* gpio0a is demodulated input*/
193 bool hw_extra_buffer; /* hardware has 'extra buffer' */
194 bool hw_fan_input; /* fan input is IR data source */
195 bool hw_learning_and_tx_capable; /* learning & tx capable */
196 int pll_freq;
197 int buffer_len;
198
199 /* Extra RX buffer location */
200 int extra_buf1_address;
201 int extra_buf1_len;
202 int extra_buf2_address;
203 int extra_buf2_len;
204
205 /* HW state*/
206 int r_pointer; /* pointer to next sample to read */
207 int w_pointer; /* pointer to next sample hw will write */
208 bool rx_fan_input_inuse; /* is fan input in use for rx*/
209 int tx_reg; /* current reg used for TX */
210 u8 saved_conf1; /* saved FEC0 reg */
211 unsigned int tx_sample; /* current sample for TX */
212 bool tx_sample_pulse; /* current sample is pulse */
213
214 /* TX buffer */
215 unsigned *tx_buffer; /* input samples buffer*/
216 int tx_pos; /* position in that buffer */
217 int tx_len; /* current len of tx buffer */
218 int tx_done; /* done transmitting */
219 /* one more sample pending*/
220 struct completion tx_complete; /* TX completion */
221 struct timer_list tx_sim_timer;
222
223 /* TX settings */
224 int tx_period;
225 int tx_duty_cycle;
226 int transmitter_mask;
227
228 /* RX settings */
229 bool learning_mode_enabled; /* learning input enabled */
230 bool carrier_detect_enabled; /* carrier detect enabled */
231 int rx_period_adjust;
232 bool rx_enabled;
233 };
234
235 static int ene_irq_status(struct ene_device *dev);
236 static void ene_rx_read_hw_pointer(struct ene_device *dev);