drivers/media/i2c/cx25840/cx25840-ir.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
to_ir_state
count_to_clock_divider
ns_to_clock_divider
clock_divider_to_ns
carrier_freq_to_clock_divider
clock_divider_to_carrier_freq
freq_to_clock_divider
clock_divider_to_freq
count_to_lpf_count
ns_to_lpf_count
lpf_count_to_ns
lpf_count_to_us
clock_divider_to_resolution
pulse_width_count_to_ns
ns_to_pulse_width_count
pulse_width_count_to_us
ns_to_pulse_clocks
pulse_clocks_to_clock_divider
control_tx_irq_watermark
control_rx_irq_watermark
control_tx_enable
control_rx_enable
control_tx_modulation_enable
control_rx_demodulation_enable
control_rx_s_edge_detection
control_rx_s_carrier_window
control_tx_polarity_invert
txclk_tx_s_carrier
rxclk_rx_s_carrier
txclk_tx_s_max_pulse_width
rxclk_rx_s_max_pulse_width
cduty_tx_s_duty_cycle
filter_rx_s_min_width
irqenable_rx
irqenable_tx
cx25840_ir_irq_handler
cx25840_ir_rx_read
cx25840_ir_rx_g_parameters
cx25840_ir_rx_shutdown
cx25840_ir_rx_s_parameters
cx25840_ir_tx_write
cx25840_ir_tx_g_parameters
cx25840_ir_tx_shutdown
cx25840_ir_tx_s_parameters
cx25840_ir_log_status
cx25840_ir_probe
cx25840_ir_remove
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
   4  *
   5  *  Integrated Consumer Infrared Controller
   6  *
   7  *  Copyright (C) 2010  Andy Walls <awalls@md.metrocast.net>
   8  */
   9 
  10 #include <linux/slab.h>
  11 #include <linux/kfifo.h>
  12 #include <linux/module.h>
  13 #include <media/drv-intf/cx25840.h>
  14 #include <media/rc-core.h>
  15 
  16 #include "cx25840-core.h"
  17 
  18 static unsigned int ir_debug;
  19 module_param(ir_debug, int, 0644);
  20 MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
  21 
  22 #define CX25840_IR_REG_BASE     0x200
  23 
  24 #define CX25840_IR_CNTRL_REG    0x200
  25 #define CNTRL_WIN_3_3   0x00000000
  26 #define CNTRL_WIN_4_3   0x00000001
  27 #define CNTRL_WIN_3_4   0x00000002
  28 #define CNTRL_WIN_4_4   0x00000003
  29 #define CNTRL_WIN       0x00000003
  30 #define CNTRL_EDG_NONE  0x00000000
  31 #define CNTRL_EDG_FALL  0x00000004
  32 #define CNTRL_EDG_RISE  0x00000008
  33 #define CNTRL_EDG_BOTH  0x0000000C
  34 #define CNTRL_EDG       0x0000000C
  35 #define CNTRL_DMD       0x00000010
  36 #define CNTRL_MOD       0x00000020
  37 #define CNTRL_RFE       0x00000040
  38 #define CNTRL_TFE       0x00000080
  39 #define CNTRL_RXE       0x00000100
  40 #define CNTRL_TXE       0x00000200
  41 #define CNTRL_RIC       0x00000400
  42 #define CNTRL_TIC       0x00000800
  43 #define CNTRL_CPL       0x00001000
  44 #define CNTRL_LBM       0x00002000
  45 #define CNTRL_R         0x00004000
  46 
  47 #define CX25840_IR_TXCLK_REG    0x204
  48 #define TXCLK_TCD       0x0000FFFF
  49 
  50 #define CX25840_IR_RXCLK_REG    0x208
  51 #define RXCLK_RCD       0x0000FFFF
  52 
  53 #define CX25840_IR_CDUTY_REG    0x20C
  54 #define CDUTY_CDC       0x0000000F
  55 
  56 #define CX25840_IR_STATS_REG    0x210
  57 #define STATS_RTO       0x00000001
  58 #define STATS_ROR       0x00000002
  59 #define STATS_RBY       0x00000004
  60 #define STATS_TBY       0x00000008
  61 #define STATS_RSR       0x00000010
  62 #define STATS_TSR       0x00000020
  63 
  64 #define CX25840_IR_IRQEN_REG    0x214
  65 #define IRQEN_RTE       0x00000001
  66 #define IRQEN_ROE       0x00000002
  67 #define IRQEN_RSE       0x00000010
  68 #define IRQEN_TSE       0x00000020
  69 #define IRQEN_MSK       0x00000033
  70 
  71 #define CX25840_IR_FILTR_REG    0x218
  72 #define FILTR_LPF       0x0000FFFF
  73 
  74 #define CX25840_IR_FIFO_REG     0x23C
  75 #define FIFO_RXTX       0x0000FFFF
  76 #define FIFO_RXTX_LVL   0x00010000
  77 #define FIFO_RXTX_RTO   0x0001FFFF
  78 #define FIFO_RX_NDV     0x00020000
  79 #define FIFO_RX_DEPTH   8
  80 #define FIFO_TX_DEPTH   8
  81 
  82 #define CX25840_VIDCLK_FREQ     108000000 /* 108 MHz, BT.656 */
  83 #define CX25840_IR_REFCLK_FREQ  (CX25840_VIDCLK_FREQ / 2)
  84 
  85 /*
  86  * We use this union internally for convenience, but callers to tx_write
  87  * and rx_read will be expecting records of type struct ir_raw_event.
  88  * Always ensure the size of this union is dictated by struct ir_raw_event.
  89  */
  90 union cx25840_ir_fifo_rec {
  91         u32 hw_fifo_data;
  92         struct ir_raw_event ir_core_data;
  93 };
  94 
  95 #define CX25840_IR_RX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
  96 #define CX25840_IR_TX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
  97 
  98 struct cx25840_ir_state {
  99         struct i2c_client *c;
 100 
 101         struct v4l2_subdev_ir_parameters rx_params;
 102         struct mutex rx_params_lock; /* protects Rx parameter settings cache */
 103         atomic_t rxclk_divider;
 104         atomic_t rx_invert;
 105 
 106         struct kfifo rx_kfifo;
 107         spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
 108 
 109         struct v4l2_subdev_ir_parameters tx_params;
 110         struct mutex tx_params_lock; /* protects Tx parameter settings cache */
 111         atomic_t txclk_divider;
 112 };
 113 
 114 static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
 115 {
 116         struct cx25840_state *state = to_state(sd);
 117         return state ? state->ir_state : NULL;
 118 }
 119 
 120 
 121 /*
 122  * Rx and Tx Clock Divider register computations
 123  *
 124  * Note the largest clock divider value of 0xffff corresponds to:
 125  *      (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
 126  * which fits in 21 bits, so we'll use unsigned int for time arguments.
 127  */
 128 static inline u16 count_to_clock_divider(unsigned int d)
 129 {
 130         if (d > RXCLK_RCD + 1)
 131                 d = RXCLK_RCD;
 132         else if (d < 2)
 133                 d = 1;
 134         else
 135                 d--;
 136         return (u16) d;
 137 }
 138 
 139 static inline u16 ns_to_clock_divider(unsigned int ns)
 140 {
 141         return count_to_clock_divider(
 142                 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 143 }
 144 
 145 static inline unsigned int clock_divider_to_ns(unsigned int divider)
 146 {
 147         /* Period of the Rx or Tx clock in ns */
 148         return DIV_ROUND_CLOSEST((divider + 1) * 1000,
 149                                  CX25840_IR_REFCLK_FREQ / 1000000);
 150 }
 151 
 152 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
 153 {
 154         return count_to_clock_divider(
 155                           DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
 156 }
 157 
 158 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
 159 {
 160         return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
 161 }
 162 
 163 static inline u16 freq_to_clock_divider(unsigned int freq,
 164                                         unsigned int rollovers)
 165 {
 166         return count_to_clock_divider(
 167                    DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
 168 }
 169 
 170 static inline unsigned int clock_divider_to_freq(unsigned int divider,
 171                                                  unsigned int rollovers)
 172 {
 173         return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
 174                                  (divider + 1) * rollovers);
 175 }
 176 
 177 /*
 178  * Low Pass Filter register calculations
 179  *
 180  * Note the largest count value of 0xffff corresponds to:
 181  *      0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
 182  * which fits in 21 bits, so we'll use unsigned int for time arguments.
 183  */
 184 static inline u16 count_to_lpf_count(unsigned int d)
 185 {
 186         if (d > FILTR_LPF)
 187                 d = FILTR_LPF;
 188         else if (d < 4)
 189                 d = 0;
 190         return (u16) d;
 191 }
 192 
 193 static inline u16 ns_to_lpf_count(unsigned int ns)
 194 {
 195         return count_to_lpf_count(
 196                 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 197 }
 198 
 199 static inline unsigned int lpf_count_to_ns(unsigned int count)
 200 {
 201         /* Duration of the Low Pass Filter rejection window in ns */
 202         return DIV_ROUND_CLOSEST(count * 1000,
 203                                  CX25840_IR_REFCLK_FREQ / 1000000);
 204 }
 205 
 206 static inline unsigned int lpf_count_to_us(unsigned int count)
 207 {
 208         /* Duration of the Low Pass Filter rejection window in us */
 209         return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
 210 }
 211 
 212 /*
 213  * FIFO register pulse width count computations
 214  */
 215 static u32 clock_divider_to_resolution(u16 divider)
 216 {
 217         /*
 218          * Resolution is the duration of 1 tick of the readable portion of
 219          * of the pulse width counter as read from the FIFO.  The two lsb's are
 220          * not readable, hence the << 2.  This function returns ns.
 221          */
 222         return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
 223                                  CX25840_IR_REFCLK_FREQ / 1000000);
 224 }
 225 
 226 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
 227 {
 228         u64 n;
 229         u32 rem;
 230 
 231         /*
 232          * The 2 lsb's of the pulse width timer count are not readable, hence
 233          * the (count << 2) | 0x3
 234          */
 235         n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
 236         rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000);     /* / MHz => ns */
 237         if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
 238                 n++;
 239         return n;
 240 }
 241 
 242 #if 0
 243 /* Keep as we will need this for Transmit functionality */
 244 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
 245 {
 246         u64 n;
 247         u32 d;
 248         u32 rem;
 249 
 250         /*
 251          * The 2 lsb's of the pulse width timer count are not accessible, hence
 252          * the (1 << 2)
 253          */
 254         n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
 255         d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
 256         rem = do_div(n, d);
 257         if (rem >= d / 2)
 258                 n++;
 259 
 260         if (n > FIFO_RXTX)
 261                 n = FIFO_RXTX;
 262         else if (n == 0)
 263                 n = 1;
 264         return (u16) n;
 265 }
 266 
 267 #endif
 268 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
 269 {
 270         u64 n;
 271         u32 rem;
 272 
 273         /*
 274          * The 2 lsb's of the pulse width timer count are not readable, hence
 275          * the (count << 2) | 0x3
 276          */
 277         n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
 278         rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
 279         if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
 280                 n++;
 281         return (unsigned int) n;
 282 }
 283 
 284 /*
 285  * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
 286  *
 287  * The total pulse clock count is an 18 bit pulse width timer count as the most
 288  * significant part and (up to) 16 bit clock divider count as a modulus.
 289  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
 290  * width timer count's least significant bit.
 291  */
 292 static u64 ns_to_pulse_clocks(u32 ns)
 293 {
 294         u64 clocks;
 295         u32 rem;
 296         clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles  */
 297         rem = do_div(clocks, 1000);                         /* /1000 = cycles */
 298         if (rem >= 1000 / 2)
 299                 clocks++;
 300         return clocks;
 301 }
 302 
 303 static u16 pulse_clocks_to_clock_divider(u64 count)
 304 {
 305         do_div(count, (FIFO_RXTX << 2) | 0x3);
 306 
 307         /* net result needs to be rounded down and decremented by 1 */
 308         if (count > RXCLK_RCD + 1)
 309                 count = RXCLK_RCD;
 310         else if (count < 2)
 311                 count = 1;
 312         else
 313                 count--;
 314         return (u16) count;
 315 }
 316 
 317 /*
 318  * IR Control Register helpers
 319  */
 320 enum tx_fifo_watermark {
 321         TX_FIFO_HALF_EMPTY = 0,
 322         TX_FIFO_EMPTY      = CNTRL_TIC,
 323 };
 324 
 325 enum rx_fifo_watermark {
 326         RX_FIFO_HALF_FULL = 0,
 327         RX_FIFO_NOT_EMPTY = CNTRL_RIC,
 328 };
 329 
 330 static inline void control_tx_irq_watermark(struct i2c_client *c,
 331                                             enum tx_fifo_watermark level)
 332 {
 333         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
 334 }
 335 
 336 static inline void control_rx_irq_watermark(struct i2c_client *c,
 337                                             enum rx_fifo_watermark level)
 338 {
 339         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
 340 }
 341 
 342 static inline void control_tx_enable(struct i2c_client *c, bool enable)
 343 {
 344         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
 345                         enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
 346 }
 347 
 348 static inline void control_rx_enable(struct i2c_client *c, bool enable)
 349 {
 350         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
 351                         enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
 352 }
 353 
 354 static inline void control_tx_modulation_enable(struct i2c_client *c,
 355                                                 bool enable)
 356 {
 357         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
 358                         enable ? CNTRL_MOD : 0);
 359 }
 360 
 361 static inline void control_rx_demodulation_enable(struct i2c_client *c,
 362                                                   bool enable)
 363 {
 364         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
 365                         enable ? CNTRL_DMD : 0);
 366 }
 367 
 368 static inline void control_rx_s_edge_detection(struct i2c_client *c,
 369                                                u32 edge_types)
 370 {
 371         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
 372                         edge_types & CNTRL_EDG_BOTH);
 373 }
 374 
 375 static void control_rx_s_carrier_window(struct i2c_client *c,
 376                                         unsigned int carrier,
 377                                         unsigned int *carrier_range_low,
 378                                         unsigned int *carrier_range_high)
 379 {
 380         u32 v;
 381         unsigned int c16 = carrier * 16;
 382 
 383         if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
 384                 v = CNTRL_WIN_3_4;
 385                 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
 386         } else {
 387                 v = CNTRL_WIN_3_3;
 388                 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
 389         }
 390 
 391         if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
 392                 v |= CNTRL_WIN_4_3;
 393                 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
 394         } else {
 395                 v |= CNTRL_WIN_3_3;
 396                 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
 397         }
 398         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
 399 }
 400 
 401 static inline void control_tx_polarity_invert(struct i2c_client *c,
 402                                               bool invert)
 403 {
 404         cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
 405                         invert ? CNTRL_CPL : 0);
 406 }
 407 
 408 /*
 409  * IR Rx & Tx Clock Register helpers
 410  */
 411 static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
 412                                        unsigned int freq,
 413                                        u16 *divider)
 414 {
 415         *divider = carrier_freq_to_clock_divider(freq);
 416         cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
 417         return clock_divider_to_carrier_freq(*divider);
 418 }
 419 
 420 static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
 421                                        unsigned int freq,
 422                                        u16 *divider)
 423 {
 424         *divider = carrier_freq_to_clock_divider(freq);
 425         cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
 426         return clock_divider_to_carrier_freq(*divider);
 427 }
 428 
 429 static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
 430                                       u16 *divider)
 431 {
 432         u64 pulse_clocks;
 433 
 434         if (ns > IR_MAX_DURATION)
 435                 ns = IR_MAX_DURATION;
 436         pulse_clocks = ns_to_pulse_clocks(ns);
 437         *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 438         cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
 439         return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 440 }
 441 
 442 static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
 443                                       u16 *divider)
 444 {
 445         u64 pulse_clocks;
 446 
 447         if (ns > IR_MAX_DURATION)
 448                 ns = IR_MAX_DURATION;
 449         pulse_clocks = ns_to_pulse_clocks(ns);
 450         *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 451         cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
 452         return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 453 }
 454 
 455 /*
 456  * IR Tx Carrier Duty Cycle register helpers
 457  */
 458 static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
 459                                           unsigned int duty_cycle)
 460 {
 461         u32 n;
 462         n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
 463         if (n != 0)
 464                 n--;
 465         if (n > 15)
 466                 n = 15;
 467         cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
 468         return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
 469 }
 470 
 471 /*
 472  * IR Filter Register helpers
 473  */
 474 static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
 475 {
 476         u32 count = ns_to_lpf_count(min_width_ns);
 477         cx25840_write4(c, CX25840_IR_FILTR_REG, count);
 478         return lpf_count_to_ns(count);
 479 }
 480 
 481 /*
 482  * IR IRQ Enable Register helpers
 483  */
 484 static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
 485 {
 486         struct cx25840_state *state = to_state(sd);
 487 
 488         if (is_cx23885(state) || is_cx23887(state))
 489                 mask ^= IRQEN_MSK;
 490         mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
 491         cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
 492                         ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
 493 }
 494 
 495 static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
 496 {
 497         struct cx25840_state *state = to_state(sd);
 498 
 499         if (is_cx23885(state) || is_cx23887(state))
 500                 mask ^= IRQEN_MSK;
 501         mask &= IRQEN_TSE;
 502         cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
 503 }
 504 
 505 /*
 506  * V4L2 Subdevice IR Ops
 507  */
 508 int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
 509 {
 510         struct cx25840_state *state = to_state(sd);
 511         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 512         struct i2c_client *c = NULL;
 513         unsigned long flags;
 514 
 515         union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
 516         unsigned int i, j, k;
 517         u32 events, v;
 518         int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
 519         u32 cntrl, irqen, stats;
 520 
 521         *handled = false;
 522         if (ir_state == NULL)
 523                 return -ENODEV;
 524 
 525         c = ir_state->c;
 526 
 527         /* Only support the IR controller for the CX2388[57] AV Core for now */
 528         if (!(is_cx23885(state) || is_cx23887(state)))
 529                 return -ENODEV;
 530 
 531         cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
 532         irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
 533         if (is_cx23885(state) || is_cx23887(state))
 534                 irqen ^= IRQEN_MSK;
 535         stats = cx25840_read4(c, CX25840_IR_STATS_REG);
 536 
 537         tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
 538         rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
 539         rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
 540         ror = stats & STATS_ROR; /* Rx FIFO Over Run */
 541 
 542         tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
 543         rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
 544         rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
 545         roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
 546 
 547         v4l2_dbg(2, ir_debug, sd, "IR IRQ Status:  %s %s %s %s %s %s\n",
 548                  tsr ? "tsr" : "   ", rsr ? "rsr" : "   ",
 549                  rto ? "rto" : "   ", ror ? "ror" : "   ",
 550                  stats & STATS_TBY ? "tby" : "   ",
 551                  stats & STATS_RBY ? "rby" : "   ");
 552 
 553         v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
 554                  tse ? "tse" : "   ", rse ? "rse" : "   ",
 555                  rte ? "rte" : "   ", roe ? "roe" : "   ");
 556 
 557         /*
 558          * Transmitter interrupt service
 559          */
 560         if (tse && tsr) {
 561                 /*
 562                  * TODO:
 563                  * Check the watermark threshold setting
 564                  * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
 565                  * Push the data to the hardware FIFO.
 566                  * If there was nothing more to send in the tx_kfifo, disable
 567                  *      the TSR IRQ and notify the v4l2_device.
 568                  * If there was something in the tx_kfifo, check the tx_kfifo
 569                  *      level and notify the v4l2_device, if it is low.
 570                  */
 571                 /* For now, inhibit TSR interrupt until Tx is implemented */
 572                 irqenable_tx(sd, 0);
 573                 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
 574                 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
 575                 *handled = true;
 576         }
 577 
 578         /*
 579          * Receiver interrupt service
 580          */
 581         kror = 0;
 582         if ((rse && rsr) || (rte && rto)) {
 583                 /*
 584                  * Receive data on RSR to clear the STATS_RSR.
 585                  * Receive data on RTO, since we may not have yet hit the RSR
 586                  * watermark when we receive the RTO.
 587                  */
 588                 for (i = 0, v = FIFO_RX_NDV;
 589                      (v & FIFO_RX_NDV) && !kror; i = 0) {
 590                         for (j = 0;
 591                              (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
 592                                 v = cx25840_read4(c, CX25840_IR_FIFO_REG);
 593                                 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
 594                                 i++;
 595                         }
 596                         if (i == 0)
 597                                 break;
 598                         j = i * sizeof(union cx25840_ir_fifo_rec);
 599                         k = kfifo_in_locked(&ir_state->rx_kfifo,
 600                                             (unsigned char *) rx_data, j,
 601                                             &ir_state->rx_kfifo_lock);
 602                         if (k != j)
 603                                 kror++; /* rx_kfifo over run */
 604                 }
 605                 *handled = true;
 606         }
 607 
 608         events = 0;
 609         v = 0;
 610         if (kror) {
 611                 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
 612                 v4l2_err(sd, "IR receiver software FIFO overrun\n");
 613         }
 614         if (roe && ror) {
 615                 /*
 616                  * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
 617                  * the Rx FIFO Over Run status (STATS_ROR)
 618                  */
 619                 v |= CNTRL_RFE;
 620                 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
 621                 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
 622         }
 623         if (rte && rto) {
 624                 /*
 625                  * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
 626                  * the Rx Pulse Width Timer Time Out (STATS_RTO)
 627                  */
 628                 v |= CNTRL_RXE;
 629                 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
 630         }
 631         if (v) {
 632                 /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
 633                 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
 634                 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
 635                 *handled = true;
 636         }
 637         spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
 638         if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
 639                 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
 640         spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
 641 
 642         if (events)
 643                 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
 644         return 0;
 645 }
 646 
 647 /* Receiver */
 648 static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
 649                               ssize_t *num)
 650 {
 651         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 652         bool invert;
 653         u16 divider;
 654         unsigned int i, n;
 655         union cx25840_ir_fifo_rec *p;
 656         unsigned u, v, w;
 657 
 658         if (ir_state == NULL)
 659                 return -ENODEV;
 660 
 661         invert = (bool) atomic_read(&ir_state->rx_invert);
 662         divider = (u16) atomic_read(&ir_state->rxclk_divider);
 663 
 664         n = count / sizeof(union cx25840_ir_fifo_rec)
 665                 * sizeof(union cx25840_ir_fifo_rec);
 666         if (n == 0) {
 667                 *num = 0;
 668                 return 0;
 669         }
 670 
 671         n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
 672                              &ir_state->rx_kfifo_lock);
 673 
 674         n /= sizeof(union cx25840_ir_fifo_rec);
 675         *num = n * sizeof(union cx25840_ir_fifo_rec);
 676 
 677         for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
 678 
 679                 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
 680                         /* Assume RTO was because of no IR light input */
 681                         u = 0;
 682                         w = 1;
 683                 } else {
 684                         u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
 685                         if (invert)
 686                                 u = u ? 0 : 1;
 687                         w = 0;
 688                 }
 689 
 690                 v = (unsigned) pulse_width_count_to_ns(
 691                                   (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
 692                 if (v > IR_MAX_DURATION)
 693                         v = IR_MAX_DURATION;
 694 
 695                 p->ir_core_data = (struct ir_raw_event)
 696                         { .pulse = u, .duration = v, .timeout = w };
 697 
 698                 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns  %s  %s\n",
 699                          v, u ? "mark" : "space", w ? "(timed out)" : "");
 700                 if (w)
 701                         v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
 702         }
 703         return 0;
 704 }
 705 
 706 static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
 707                                       struct v4l2_subdev_ir_parameters *p)
 708 {
 709         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 710 
 711         if (ir_state == NULL)
 712                 return -ENODEV;
 713 
 714         mutex_lock(&ir_state->rx_params_lock);
 715         memcpy(p, &ir_state->rx_params,
 716                                       sizeof(struct v4l2_subdev_ir_parameters));
 717         mutex_unlock(&ir_state->rx_params_lock);
 718         return 0;
 719 }
 720 
 721 static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
 722 {
 723         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 724         struct i2c_client *c;
 725 
 726         if (ir_state == NULL)
 727                 return -ENODEV;
 728 
 729         c = ir_state->c;
 730         mutex_lock(&ir_state->rx_params_lock);
 731 
 732         /* Disable or slow down all IR Rx circuits and counters */
 733         irqenable_rx(sd, 0);
 734         control_rx_enable(c, false);
 735         control_rx_demodulation_enable(c, false);
 736         control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
 737         filter_rx_s_min_width(c, 0);
 738         cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
 739 
 740         ir_state->rx_params.shutdown = true;
 741 
 742         mutex_unlock(&ir_state->rx_params_lock);
 743         return 0;
 744 }
 745 
 746 static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
 747                                       struct v4l2_subdev_ir_parameters *p)
 748 {
 749         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 750         struct i2c_client *c;
 751         struct v4l2_subdev_ir_parameters *o;
 752         u16 rxclk_divider;
 753 
 754         if (ir_state == NULL)
 755                 return -ENODEV;
 756 
 757         if (p->shutdown)
 758                 return cx25840_ir_rx_shutdown(sd);
 759 
 760         if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 761                 return -ENOSYS;
 762 
 763         c = ir_state->c;
 764         o = &ir_state->rx_params;
 765 
 766         mutex_lock(&ir_state->rx_params_lock);
 767 
 768         o->shutdown = p->shutdown;
 769 
 770         p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 771         o->mode = p->mode;
 772 
 773         p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
 774         o->bytes_per_data_element = p->bytes_per_data_element;
 775 
 776         /* Before we tweak the hardware, we have to disable the receiver */
 777         irqenable_rx(sd, 0);
 778         control_rx_enable(c, false);
 779 
 780         control_rx_demodulation_enable(c, p->modulation);
 781         o->modulation = p->modulation;
 782 
 783         if (p->modulation) {
 784                 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
 785                                                      &rxclk_divider);
 786 
 787                 o->carrier_freq = p->carrier_freq;
 788 
 789                 p->duty_cycle = 50;
 790                 o->duty_cycle = p->duty_cycle;
 791 
 792                 control_rx_s_carrier_window(c, p->carrier_freq,
 793                                             &p->carrier_range_lower,
 794                                             &p->carrier_range_upper);
 795                 o->carrier_range_lower = p->carrier_range_lower;
 796                 o->carrier_range_upper = p->carrier_range_upper;
 797 
 798                 p->max_pulse_width =
 799                         (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
 800         } else {
 801                 p->max_pulse_width =
 802                             rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
 803                                                        &rxclk_divider);
 804         }
 805         o->max_pulse_width = p->max_pulse_width;
 806         atomic_set(&ir_state->rxclk_divider, rxclk_divider);
 807 
 808         p->noise_filter_min_width =
 809                             filter_rx_s_min_width(c, p->noise_filter_min_width);
 810         o->noise_filter_min_width = p->noise_filter_min_width;
 811 
 812         p->resolution = clock_divider_to_resolution(rxclk_divider);
 813         o->resolution = p->resolution;
 814 
 815         /* FIXME - make this dependent on resolution for better performance */
 816         control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
 817 
 818         control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
 819 
 820         o->invert_level = p->invert_level;
 821         atomic_set(&ir_state->rx_invert, p->invert_level);
 822 
 823         o->interrupt_enable = p->interrupt_enable;
 824         o->enable = p->enable;
 825         if (p->enable) {
 826                 unsigned long flags;
 827 
 828                 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
 829                 kfifo_reset(&ir_state->rx_kfifo);
 830                 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
 831                 if (p->interrupt_enable)
 832                         irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
 833                 control_rx_enable(c, p->enable);
 834         }
 835 
 836         mutex_unlock(&ir_state->rx_params_lock);
 837         return 0;
 838 }
 839 
 840 /* Transmitter */
 841 static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
 842                                ssize_t *num)
 843 {
 844         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 845 
 846         if (ir_state == NULL)
 847                 return -ENODEV;
 848 
 849 #if 0
 850         /*
 851          * FIXME - the code below is an incomplete and untested sketch of what
 852          * may need to be done.  The critical part is to get 4 (or 8) pulses
 853          * from the tx_kfifo, or converted from ns to the proper units from the
 854          * input, and push them off to the hardware Tx FIFO right away, if the
 855          * HW TX fifo needs service.  The rest can be pushed to the tx_kfifo in
 856          * a less critical timeframe.  Also watch out for overruning the
 857          * tx_kfifo - don't let it happen and let the caller know not all his
 858          * pulses were written.
 859          */
 860         u32 *ns_pulse = (u32 *) buf;
 861         unsigned int n;
 862         u32 fifo_pulse[FIFO_TX_DEPTH];
 863         u32 mark;
 864 
 865         /* Compute how much we can fit in the tx kfifo */
 866         n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
 867         n = min(n, (unsigned int) count);
 868         n /= sizeof(u32);
 869 
 870         /* FIXME - turn on Tx Fifo service interrupt
 871          * check hardware fifo level, and other stuff
 872          */
 873         for (i = 0; i < n; ) {
 874                 for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
 875                         mark = ns_pulse[i] & LEVEL_MASK;
 876                         fifo_pulse[j] = ns_to_pulse_width_count(
 877                                          ns_pulse[i] &
 878                                                ~LEVEL_MASK,
 879                                          ir_state->txclk_divider);
 880                         if (mark)
 881                                 fifo_pulse[j] &= FIFO_RXTX_LVL;
 882                         i++;
 883                 }
 884                 kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
 885                                                                j * sizeof(u32));
 886         }
 887         *num = n * sizeof(u32);
 888 #else
 889         /* For now enable the Tx FIFO Service interrupt & pretend we did work */
 890         irqenable_tx(sd, IRQEN_TSE);
 891         *num = count;
 892 #endif
 893         return 0;
 894 }
 895 
 896 static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
 897                                       struct v4l2_subdev_ir_parameters *p)
 898 {
 899         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 900 
 901         if (ir_state == NULL)
 902                 return -ENODEV;
 903 
 904         mutex_lock(&ir_state->tx_params_lock);
 905         memcpy(p, &ir_state->tx_params,
 906                                       sizeof(struct v4l2_subdev_ir_parameters));
 907         mutex_unlock(&ir_state->tx_params_lock);
 908         return 0;
 909 }
 910 
 911 static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
 912 {
 913         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 914         struct i2c_client *c;
 915 
 916         if (ir_state == NULL)
 917                 return -ENODEV;
 918 
 919         c = ir_state->c;
 920         mutex_lock(&ir_state->tx_params_lock);
 921 
 922         /* Disable or slow down all IR Tx circuits and counters */
 923         irqenable_tx(sd, 0);
 924         control_tx_enable(c, false);
 925         control_tx_modulation_enable(c, false);
 926         cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
 927 
 928         ir_state->tx_params.shutdown = true;
 929 
 930         mutex_unlock(&ir_state->tx_params_lock);
 931         return 0;
 932 }
 933 
 934 static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
 935                                       struct v4l2_subdev_ir_parameters *p)
 936 {
 937         struct cx25840_ir_state *ir_state = to_ir_state(sd);
 938         struct i2c_client *c;
 939         struct v4l2_subdev_ir_parameters *o;
 940         u16 txclk_divider;
 941 
 942         if (ir_state == NULL)
 943                 return -ENODEV;
 944 
 945         if (p->shutdown)
 946                 return cx25840_ir_tx_shutdown(sd);
 947 
 948         if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 949                 return -ENOSYS;
 950 
 951         c = ir_state->c;
 952         o = &ir_state->tx_params;
 953         mutex_lock(&ir_state->tx_params_lock);
 954 
 955         o->shutdown = p->shutdown;
 956 
 957         p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 958         o->mode = p->mode;
 959 
 960         p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
 961         o->bytes_per_data_element = p->bytes_per_data_element;
 962 
 963         /* Before we tweak the hardware, we have to disable the transmitter */
 964         irqenable_tx(sd, 0);
 965         control_tx_enable(c, false);
 966 
 967         control_tx_modulation_enable(c, p->modulation);
 968         o->modulation = p->modulation;
 969 
 970         if (p->modulation) {
 971                 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
 972                                                      &txclk_divider);
 973                 o->carrier_freq = p->carrier_freq;
 974 
 975                 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
 976                 o->duty_cycle = p->duty_cycle;
 977 
 978                 p->max_pulse_width =
 979                         (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
 980         } else {
 981                 p->max_pulse_width =
 982                             txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
 983                                                        &txclk_divider);
 984         }
 985         o->max_pulse_width = p->max_pulse_width;
 986         atomic_set(&ir_state->txclk_divider, txclk_divider);
 987 
 988         p->resolution = clock_divider_to_resolution(txclk_divider);
 989         o->resolution = p->resolution;
 990 
 991         /* FIXME - make this dependent on resolution for better performance */
 992         control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
 993 
 994         control_tx_polarity_invert(c, p->invert_carrier_sense);
 995         o->invert_carrier_sense = p->invert_carrier_sense;
 996 
 997         /*
 998          * FIXME: we don't have hardware help for IO pin level inversion
 999          * here like we have on the CX23888.
1000          * Act on this with some mix of logical inversion of data levels,
1001          * carrier polarity, and carrier duty cycle.
1002          */
1003         o->invert_level = p->invert_level;
1004 
1005         o->interrupt_enable = p->interrupt_enable;
1006         o->enable = p->enable;
1007         if (p->enable) {
1008                 /* reset tx_fifo here */
1009                 if (p->interrupt_enable)
1010                         irqenable_tx(sd, IRQEN_TSE);
1011                 control_tx_enable(c, p->enable);
1012         }
1013 
1014         mutex_unlock(&ir_state->tx_params_lock);
1015         return 0;
1016 }
1017 
1018 
1019 /*
1020  * V4L2 Subdevice Core Ops support
1021  */
1022 int cx25840_ir_log_status(struct v4l2_subdev *sd)
1023 {
1024         struct cx25840_state *state = to_state(sd);
1025         struct i2c_client *c = state->c;
1026         char *s;
1027         int i, j;
1028         u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1029 
1030         /* The CX23888 chip doesn't have an IR controller on the A/V core */
1031         if (is_cx23888(state))
1032                 return 0;
1033 
1034         cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1035         txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1036         rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1037         cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1038         stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1039         irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1040         if (is_cx23885(state) || is_cx23887(state))
1041                 irqen ^= IRQEN_MSK;
1042         filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1043 
1044         v4l2_info(sd, "IR Receiver:\n");
1045         v4l2_info(sd, "\tEnabled:                           %s\n",
1046                   cntrl & CNTRL_RXE ? "yes" : "no");
1047         v4l2_info(sd, "\tDemodulation from a carrier:       %s\n",
1048                   cntrl & CNTRL_DMD ? "enabled" : "disabled");
1049         v4l2_info(sd, "\tFIFO:                              %s\n",
1050                   cntrl & CNTRL_RFE ? "enabled" : "disabled");
1051         switch (cntrl & CNTRL_EDG) {
1052         case CNTRL_EDG_NONE:
1053                 s = "disabled";
1054                 break;
1055         case CNTRL_EDG_FALL:
1056                 s = "falling edge";
1057                 break;
1058         case CNTRL_EDG_RISE:
1059                 s = "rising edge";
1060                 break;
1061         case CNTRL_EDG_BOTH:
1062                 s = "rising & falling edges";
1063                 break;
1064         default:
1065                 s = "??? edge";
1066                 break;
1067         }
1068         v4l2_info(sd, "\tPulse timers' start/stop trigger:  %s\n", s);
1069         v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1070                   cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1071         v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1072                   cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1073         v4l2_info(sd, "\tLoopback mode:                     %s\n",
1074                   cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1075         if (cntrl & CNTRL_DMD) {
1076                 v4l2_info(sd, "\tExpected carrier (16 clocks):      %u Hz\n",
1077                           clock_divider_to_carrier_freq(rxclk));
1078                 switch (cntrl & CNTRL_WIN) {
1079                 case CNTRL_WIN_3_3:
1080                         i = 3;
1081                         j = 3;
1082                         break;
1083                 case CNTRL_WIN_4_3:
1084                         i = 4;
1085                         j = 3;
1086                         break;
1087                 case CNTRL_WIN_3_4:
1088                         i = 3;
1089                         j = 4;
1090                         break;
1091                 case CNTRL_WIN_4_4:
1092                         i = 4;
1093                         j = 4;
1094                         break;
1095                 default:
1096                         i = 0;
1097                         j = 0;
1098                         break;
1099                 }
1100                 v4l2_info(sd, "\tNext carrier edge window:          16 clocks -%1d/+%1d, %u to %u Hz\n",
1101                           i, j,
1102                           clock_divider_to_freq(rxclk, 16 + j),
1103                           clock_divider_to_freq(rxclk, 16 - i));
1104         }
1105         v4l2_info(sd, "\tMax measurable pulse width:        %u us, %llu ns\n",
1106                   pulse_width_count_to_us(FIFO_RXTX, rxclk),
1107                   pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1108         v4l2_info(sd, "\tLow pass filter:                   %s\n",
1109                   filtr ? "enabled" : "disabled");
1110         if (filtr)
1111                 v4l2_info(sd, "\tMin acceptable pulse width (LPF):  %u us, %u ns\n",
1112                           lpf_count_to_us(filtr),
1113                           lpf_count_to_ns(filtr));
1114         v4l2_info(sd, "\tPulse width timer timed-out:       %s\n",
1115                   stats & STATS_RTO ? "yes" : "no");
1116         v4l2_info(sd, "\tPulse width timer time-out intr:   %s\n",
1117                   irqen & IRQEN_RTE ? "enabled" : "disabled");
1118         v4l2_info(sd, "\tFIFO overrun:                      %s\n",
1119                   stats & STATS_ROR ? "yes" : "no");
1120         v4l2_info(sd, "\tFIFO overrun interrupt:            %s\n",
1121                   irqen & IRQEN_ROE ? "enabled" : "disabled");
1122         v4l2_info(sd, "\tBusy:                              %s\n",
1123                   stats & STATS_RBY ? "yes" : "no");
1124         v4l2_info(sd, "\tFIFO service requested:            %s\n",
1125                   stats & STATS_RSR ? "yes" : "no");
1126         v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1127                   irqen & IRQEN_RSE ? "enabled" : "disabled");
1128 
1129         v4l2_info(sd, "IR Transmitter:\n");
1130         v4l2_info(sd, "\tEnabled:                           %s\n",
1131                   cntrl & CNTRL_TXE ? "yes" : "no");
1132         v4l2_info(sd, "\tModulation onto a carrier:         %s\n",
1133                   cntrl & CNTRL_MOD ? "enabled" : "disabled");
1134         v4l2_info(sd, "\tFIFO:                              %s\n",
1135                   cntrl & CNTRL_TFE ? "enabled" : "disabled");
1136         v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1137                   cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1138         v4l2_info(sd, "\tCarrier polarity:                  %s\n",
1139                   cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1140                                     : "space:noburst mark:burst");
1141         if (cntrl & CNTRL_MOD) {
1142                 v4l2_info(sd, "\tCarrier (16 clocks):               %u Hz\n",
1143                           clock_divider_to_carrier_freq(txclk));
1144                 v4l2_info(sd, "\tCarrier duty cycle:                %2u/16\n",
1145                           cduty + 1);
1146         }
1147         v4l2_info(sd, "\tMax pulse width:                   %u us, %llu ns\n",
1148                   pulse_width_count_to_us(FIFO_RXTX, txclk),
1149                   pulse_width_count_to_ns(FIFO_RXTX, txclk));
1150         v4l2_info(sd, "\tBusy:                              %s\n",
1151                   stats & STATS_TBY ? "yes" : "no");
1152         v4l2_info(sd, "\tFIFO service requested:            %s\n",
1153                   stats & STATS_TSR ? "yes" : "no");
1154         v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1155                   irqen & IRQEN_TSE ? "enabled" : "disabled");
1156 
1157         return 0;
1158 }
1159 
1160 
1161 const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1162         .rx_read = cx25840_ir_rx_read,
1163         .rx_g_parameters = cx25840_ir_rx_g_parameters,
1164         .rx_s_parameters = cx25840_ir_rx_s_parameters,
1165 
1166         .tx_write = cx25840_ir_tx_write,
1167         .tx_g_parameters = cx25840_ir_tx_g_parameters,
1168         .tx_s_parameters = cx25840_ir_tx_s_parameters,
1169 };
1170 
1171 
1172 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1173         .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1174         .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1175 
1176         .enable = false,
1177         .interrupt_enable = false,
1178         .shutdown = true,
1179 
1180         .modulation = true,
1181         .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1182 
1183         /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1184         /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1185         .noise_filter_min_width = 333333, /* ns */
1186         .carrier_range_lower = 35000,
1187         .carrier_range_upper = 37000,
1188         .invert_level = false,
1189 };
1190 
1191 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1192         .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1193         .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1194 
1195         .enable = false,
1196         .interrupt_enable = false,
1197         .shutdown = true,
1198 
1199         .modulation = true,
1200         .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1201         .duty_cycle = 25,      /* 25 %   - RC-5 carrier */
1202         .invert_level = false,
1203         .invert_carrier_sense = false,
1204 };
1205 
1206 int cx25840_ir_probe(struct v4l2_subdev *sd)
1207 {
1208         struct cx25840_state *state = to_state(sd);
1209         struct cx25840_ir_state *ir_state;
1210         struct v4l2_subdev_ir_parameters default_params;
1211 
1212         /* Only init the IR controller for the CX2388[57] AV Core for now */
1213         if (!(is_cx23885(state) || is_cx23887(state)))
1214                 return 0;
1215 
1216         ir_state = devm_kzalloc(&state->c->dev, sizeof(*ir_state), GFP_KERNEL);
1217         if (ir_state == NULL)
1218                 return -ENOMEM;
1219 
1220         spin_lock_init(&ir_state->rx_kfifo_lock);
1221         if (kfifo_alloc(&ir_state->rx_kfifo,
1222                         CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1223                 return -ENOMEM;
1224 
1225         ir_state->c = state->c;
1226         state->ir_state = ir_state;
1227 
1228         /* Ensure no interrupts arrive yet */
1229         if (is_cx23885(state) || is_cx23887(state))
1230                 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1231         else
1232                 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1233 
1234         mutex_init(&ir_state->rx_params_lock);
1235         default_params = default_rx_params;
1236         v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1237 
1238         mutex_init(&ir_state->tx_params_lock);
1239         default_params = default_tx_params;
1240         v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1241 
1242         return 0;
1243 }
1244 
1245 int cx25840_ir_remove(struct v4l2_subdev *sd)
1246 {
1247         struct cx25840_state *state = to_state(sd);
1248         struct cx25840_ir_state *ir_state = to_ir_state(sd);
1249 
1250         if (ir_state == NULL)
1251                 return -ENODEV;
1252 
1253         cx25840_ir_rx_shutdown(sd);
1254         cx25840_ir_tx_shutdown(sd);
1255 
1256         kfifo_free(&ir_state->rx_kfifo);
1257         state->ir_state = NULL;
1258         return 0;
1259 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/media/i2c/cx25840/cx25840-ir.c

DEFINITIONS
