drivers/gpio/gpio-104-dio-48e.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
dio48e_gpio_get_direction
dio48e_gpio_direction_input
dio48e_gpio_direction_output
dio48e_gpio_get
dio48e_gpio_get_multiple
dio48e_gpio_set
dio48e_gpio_set_multiple
dio48e_irq_ack
dio48e_irq_mask
dio48e_irq_unmask
dio48e_irq_set_type
dio48e_irq_handler
dio48e_probe
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPIO driver for the ACCES 104-DIO-48E series
   4  * Copyright (C) 2016 William Breathitt Gray
   5  *
   6  * This driver supports the following ACCES devices: 104-DIO-48E and
   7  * 104-DIO-24E.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/bitops.h>
  11 #include <linux/device.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/io.h>
  15 #include <linux/ioport.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdesc.h>
  18 #include <linux/isa.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/spinlock.h>
  23 
  24 #define DIO48E_EXTENT 16
  25 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
  26 
  27 static unsigned int base[MAX_NUM_DIO48E];
  28 static unsigned int num_dio48e;
  29 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
  30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
  31 
  32 static unsigned int irq[MAX_NUM_DIO48E];
  33 module_param_hw_array(irq, uint, irq, NULL, 0);
  34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
  35 
  36 /**
  37  * struct dio48e_gpio - GPIO device private data structure
  38  * @chip:       instance of the gpio_chip
  39  * @io_state:   bit I/O state (whether bit is set to input or output)
  40  * @out_state:  output bits state
  41  * @control:    Control registers state
  42  * @lock:       synchronization lock to prevent I/O race conditions
  43  * @base:       base port address of the GPIO device
  44  * @irq_mask:   I/O bits affected by interrupts
  45  */
  46 struct dio48e_gpio {
  47         struct gpio_chip chip;
  48         unsigned char io_state[6];
  49         unsigned char out_state[6];
  50         unsigned char control[2];
  51         raw_spinlock_t lock;
  52         unsigned base;
  53         unsigned char irq_mask;
  54 };
  55 
  56 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  57 {
  58         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
  59         const unsigned port = offset / 8;
  60         const unsigned mask = BIT(offset % 8);
  61 
  62         return !!(dio48egpio->io_state[port] & mask);
  63 }
  64 
  65 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  66 {
  67         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
  68         const unsigned io_port = offset / 8;
  69         const unsigned int control_port = io_port / 3;
  70         const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
  71         unsigned long flags;
  72         unsigned control;
  73 
  74         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
  75 
  76         /* Check if configuring Port C */
  77         if (io_port == 2 || io_port == 5) {
  78                 /* Port C can be configured by nibble */
  79                 if (offset % 8 > 3) {
  80                         dio48egpio->io_state[io_port] |= 0xF0;
  81                         dio48egpio->control[control_port] |= BIT(3);
  82                 } else {
  83                         dio48egpio->io_state[io_port] |= 0x0F;
  84                         dio48egpio->control[control_port] |= BIT(0);
  85                 }
  86         } else {
  87                 dio48egpio->io_state[io_port] |= 0xFF;
  88                 if (io_port == 0 || io_port == 3)
  89                         dio48egpio->control[control_port] |= BIT(4);
  90                 else
  91                         dio48egpio->control[control_port] |= BIT(1);
  92         }
  93 
  94         control = BIT(7) | dio48egpio->control[control_port];
  95         outb(control, control_addr);
  96         control &= ~BIT(7);
  97         outb(control, control_addr);
  98 
  99         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 100 
 101         return 0;
 102 }
 103 
 104 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 105         int value)
 106 {
 107         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 108         const unsigned io_port = offset / 8;
 109         const unsigned int control_port = io_port / 3;
 110         const unsigned mask = BIT(offset % 8);
 111         const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
 112         const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
 113         unsigned long flags;
 114         unsigned control;
 115 
 116         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 117 
 118         /* Check if configuring Port C */
 119         if (io_port == 2 || io_port == 5) {
 120                 /* Port C can be configured by nibble */
 121                 if (offset % 8 > 3) {
 122                         dio48egpio->io_state[io_port] &= 0x0F;
 123                         dio48egpio->control[control_port] &= ~BIT(3);
 124                 } else {
 125                         dio48egpio->io_state[io_port] &= 0xF0;
 126                         dio48egpio->control[control_port] &= ~BIT(0);
 127                 }
 128         } else {
 129                 dio48egpio->io_state[io_port] &= 0x00;
 130                 if (io_port == 0 || io_port == 3)
 131                         dio48egpio->control[control_port] &= ~BIT(4);
 132                 else
 133                         dio48egpio->control[control_port] &= ~BIT(1);
 134         }
 135 
 136         if (value)
 137                 dio48egpio->out_state[io_port] |= mask;
 138         else
 139                 dio48egpio->out_state[io_port] &= ~mask;
 140 
 141         control = BIT(7) | dio48egpio->control[control_port];
 142         outb(control, control_addr);
 143 
 144         outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
 145 
 146         control &= ~BIT(7);
 147         outb(control, control_addr);
 148 
 149         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 150 
 151         return 0;
 152 }
 153 
 154 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
 155 {
 156         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 157         const unsigned port = offset / 8;
 158         const unsigned mask = BIT(offset % 8);
 159         const unsigned in_port = (port > 2) ? port + 1 : port;
 160         unsigned long flags;
 161         unsigned port_state;
 162 
 163         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 164 
 165         /* ensure that GPIO is set for input */
 166         if (!(dio48egpio->io_state[port] & mask)) {
 167                 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 168                 return -EINVAL;
 169         }
 170 
 171         port_state = inb(dio48egpio->base + in_port);
 172 
 173         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 174 
 175         return !!(port_state & mask);
 176 }
 177 
 178 static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
 179         unsigned long *bits)
 180 {
 181         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 182         size_t i;
 183         static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
 184         const unsigned int gpio_reg_size = 8;
 185         unsigned int bits_offset;
 186         size_t word_index;
 187         unsigned int word_offset;
 188         unsigned long word_mask;
 189         const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
 190         unsigned long port_state;
 191 
 192         /* clear bits array to a clean slate */
 193         bitmap_zero(bits, chip->ngpio);
 194 
 195         /* get bits are evaluated a gpio port register at a time */
 196         for (i = 0; i < ARRAY_SIZE(ports); i++) {
 197                 /* gpio offset in bits array */
 198                 bits_offset = i * gpio_reg_size;
 199 
 200                 /* word index for bits array */
 201                 word_index = BIT_WORD(bits_offset);
 202 
 203                 /* gpio offset within current word of bits array */
 204                 word_offset = bits_offset % BITS_PER_LONG;
 205 
 206                 /* mask of get bits for current gpio within current word */
 207                 word_mask = mask[word_index] & (port_mask << word_offset);
 208                 if (!word_mask) {
 209                         /* no get bits in this port so skip to next one */
 210                         continue;
 211                 }
 212 
 213                 /* read bits from current gpio port */
 214                 port_state = inb(dio48egpio->base + ports[i]);
 215 
 216                 /* store acquired bits at respective bits array offset */
 217                 bits[word_index] |= (port_state << word_offset) & word_mask;
 218         }
 219 
 220         return 0;
 221 }
 222 
 223 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 224 {
 225         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 226         const unsigned port = offset / 8;
 227         const unsigned mask = BIT(offset % 8);
 228         const unsigned out_port = (port > 2) ? port + 1 : port;
 229         unsigned long flags;
 230 
 231         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 232 
 233         if (value)
 234                 dio48egpio->out_state[port] |= mask;
 235         else
 236                 dio48egpio->out_state[port] &= ~mask;
 237 
 238         outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
 239 
 240         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 241 }
 242 
 243 static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
 244         unsigned long *mask, unsigned long *bits)
 245 {
 246         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 247         unsigned int i;
 248         const unsigned int gpio_reg_size = 8;
 249         unsigned int port;
 250         unsigned int out_port;
 251         unsigned int bitmask;
 252         unsigned long flags;
 253 
 254         /* set bits are evaluated a gpio register size at a time */
 255         for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
 256                 /* no more set bits in this mask word; skip to the next word */
 257                 if (!mask[BIT_WORD(i)]) {
 258                         i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
 259                         continue;
 260                 }
 261 
 262                 port = i / gpio_reg_size;
 263                 out_port = (port > 2) ? port + 1 : port;
 264                 bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
 265 
 266                 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 267 
 268                 /* update output state data and set device gpio register */
 269                 dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)];
 270                 dio48egpio->out_state[port] |= bitmask;
 271                 outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
 272 
 273                 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 274 
 275                 /* prepare for next gpio register set */
 276                 mask[BIT_WORD(i)] >>= gpio_reg_size;
 277                 bits[BIT_WORD(i)] >>= gpio_reg_size;
 278         }
 279 }
 280 
 281 static void dio48e_irq_ack(struct irq_data *data)
 282 {
 283 }
 284 
 285 static void dio48e_irq_mask(struct irq_data *data)
 286 {
 287         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 288         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 289         const unsigned long offset = irqd_to_hwirq(data);
 290         unsigned long flags;
 291 
 292         /* only bit 3 on each respective Port C supports interrupts */
 293         if (offset != 19 && offset != 43)
 294                 return;
 295 
 296         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 297 
 298         if (offset == 19)
 299                 dio48egpio->irq_mask &= ~BIT(0);
 300         else
 301                 dio48egpio->irq_mask &= ~BIT(1);
 302 
 303         if (!dio48egpio->irq_mask)
 304                 /* disable interrupts */
 305                 inb(dio48egpio->base + 0xB);
 306 
 307         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 308 }
 309 
 310 static void dio48e_irq_unmask(struct irq_data *data)
 311 {
 312         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 313         struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 314         const unsigned long offset = irqd_to_hwirq(data);
 315         unsigned long flags;
 316 
 317         /* only bit 3 on each respective Port C supports interrupts */
 318         if (offset != 19 && offset != 43)
 319                 return;
 320 
 321         raw_spin_lock_irqsave(&dio48egpio->lock, flags);
 322 
 323         if (!dio48egpio->irq_mask) {
 324                 /* enable interrupts */
 325                 outb(0x00, dio48egpio->base + 0xF);
 326                 outb(0x00, dio48egpio->base + 0xB);
 327         }
 328 
 329         if (offset == 19)
 330                 dio48egpio->irq_mask |= BIT(0);
 331         else
 332                 dio48egpio->irq_mask |= BIT(1);
 333 
 334         raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
 335 }
 336 
 337 static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
 338 {
 339         const unsigned long offset = irqd_to_hwirq(data);
 340 
 341         /* only bit 3 on each respective Port C supports interrupts */
 342         if (offset != 19 && offset != 43)
 343                 return -EINVAL;
 344 
 345         if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
 346                 return -EINVAL;
 347 
 348         return 0;
 349 }
 350 
 351 static struct irq_chip dio48e_irqchip = {
 352         .name = "104-dio-48e",
 353         .irq_ack = dio48e_irq_ack,
 354         .irq_mask = dio48e_irq_mask,
 355         .irq_unmask = dio48e_irq_unmask,
 356         .irq_set_type = dio48e_irq_set_type
 357 };
 358 
 359 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
 360 {
 361         struct dio48e_gpio *const dio48egpio = dev_id;
 362         struct gpio_chip *const chip = &dio48egpio->chip;
 363         const unsigned long irq_mask = dio48egpio->irq_mask;
 364         unsigned long gpio;
 365 
 366         for_each_set_bit(gpio, &irq_mask, 2)
 367                 generic_handle_irq(irq_find_mapping(chip->irq.domain,
 368                         19 + gpio*24));
 369 
 370         raw_spin_lock(&dio48egpio->lock);
 371 
 372         outb(0x00, dio48egpio->base + 0xF);
 373 
 374         raw_spin_unlock(&dio48egpio->lock);
 375 
 376         return IRQ_HANDLED;
 377 }
 378 
 379 #define DIO48E_NGPIO 48
 380 static const char *dio48e_names[DIO48E_NGPIO] = {
 381         "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
 382         "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
 383         "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
 384         "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
 385         "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
 386         "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
 387         "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
 388         "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
 389         "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
 390         "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
 391         "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
 392         "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
 393         "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
 394         "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
 395         "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
 396         "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
 397 };
 398 
 399 static int dio48e_probe(struct device *dev, unsigned int id)
 400 {
 401         struct dio48e_gpio *dio48egpio;
 402         const char *const name = dev_name(dev);
 403         int err;
 404 
 405         dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
 406         if (!dio48egpio)
 407                 return -ENOMEM;
 408 
 409         if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
 410                 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
 411                         base[id], base[id] + DIO48E_EXTENT);
 412                 return -EBUSY;
 413         }
 414 
 415         dio48egpio->chip.label = name;
 416         dio48egpio->chip.parent = dev;
 417         dio48egpio->chip.owner = THIS_MODULE;
 418         dio48egpio->chip.base = -1;
 419         dio48egpio->chip.ngpio = DIO48E_NGPIO;
 420         dio48egpio->chip.names = dio48e_names;
 421         dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
 422         dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
 423         dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
 424         dio48egpio->chip.get = dio48e_gpio_get;
 425         dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
 426         dio48egpio->chip.set = dio48e_gpio_set;
 427         dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
 428         dio48egpio->base = base[id];
 429 
 430         raw_spin_lock_init(&dio48egpio->lock);
 431 
 432         err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
 433         if (err) {
 434                 dev_err(dev, "GPIO registering failed (%d)\n", err);
 435                 return err;
 436         }
 437 
 438         /* initialize all GPIO as output */
 439         outb(0x80, base[id] + 3);
 440         outb(0x00, base[id]);
 441         outb(0x00, base[id] + 1);
 442         outb(0x00, base[id] + 2);
 443         outb(0x00, base[id] + 3);
 444         outb(0x80, base[id] + 7);
 445         outb(0x00, base[id] + 4);
 446         outb(0x00, base[id] + 5);
 447         outb(0x00, base[id] + 6);
 448         outb(0x00, base[id] + 7);
 449 
 450         /* disable IRQ by default */
 451         inb(base[id] + 0xB);
 452 
 453         err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0,
 454                 handle_edge_irq, IRQ_TYPE_NONE);
 455         if (err) {
 456                 dev_err(dev, "Could not add irqchip (%d)\n", err);
 457                 return err;
 458         }
 459 
 460         err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
 461                 dio48egpio);
 462         if (err) {
 463                 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
 464                 return err;
 465         }
 466 
 467         return 0;
 468 }
 469 
 470 static struct isa_driver dio48e_driver = {
 471         .probe = dio48e_probe,
 472         .driver = {
 473                 .name = "104-dio-48e"
 474         },
 475 };
 476 module_isa_driver(dio48e_driver, num_dio48e);
 477 
 478 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
 479 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
 480 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpio/gpio-104-dio-48e.c

DEFINITIONS
