This source file includes following definitions.
- zx_direction_input
- zx_direction_output
- zx_get_value
- zx_set_value
- zx_irq_type
- zx_irq_handler
- zx_irq_mask
- zx_irq_unmask
- zx_gpio_probe
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9 #include <linux/bitops.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21
22 #define ZX_GPIO_DIR 0x00
23 #define ZX_GPIO_IVE 0x04
24 #define ZX_GPIO_IV 0x08
25 #define ZX_GPIO_IEP 0x0C
26 #define ZX_GPIO_IEN 0x10
27 #define ZX_GPIO_DI 0x14
28 #define ZX_GPIO_DO1 0x18
29 #define ZX_GPIO_DO0 0x1C
30 #define ZX_GPIO_DO 0x20
31
32 #define ZX_GPIO_IM 0x28
33 #define ZX_GPIO_IE 0x2C
34
35 #define ZX_GPIO_MIS 0x30
36 #define ZX_GPIO_IC 0x34
37
38 #define ZX_GPIO_NR 16
39
40 struct zx_gpio {
41 raw_spinlock_t lock;
42
43 void __iomem *base;
44 struct gpio_chip gc;
45 };
46
47 static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
48 {
49 struct zx_gpio *chip = gpiochip_get_data(gc);
50 unsigned long flags;
51 u16 gpiodir;
52
53 if (offset >= gc->ngpio)
54 return -EINVAL;
55
56 raw_spin_lock_irqsave(&chip->lock, flags);
57 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
58 gpiodir &= ~BIT(offset);
59 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
60 raw_spin_unlock_irqrestore(&chip->lock, flags);
61
62 return 0;
63 }
64
65 static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
66 int value)
67 {
68 struct zx_gpio *chip = gpiochip_get_data(gc);
69 unsigned long flags;
70 u16 gpiodir;
71
72 if (offset >= gc->ngpio)
73 return -EINVAL;
74
75 raw_spin_lock_irqsave(&chip->lock, flags);
76 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
77 gpiodir |= BIT(offset);
78 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
79
80 if (value)
81 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
82 else
83 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
84 raw_spin_unlock_irqrestore(&chip->lock, flags);
85
86 return 0;
87 }
88
89 static int zx_get_value(struct gpio_chip *gc, unsigned offset)
90 {
91 struct zx_gpio *chip = gpiochip_get_data(gc);
92
93 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
94 }
95
96 static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
97 {
98 struct zx_gpio *chip = gpiochip_get_data(gc);
99
100 if (value)
101 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
102 else
103 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
104 }
105
106 static int zx_irq_type(struct irq_data *d, unsigned trigger)
107 {
108 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
109 struct zx_gpio *chip = gpiochip_get_data(gc);
110 int offset = irqd_to_hwirq(d);
111 unsigned long flags;
112 u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
113 u16 bit = BIT(offset);
114
115 if (offset < 0 || offset >= ZX_GPIO_NR)
116 return -EINVAL;
117
118 raw_spin_lock_irqsave(&chip->lock, flags);
119
120 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
121 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
122 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
123 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
124
125 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
126 gpiois |= bit;
127 if (trigger & IRQ_TYPE_LEVEL_HIGH)
128 gpioiev |= bit;
129 else
130 gpioiev &= ~bit;
131 } else
132 gpiois &= ~bit;
133
134 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
135 gpioi_epos |= bit;
136 gpioi_eneg |= bit;
137 } else {
138 if (trigger & IRQ_TYPE_EDGE_RISING) {
139 gpioi_epos |= bit;
140 gpioi_eneg &= ~bit;
141 } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
142 gpioi_eneg |= bit;
143 gpioi_epos &= ~bit;
144 }
145 }
146
147 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
148 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
149 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
150 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
151 raw_spin_unlock_irqrestore(&chip->lock, flags);
152
153 return 0;
154 }
155
156 static void zx_irq_handler(struct irq_desc *desc)
157 {
158 unsigned long pending;
159 int offset;
160 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
161 struct zx_gpio *chip = gpiochip_get_data(gc);
162 struct irq_chip *irqchip = irq_desc_get_chip(desc);
163
164 chained_irq_enter(irqchip, desc);
165
166 pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
167 writew_relaxed(pending, chip->base + ZX_GPIO_IC);
168 if (pending) {
169 for_each_set_bit(offset, &pending, ZX_GPIO_NR)
170 generic_handle_irq(irq_find_mapping(gc->irq.domain,
171 offset));
172 }
173
174 chained_irq_exit(irqchip, desc);
175 }
176
177 static void zx_irq_mask(struct irq_data *d)
178 {
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct zx_gpio *chip = gpiochip_get_data(gc);
181 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
182 u16 gpioie;
183
184 raw_spin_lock(&chip->lock);
185 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
186 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
187 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
188 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
189 raw_spin_unlock(&chip->lock);
190 }
191
192 static void zx_irq_unmask(struct irq_data *d)
193 {
194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
195 struct zx_gpio *chip = gpiochip_get_data(gc);
196 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
197 u16 gpioie;
198
199 raw_spin_lock(&chip->lock);
200 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
201 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
202 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
203 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
204 raw_spin_unlock(&chip->lock);
205 }
206
207 static struct irq_chip zx_irqchip = {
208 .name = "zx-gpio",
209 .irq_mask = zx_irq_mask,
210 .irq_unmask = zx_irq_unmask,
211 .irq_set_type = zx_irq_type,
212 };
213
214 static int zx_gpio_probe(struct platform_device *pdev)
215 {
216 struct device *dev = &pdev->dev;
217 struct zx_gpio *chip;
218 struct gpio_irq_chip *girq;
219 int irq, id, ret;
220
221 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
222 if (!chip)
223 return -ENOMEM;
224
225 chip->base = devm_platform_ioremap_resource(pdev, 0);
226 if (IS_ERR(chip->base))
227 return PTR_ERR(chip->base);
228
229 raw_spin_lock_init(&chip->lock);
230 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
231 chip->gc.request = gpiochip_generic_request;
232 chip->gc.free = gpiochip_generic_free;
233 }
234
235 id = of_alias_get_id(dev->of_node, "gpio");
236 chip->gc.direction_input = zx_direction_input;
237 chip->gc.direction_output = zx_direction_output;
238 chip->gc.get = zx_get_value;
239 chip->gc.set = zx_set_value;
240 chip->gc.base = ZX_GPIO_NR * id;
241 chip->gc.ngpio = ZX_GPIO_NR;
242 chip->gc.label = dev_name(dev);
243 chip->gc.parent = dev;
244 chip->gc.owner = THIS_MODULE;
245
246
247
248
249 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
250 writew_relaxed(0, chip->base + ZX_GPIO_IE);
251 irq = platform_get_irq(pdev, 0);
252 if (irq < 0)
253 return irq;
254 girq = &chip->gc.irq;
255 girq->chip = &zx_irqchip;
256 girq->parent_handler = zx_irq_handler;
257 girq->num_parents = 1;
258 girq->parents = devm_kcalloc(&pdev->dev, 1,
259 sizeof(*girq->parents),
260 GFP_KERNEL);
261 if (!girq->parents)
262 return -ENOMEM;
263 girq->parents[0] = irq;
264 girq->default_type = IRQ_TYPE_NONE;
265 girq->handler = handle_simple_irq;
266
267 ret = gpiochip_add_data(&chip->gc, chip);
268 if (ret)
269 return ret;
270
271 platform_set_drvdata(pdev, chip);
272 dev_info(dev, "ZX GPIO chip registered\n");
273
274 return 0;
275 }
276
277 static const struct of_device_id zx_gpio_match[] = {
278 {
279 .compatible = "zte,zx296702-gpio",
280 },
281 { },
282 };
283
284 static struct platform_driver zx_gpio_driver = {
285 .probe = zx_gpio_probe,
286 .driver = {
287 .name = "zx_gpio",
288 .of_match_table = of_match_ptr(zx_gpio_match),
289 },
290 };
291 builtin_platform_driver(zx_gpio_driver)