This source file includes following definitions.
- q6v5_regulator_init
- q6v5_regulator_enable
- q6v5_regulator_disable
- q6v5_clk_enable
- q6v5_clk_disable
- q6v5_pds_enable
- q6v5_pds_disable
- q6v5_xfer_mem_ownership
- q6v5_load
- q6v5_reset_assert
- q6v5_reset_deassert
- q6v5_rmb_pbl_wait
- q6v5_rmb_mba_wait
- q6v5proc_reset
- q6v5proc_halt_axi_port
- q6v5_mpss_init_image
- q6v5_phdr_valid
- q6v5_mba_load
- q6v5_mba_reclaim
- q6v5_reload_mba
- q6v5_mpss_load
- qcom_q6v5_dump_segment
- q6v5_start
- q6v5_stop
- q6v5_da_to_va
- qcom_q6v5_register_dump_segments
- qcom_msa_handover
- q6v5_init_mem
- q6v5_init_clocks
- q6v5_pds_attach
- q6v5_pds_detach
- q6v5_init_reset
- q6v5_alloc_memory_region
- q6v5_probe
- q6v5_remove
1
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8
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/remoteproc.h>
25 #include <linux/reset.h>
26 #include <linux/soc/qcom/mdt_loader.h>
27 #include <linux/iopoll.h>
28
29 #include "remoteproc_internal.h"
30 #include "qcom_common.h"
31 #include "qcom_q6v5.h"
32
33 #include <linux/qcom_scm.h>
34
35 #define MPSS_CRASH_REASON_SMEM 421
36
37
38 #define RMB_PBL_SUCCESS 0x1
39
40 #define RMB_MBA_XPU_UNLOCKED 0x1
41 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
42 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
43 #define RMB_MBA_AUTH_COMPLETE 0x4
44
45
46 #define RMB_MBA_IMAGE_REG 0x00
47 #define RMB_PBL_STATUS_REG 0x04
48 #define RMB_MBA_COMMAND_REG 0x08
49 #define RMB_MBA_STATUS_REG 0x0C
50 #define RMB_PMI_META_DATA_REG 0x10
51 #define RMB_PMI_CODE_START_REG 0x14
52 #define RMB_PMI_CODE_LENGTH_REG 0x18
53 #define RMB_MBA_MSS_STATUS 0x40
54 #define RMB_MBA_ALT_RESET 0x44
55
56 #define RMB_CMD_META_DATA_READY 0x1
57 #define RMB_CMD_LOAD_READY 0x2
58
59
60 #define QDSP6SS_RESET_REG 0x014
61 #define QDSP6SS_GFMUX_CTL_REG 0x020
62 #define QDSP6SS_PWR_CTL_REG 0x030
63 #define QDSP6SS_MEM_PWR_CTL 0x0B0
64 #define QDSP6SS_STRAP_ACC 0x110
65
66
67 #define AXI_HALTREQ_REG 0x0
68 #define AXI_HALTACK_REG 0x4
69 #define AXI_IDLE_REG 0x8
70
71 #define HALT_ACK_TIMEOUT_MS 100
72
73
74 #define Q6SS_STOP_CORE BIT(0)
75 #define Q6SS_CORE_ARES BIT(1)
76 #define Q6SS_BUS_ARES_ENABLE BIT(2)
77
78
79 #define Q6SS_CLK_ENABLE BIT(1)
80
81
82 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
83 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
84 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
85 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
86 #define Q6SS_ETB_SLP_NRET_N BIT(17)
87 #define Q6SS_L2DATA_STBY_N BIT(18)
88 #define Q6SS_SLP_RET_N BIT(19)
89 #define Q6SS_CLAMP_IO BIT(20)
90 #define QDSS_BHS_ON BIT(21)
91 #define QDSS_LDO_BYP BIT(22)
92
93
94 #define QDSP6v56_LDO_BYP BIT(25)
95 #define QDSP6v56_BHS_ON BIT(24)
96 #define QDSP6v56_CLAMP_WL BIT(21)
97 #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
98 #define HALT_CHECK_MAX_LOOPS 200
99 #define QDSP6SS_XO_CBCR 0x0038
100 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
101
102
103 #define QDSP6SS_SLEEP 0x3C
104 #define QDSP6SS_BOOT_CORE_START 0x400
105 #define QDSP6SS_BOOT_CMD 0x404
106 #define SLEEP_CHECK_MAX_LOOPS 200
107 #define BOOT_FSM_TIMEOUT 10000
108
109 struct reg_info {
110 struct regulator *reg;
111 int uV;
112 int uA;
113 };
114
115 struct qcom_mss_reg_res {
116 const char *supply;
117 int uV;
118 int uA;
119 };
120
121 struct rproc_hexagon_res {
122 const char *hexagon_mba_image;
123 struct qcom_mss_reg_res *proxy_supply;
124 struct qcom_mss_reg_res *active_supply;
125 char **proxy_clk_names;
126 char **reset_clk_names;
127 char **active_clk_names;
128 char **active_pd_names;
129 char **proxy_pd_names;
130 int version;
131 bool need_mem_protection;
132 bool has_alt_reset;
133 };
134
135 struct q6v5 {
136 struct device *dev;
137 struct rproc *rproc;
138
139 void __iomem *reg_base;
140 void __iomem *rmb_base;
141
142 struct regmap *halt_map;
143 u32 halt_q6;
144 u32 halt_modem;
145 u32 halt_nc;
146
147 struct reset_control *mss_restart;
148 struct reset_control *pdc_reset;
149
150 struct qcom_q6v5 q6v5;
151
152 struct clk *active_clks[8];
153 struct clk *reset_clks[4];
154 struct clk *proxy_clks[4];
155 struct device *active_pds[1];
156 struct device *proxy_pds[3];
157 int active_clk_count;
158 int reset_clk_count;
159 int proxy_clk_count;
160 int active_pd_count;
161 int proxy_pd_count;
162
163 struct reg_info active_regs[1];
164 struct reg_info proxy_regs[3];
165 int active_reg_count;
166 int proxy_reg_count;
167
168 bool running;
169
170 bool dump_mba_loaded;
171 unsigned long dump_segment_mask;
172 unsigned long dump_complete_mask;
173
174 phys_addr_t mba_phys;
175 void *mba_region;
176 size_t mba_size;
177
178 phys_addr_t mpss_phys;
179 phys_addr_t mpss_reloc;
180 void *mpss_region;
181 size_t mpss_size;
182
183 struct qcom_rproc_glink glink_subdev;
184 struct qcom_rproc_subdev smd_subdev;
185 struct qcom_rproc_ssr ssr_subdev;
186 struct qcom_sysmon *sysmon;
187 bool need_mem_protection;
188 bool has_alt_reset;
189 int mpss_perm;
190 int mba_perm;
191 const char *hexagon_mdt_image;
192 int version;
193 };
194
195 enum {
196 MSS_MSM8916,
197 MSS_MSM8974,
198 MSS_MSM8996,
199 MSS_SDM845,
200 };
201
202 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
203 const struct qcom_mss_reg_res *reg_res)
204 {
205 int rc;
206 int i;
207
208 if (!reg_res)
209 return 0;
210
211 for (i = 0; reg_res[i].supply; i++) {
212 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
213 if (IS_ERR(regs[i].reg)) {
214 rc = PTR_ERR(regs[i].reg);
215 if (rc != -EPROBE_DEFER)
216 dev_err(dev, "Failed to get %s\n regulator",
217 reg_res[i].supply);
218 return rc;
219 }
220
221 regs[i].uV = reg_res[i].uV;
222 regs[i].uA = reg_res[i].uA;
223 }
224
225 return i;
226 }
227
228 static int q6v5_regulator_enable(struct q6v5 *qproc,
229 struct reg_info *regs, int count)
230 {
231 int ret;
232 int i;
233
234 for (i = 0; i < count; i++) {
235 if (regs[i].uV > 0) {
236 ret = regulator_set_voltage(regs[i].reg,
237 regs[i].uV, INT_MAX);
238 if (ret) {
239 dev_err(qproc->dev,
240 "Failed to request voltage for %d.\n",
241 i);
242 goto err;
243 }
244 }
245
246 if (regs[i].uA > 0) {
247 ret = regulator_set_load(regs[i].reg,
248 regs[i].uA);
249 if (ret < 0) {
250 dev_err(qproc->dev,
251 "Failed to set regulator mode\n");
252 goto err;
253 }
254 }
255
256 ret = regulator_enable(regs[i].reg);
257 if (ret) {
258 dev_err(qproc->dev, "Regulator enable failed\n");
259 goto err;
260 }
261 }
262
263 return 0;
264 err:
265 for (; i >= 0; i--) {
266 if (regs[i].uV > 0)
267 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
268
269 if (regs[i].uA > 0)
270 regulator_set_load(regs[i].reg, 0);
271
272 regulator_disable(regs[i].reg);
273 }
274
275 return ret;
276 }
277
278 static void q6v5_regulator_disable(struct q6v5 *qproc,
279 struct reg_info *regs, int count)
280 {
281 int i;
282
283 for (i = 0; i < count; i++) {
284 if (regs[i].uV > 0)
285 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
286
287 if (regs[i].uA > 0)
288 regulator_set_load(regs[i].reg, 0);
289
290 regulator_disable(regs[i].reg);
291 }
292 }
293
294 static int q6v5_clk_enable(struct device *dev,
295 struct clk **clks, int count)
296 {
297 int rc;
298 int i;
299
300 for (i = 0; i < count; i++) {
301 rc = clk_prepare_enable(clks[i]);
302 if (rc) {
303 dev_err(dev, "Clock enable failed\n");
304 goto err;
305 }
306 }
307
308 return 0;
309 err:
310 for (i--; i >= 0; i--)
311 clk_disable_unprepare(clks[i]);
312
313 return rc;
314 }
315
316 static void q6v5_clk_disable(struct device *dev,
317 struct clk **clks, int count)
318 {
319 int i;
320
321 for (i = 0; i < count; i++)
322 clk_disable_unprepare(clks[i]);
323 }
324
325 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
326 size_t pd_count)
327 {
328 int ret;
329 int i;
330
331 for (i = 0; i < pd_count; i++) {
332 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
333 ret = pm_runtime_get_sync(pds[i]);
334 if (ret < 0)
335 goto unroll_pd_votes;
336 }
337
338 return 0;
339
340 unroll_pd_votes:
341 for (i--; i >= 0; i--) {
342 dev_pm_genpd_set_performance_state(pds[i], 0);
343 pm_runtime_put(pds[i]);
344 }
345
346 return ret;
347 };
348
349 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
350 size_t pd_count)
351 {
352 int i;
353
354 for (i = 0; i < pd_count; i++) {
355 dev_pm_genpd_set_performance_state(pds[i], 0);
356 pm_runtime_put(pds[i]);
357 }
358 }
359
360 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
361 bool remote_owner, phys_addr_t addr,
362 size_t size)
363 {
364 struct qcom_scm_vmperm next;
365
366 if (!qproc->need_mem_protection)
367 return 0;
368 if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
369 return 0;
370 if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
371 return 0;
372
373 next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
374 next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
375
376 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
377 current_perm, &next, 1);
378 }
379
380 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
381 {
382 struct q6v5 *qproc = rproc->priv;
383
384 memcpy(qproc->mba_region, fw->data, fw->size);
385
386 return 0;
387 }
388
389 static int q6v5_reset_assert(struct q6v5 *qproc)
390 {
391 int ret;
392
393 if (qproc->has_alt_reset) {
394 reset_control_assert(qproc->pdc_reset);
395 ret = reset_control_reset(qproc->mss_restart);
396 reset_control_deassert(qproc->pdc_reset);
397 } else {
398 ret = reset_control_assert(qproc->mss_restart);
399 }
400
401 return ret;
402 }
403
404 static int q6v5_reset_deassert(struct q6v5 *qproc)
405 {
406 int ret;
407
408 if (qproc->has_alt_reset) {
409 reset_control_assert(qproc->pdc_reset);
410 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
411 ret = reset_control_reset(qproc->mss_restart);
412 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
413 reset_control_deassert(qproc->pdc_reset);
414 } else {
415 ret = reset_control_deassert(qproc->mss_restart);
416 }
417
418 return ret;
419 }
420
421 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
422 {
423 unsigned long timeout;
424 s32 val;
425
426 timeout = jiffies + msecs_to_jiffies(ms);
427 for (;;) {
428 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
429 if (val)
430 break;
431
432 if (time_after(jiffies, timeout))
433 return -ETIMEDOUT;
434
435 msleep(1);
436 }
437
438 return val;
439 }
440
441 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
442 {
443
444 unsigned long timeout;
445 s32 val;
446
447 timeout = jiffies + msecs_to_jiffies(ms);
448 for (;;) {
449 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
450 if (val < 0)
451 break;
452
453 if (!status && val)
454 break;
455 else if (status && val == status)
456 break;
457
458 if (time_after(jiffies, timeout))
459 return -ETIMEDOUT;
460
461 msleep(1);
462 }
463
464 return val;
465 }
466
467 static int q6v5proc_reset(struct q6v5 *qproc)
468 {
469 u32 val;
470 int ret;
471 int i;
472
473 if (qproc->version == MSS_SDM845) {
474 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
475 val |= 0x1;
476 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
477
478 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
479 val, !(val & BIT(31)), 1,
480 SLEEP_CHECK_MAX_LOOPS);
481 if (ret) {
482 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
483 return -ETIMEDOUT;
484 }
485
486
487 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
488
489 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
490
491 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
492 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
493 if (ret) {
494 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
495
496 q6v5_reset_deassert(qproc);
497 return ret;
498 }
499
500 goto pbl_wait;
501 } else if (qproc->version == MSS_MSM8996) {
502
503 writel(QDSP6SS_ACC_OVERRIDE_VAL,
504 qproc->reg_base + QDSP6SS_STRAP_ACC);
505
506
507 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
508 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
509 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
510
511
512 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
513 val |= 0x1;
514 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
515
516
517 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
518 val, !(val & BIT(31)), 1,
519 HALT_CHECK_MAX_LOOPS);
520 if (ret) {
521 dev_err(qproc->dev,
522 "xo cbcr enabling timed out (rc:%d)\n", ret);
523 return ret;
524 }
525
526 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
527 val |= QDSP6v56_BHS_ON;
528 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
529 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
530 udelay(1);
531
532
533 val |= QDSP6v56_LDO_BYP;
534 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
535
536
537 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
538 val &= ~QDSP6v56_CLAMP_QMC_MEM;
539 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
540
541
542 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
543 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
544
545
546 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
547 for (i = 19; i >= 0; i--) {
548 val |= BIT(i);
549 writel(val, qproc->reg_base +
550 QDSP6SS_MEM_PWR_CTL);
551
552
553
554
555
556 val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
557 udelay(1);
558 }
559
560 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
561 val &= ~QDSP6v56_CLAMP_WL;
562 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
563 } else {
564
565 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
566 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
567 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
568
569
570 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
571 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
572 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
573 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
574 udelay(1);
575
576
577
578
579 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
580 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
581 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
582 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
583 val |= Q6SS_L2DATA_SLP_NRET_N_2;
584 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
585 val |= Q6SS_L2DATA_SLP_NRET_N_1;
586 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
587 val |= Q6SS_L2DATA_SLP_NRET_N_0;
588 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
589 }
590
591 val &= ~Q6SS_CLAMP_IO;
592 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
593
594
595 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
596 val &= ~Q6SS_CORE_ARES;
597 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
598
599
600 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
601 val |= Q6SS_CLK_ENABLE;
602 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
603
604
605 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
606 val &= ~Q6SS_STOP_CORE;
607 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
608
609 pbl_wait:
610
611 ret = q6v5_rmb_pbl_wait(qproc, 1000);
612 if (ret == -ETIMEDOUT) {
613 dev_err(qproc->dev, "PBL boot timed out\n");
614 } else if (ret != RMB_PBL_SUCCESS) {
615 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
616 ret = -EINVAL;
617 } else {
618 ret = 0;
619 }
620
621 return ret;
622 }
623
624 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
625 struct regmap *halt_map,
626 u32 offset)
627 {
628 unsigned long timeout;
629 unsigned int val;
630 int ret;
631
632
633 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
634 if (!ret && val)
635 return;
636
637
638 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
639
640
641 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
642 for (;;) {
643 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
644 if (ret || val || time_after(jiffies, timeout))
645 break;
646
647 msleep(1);
648 }
649
650 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
651 if (ret || !val)
652 dev_err(qproc->dev, "port failed halt\n");
653
654
655 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
656 }
657
658 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
659 {
660 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
661 dma_addr_t phys;
662 void *metadata;
663 int mdata_perm;
664 int xferop_ret;
665 size_t size;
666 void *ptr;
667 int ret;
668
669 metadata = qcom_mdt_read_metadata(fw, &size);
670 if (IS_ERR(metadata))
671 return PTR_ERR(metadata);
672
673 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
674 if (!ptr) {
675 kfree(metadata);
676 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
677 return -ENOMEM;
678 }
679
680 memcpy(ptr, metadata, size);
681
682
683 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
684 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, phys, size);
685 if (ret) {
686 dev_err(qproc->dev,
687 "assigning Q6 access to metadata failed: %d\n", ret);
688 ret = -EAGAIN;
689 goto free_dma_attrs;
690 }
691
692 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
693 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
694
695 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
696 if (ret == -ETIMEDOUT)
697 dev_err(qproc->dev, "MPSS header authentication timed out\n");
698 else if (ret < 0)
699 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
700
701
702 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, phys, size);
703 if (xferop_ret)
704 dev_warn(qproc->dev,
705 "mdt buffer not reclaimed system may become unstable\n");
706
707 free_dma_attrs:
708 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
709 kfree(metadata);
710
711 return ret < 0 ? ret : 0;
712 }
713
714 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
715 {
716 if (phdr->p_type != PT_LOAD)
717 return false;
718
719 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
720 return false;
721
722 if (!phdr->p_memsz)
723 return false;
724
725 return true;
726 }
727
728 static int q6v5_mba_load(struct q6v5 *qproc)
729 {
730 int ret;
731 int xfermemop_ret;
732
733 qcom_q6v5_prepare(&qproc->q6v5);
734
735 ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
736 if (ret < 0) {
737 dev_err(qproc->dev, "failed to enable active power domains\n");
738 goto disable_irqs;
739 }
740
741 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
742 if (ret < 0) {
743 dev_err(qproc->dev, "failed to enable proxy power domains\n");
744 goto disable_active_pds;
745 }
746
747 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
748 qproc->proxy_reg_count);
749 if (ret) {
750 dev_err(qproc->dev, "failed to enable proxy supplies\n");
751 goto disable_proxy_pds;
752 }
753
754 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
755 qproc->proxy_clk_count);
756 if (ret) {
757 dev_err(qproc->dev, "failed to enable proxy clocks\n");
758 goto disable_proxy_reg;
759 }
760
761 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
762 qproc->active_reg_count);
763 if (ret) {
764 dev_err(qproc->dev, "failed to enable supplies\n");
765 goto disable_proxy_clk;
766 }
767
768 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
769 qproc->reset_clk_count);
770 if (ret) {
771 dev_err(qproc->dev, "failed to enable reset clocks\n");
772 goto disable_vdd;
773 }
774
775 ret = q6v5_reset_deassert(qproc);
776 if (ret) {
777 dev_err(qproc->dev, "failed to deassert mss restart\n");
778 goto disable_reset_clks;
779 }
780
781 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
782 qproc->active_clk_count);
783 if (ret) {
784 dev_err(qproc->dev, "failed to enable clocks\n");
785 goto assert_reset;
786 }
787
788
789 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
790 qproc->mba_phys, qproc->mba_size);
791 if (ret) {
792 dev_err(qproc->dev,
793 "assigning Q6 access to mba memory failed: %d\n", ret);
794 goto disable_active_clks;
795 }
796
797 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
798
799 ret = q6v5proc_reset(qproc);
800 if (ret)
801 goto reclaim_mba;
802
803 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
804 if (ret == -ETIMEDOUT) {
805 dev_err(qproc->dev, "MBA boot timed out\n");
806 goto halt_axi_ports;
807 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
808 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
809 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
810 ret = -EINVAL;
811 goto halt_axi_ports;
812 }
813
814 qproc->dump_mba_loaded = true;
815 return 0;
816
817 halt_axi_ports:
818 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
819 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
820 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
821
822 reclaim_mba:
823 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
824 qproc->mba_phys,
825 qproc->mba_size);
826 if (xfermemop_ret) {
827 dev_err(qproc->dev,
828 "Failed to reclaim mba buffer, system may become unstable\n");
829 }
830
831 disable_active_clks:
832 q6v5_clk_disable(qproc->dev, qproc->active_clks,
833 qproc->active_clk_count);
834 assert_reset:
835 q6v5_reset_assert(qproc);
836 disable_reset_clks:
837 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
838 qproc->reset_clk_count);
839 disable_vdd:
840 q6v5_regulator_disable(qproc, qproc->active_regs,
841 qproc->active_reg_count);
842 disable_proxy_clk:
843 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
844 qproc->proxy_clk_count);
845 disable_proxy_reg:
846 q6v5_regulator_disable(qproc, qproc->proxy_regs,
847 qproc->proxy_reg_count);
848 disable_proxy_pds:
849 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
850 disable_active_pds:
851 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
852 disable_irqs:
853 qcom_q6v5_unprepare(&qproc->q6v5);
854
855 return ret;
856 }
857
858 static void q6v5_mba_reclaim(struct q6v5 *qproc)
859 {
860 int ret;
861 u32 val;
862
863 qproc->dump_mba_loaded = false;
864
865 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
866 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
867 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
868 if (qproc->version == MSS_MSM8996) {
869
870
871
872 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
873 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
874 QDSP6v56_CLAMP_QMC_MEM;
875 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
876 }
877
878 q6v5_reset_assert(qproc);
879
880 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
881 qproc->reset_clk_count);
882 q6v5_clk_disable(qproc->dev, qproc->active_clks,
883 qproc->active_clk_count);
884 q6v5_regulator_disable(qproc, qproc->active_regs,
885 qproc->active_reg_count);
886 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
887
888
889
890
891 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
892 qproc->mba_phys,
893 qproc->mba_size);
894 WARN_ON(ret);
895
896 ret = qcom_q6v5_unprepare(&qproc->q6v5);
897 if (ret) {
898 q6v5_pds_disable(qproc, qproc->proxy_pds,
899 qproc->proxy_pd_count);
900 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
901 qproc->proxy_clk_count);
902 q6v5_regulator_disable(qproc, qproc->proxy_regs,
903 qproc->proxy_reg_count);
904 }
905 }
906
907 static int q6v5_reload_mba(struct rproc *rproc)
908 {
909 struct q6v5 *qproc = rproc->priv;
910 const struct firmware *fw;
911 int ret;
912
913 ret = request_firmware(&fw, rproc->firmware, qproc->dev);
914 if (ret < 0)
915 return ret;
916
917 q6v5_load(rproc, fw);
918 ret = q6v5_mba_load(qproc);
919 release_firmware(fw);
920
921 return ret;
922 }
923
924 static int q6v5_mpss_load(struct q6v5 *qproc)
925 {
926 const struct elf32_phdr *phdrs;
927 const struct elf32_phdr *phdr;
928 const struct firmware *seg_fw;
929 const struct firmware *fw;
930 struct elf32_hdr *ehdr;
931 phys_addr_t mpss_reloc;
932 phys_addr_t boot_addr;
933 phys_addr_t min_addr = PHYS_ADDR_MAX;
934 phys_addr_t max_addr = 0;
935 bool relocate = false;
936 char *fw_name;
937 size_t fw_name_len;
938 ssize_t offset;
939 size_t size = 0;
940 void *ptr;
941 int ret;
942 int i;
943
944 fw_name_len = strlen(qproc->hexagon_mdt_image);
945 if (fw_name_len <= 4)
946 return -EINVAL;
947
948 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
949 if (!fw_name)
950 return -ENOMEM;
951
952 ret = request_firmware(&fw, fw_name, qproc->dev);
953 if (ret < 0) {
954 dev_err(qproc->dev, "unable to load %s\n", fw_name);
955 goto out;
956 }
957
958
959 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
960
961 ret = q6v5_mpss_init_image(qproc, fw);
962 if (ret)
963 goto release_firmware;
964
965 ehdr = (struct elf32_hdr *)fw->data;
966 phdrs = (struct elf32_phdr *)(ehdr + 1);
967
968 for (i = 0; i < ehdr->e_phnum; i++) {
969 phdr = &phdrs[i];
970
971 if (!q6v5_phdr_valid(phdr))
972 continue;
973
974 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
975 relocate = true;
976
977 if (phdr->p_paddr < min_addr)
978 min_addr = phdr->p_paddr;
979
980 if (phdr->p_paddr + phdr->p_memsz > max_addr)
981 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
982 }
983
984
985
986
987
988
989 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
990 qproc->mpss_phys, qproc->mpss_size);
991
992 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
993 qproc->mpss_reloc = mpss_reloc;
994
995 for (i = 0; i < ehdr->e_phnum; i++) {
996 phdr = &phdrs[i];
997
998 if (!q6v5_phdr_valid(phdr))
999 continue;
1000
1001 offset = phdr->p_paddr - mpss_reloc;
1002 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1003 dev_err(qproc->dev, "segment outside memory range\n");
1004 ret = -EINVAL;
1005 goto release_firmware;
1006 }
1007
1008 ptr = qproc->mpss_region + offset;
1009
1010 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1011
1012 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1013 dev_err(qproc->dev,
1014 "failed to load segment %d from truncated file %s\n",
1015 i, fw_name);
1016 ret = -EINVAL;
1017 goto release_firmware;
1018 }
1019
1020 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1021 } else if (phdr->p_filesz) {
1022
1023 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1024 ret = request_firmware(&seg_fw, fw_name, qproc->dev);
1025 if (ret) {
1026 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1027 goto release_firmware;
1028 }
1029
1030 memcpy(ptr, seg_fw->data, seg_fw->size);
1031
1032 release_firmware(seg_fw);
1033 }
1034
1035 if (phdr->p_memsz > phdr->p_filesz) {
1036 memset(ptr + phdr->p_filesz, 0,
1037 phdr->p_memsz - phdr->p_filesz);
1038 }
1039 size += phdr->p_memsz;
1040 }
1041
1042
1043 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
1044 qproc->mpss_phys, qproc->mpss_size);
1045 if (ret) {
1046 dev_err(qproc->dev,
1047 "assigning Q6 access to mpss memory failed: %d\n", ret);
1048 ret = -EAGAIN;
1049 goto release_firmware;
1050 }
1051
1052 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1053 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1054 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1055 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1056
1057 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1058 if (ret == -ETIMEDOUT)
1059 dev_err(qproc->dev, "MPSS authentication timed out\n");
1060 else if (ret < 0)
1061 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1062
1063 release_firmware:
1064 release_firmware(fw);
1065 out:
1066 kfree(fw_name);
1067
1068 return ret < 0 ? ret : 0;
1069 }
1070
1071 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1072 struct rproc_dump_segment *segment,
1073 void *dest)
1074 {
1075 int ret = 0;
1076 struct q6v5 *qproc = rproc->priv;
1077 unsigned long mask = BIT((unsigned long)segment->priv);
1078 void *ptr = rproc_da_to_va(rproc, segment->da, segment->size);
1079
1080
1081 if (!qproc->dump_mba_loaded) {
1082 ret = q6v5_reload_mba(rproc);
1083 if (!ret) {
1084
1085 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1086 false,
1087 qproc->mpss_phys,
1088 qproc->mpss_size);
1089 }
1090 }
1091
1092 if (!ptr || ret)
1093 memset(dest, 0xff, segment->size);
1094 else
1095 memcpy(dest, ptr, segment->size);
1096
1097 qproc->dump_segment_mask |= mask;
1098
1099
1100 if (qproc->dump_segment_mask == qproc->dump_complete_mask) {
1101 if (qproc->dump_mba_loaded) {
1102
1103 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1104 true,
1105 qproc->mpss_phys,
1106 qproc->mpss_size);
1107 q6v5_mba_reclaim(qproc);
1108 }
1109 }
1110 }
1111
1112 static int q6v5_start(struct rproc *rproc)
1113 {
1114 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1115 int xfermemop_ret;
1116 int ret;
1117
1118 ret = q6v5_mba_load(qproc);
1119 if (ret)
1120 return ret;
1121
1122 dev_info(qproc->dev, "MBA booted, loading mpss\n");
1123
1124 ret = q6v5_mpss_load(qproc);
1125 if (ret)
1126 goto reclaim_mpss;
1127
1128 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1129 if (ret == -ETIMEDOUT) {
1130 dev_err(qproc->dev, "start timed out\n");
1131 goto reclaim_mpss;
1132 }
1133
1134 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
1135 qproc->mba_phys,
1136 qproc->mba_size);
1137 if (xfermemop_ret)
1138 dev_err(qproc->dev,
1139 "Failed to reclaim mba buffer system may become unstable\n");
1140
1141
1142 qproc->dump_segment_mask = 0;
1143 qproc->running = true;
1144
1145 return 0;
1146
1147 reclaim_mpss:
1148 q6v5_mba_reclaim(qproc);
1149
1150 return ret;
1151 }
1152
1153 static int q6v5_stop(struct rproc *rproc)
1154 {
1155 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1156 int ret;
1157
1158 qproc->running = false;
1159
1160 ret = qcom_q6v5_request_stop(&qproc->q6v5);
1161 if (ret == -ETIMEDOUT)
1162 dev_err(qproc->dev, "timed out on wait\n");
1163
1164 q6v5_mba_reclaim(qproc);
1165
1166 return 0;
1167 }
1168
1169 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
1170 {
1171 struct q6v5 *qproc = rproc->priv;
1172 int offset;
1173
1174 offset = da - qproc->mpss_reloc;
1175 if (offset < 0 || offset + len > qproc->mpss_size)
1176 return NULL;
1177
1178 return qproc->mpss_region + offset;
1179 }
1180
1181 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1182 const struct firmware *mba_fw)
1183 {
1184 const struct firmware *fw;
1185 const struct elf32_phdr *phdrs;
1186 const struct elf32_phdr *phdr;
1187 const struct elf32_hdr *ehdr;
1188 struct q6v5 *qproc = rproc->priv;
1189 unsigned long i;
1190 int ret;
1191
1192 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1193 if (ret < 0) {
1194 dev_err(qproc->dev, "unable to load %s\n",
1195 qproc->hexagon_mdt_image);
1196 return ret;
1197 }
1198
1199 ehdr = (struct elf32_hdr *)fw->data;
1200 phdrs = (struct elf32_phdr *)(ehdr + 1);
1201 qproc->dump_complete_mask = 0;
1202
1203 for (i = 0; i < ehdr->e_phnum; i++) {
1204 phdr = &phdrs[i];
1205
1206 if (!q6v5_phdr_valid(phdr))
1207 continue;
1208
1209 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1210 phdr->p_memsz,
1211 qcom_q6v5_dump_segment,
1212 (void *)i);
1213 if (ret)
1214 break;
1215
1216 qproc->dump_complete_mask |= BIT(i);
1217 }
1218
1219 release_firmware(fw);
1220 return ret;
1221 }
1222
1223 static const struct rproc_ops q6v5_ops = {
1224 .start = q6v5_start,
1225 .stop = q6v5_stop,
1226 .da_to_va = q6v5_da_to_va,
1227 .parse_fw = qcom_q6v5_register_dump_segments,
1228 .load = q6v5_load,
1229 };
1230
1231 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1232 {
1233 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1234
1235 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1236 qproc->proxy_clk_count);
1237 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1238 qproc->proxy_reg_count);
1239 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1240 }
1241
1242 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1243 {
1244 struct of_phandle_args args;
1245 struct resource *res;
1246 int ret;
1247
1248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1249 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1250 if (IS_ERR(qproc->reg_base))
1251 return PTR_ERR(qproc->reg_base);
1252
1253 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1254 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1255 if (IS_ERR(qproc->rmb_base))
1256 return PTR_ERR(qproc->rmb_base);
1257
1258 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1259 "qcom,halt-regs", 3, 0, &args);
1260 if (ret < 0) {
1261 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1262 return -EINVAL;
1263 }
1264
1265 qproc->halt_map = syscon_node_to_regmap(args.np);
1266 of_node_put(args.np);
1267 if (IS_ERR(qproc->halt_map))
1268 return PTR_ERR(qproc->halt_map);
1269
1270 qproc->halt_q6 = args.args[0];
1271 qproc->halt_modem = args.args[1];
1272 qproc->halt_nc = args.args[2];
1273
1274 return 0;
1275 }
1276
1277 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1278 char **clk_names)
1279 {
1280 int i;
1281
1282 if (!clk_names)
1283 return 0;
1284
1285 for (i = 0; clk_names[i]; i++) {
1286 clks[i] = devm_clk_get(dev, clk_names[i]);
1287 if (IS_ERR(clks[i])) {
1288 int rc = PTR_ERR(clks[i]);
1289
1290 if (rc != -EPROBE_DEFER)
1291 dev_err(dev, "Failed to get %s clock\n",
1292 clk_names[i]);
1293 return rc;
1294 }
1295 }
1296
1297 return i;
1298 }
1299
1300 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1301 char **pd_names)
1302 {
1303 size_t num_pds = 0;
1304 int ret;
1305 int i;
1306
1307 if (!pd_names)
1308 return 0;
1309
1310 while (pd_names[num_pds])
1311 num_pds++;
1312
1313 for (i = 0; i < num_pds; i++) {
1314 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1315 if (IS_ERR_OR_NULL(devs[i])) {
1316 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1317 goto unroll_attach;
1318 }
1319 }
1320
1321 return num_pds;
1322
1323 unroll_attach:
1324 for (i--; i >= 0; i--)
1325 dev_pm_domain_detach(devs[i], false);
1326
1327 return ret;
1328 };
1329
1330 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1331 size_t pd_count)
1332 {
1333 int i;
1334
1335 for (i = 0; i < pd_count; i++)
1336 dev_pm_domain_detach(pds[i], false);
1337 }
1338
1339 static int q6v5_init_reset(struct q6v5 *qproc)
1340 {
1341 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1342 "mss_restart");
1343 if (IS_ERR(qproc->mss_restart)) {
1344 dev_err(qproc->dev, "failed to acquire mss restart\n");
1345 return PTR_ERR(qproc->mss_restart);
1346 }
1347
1348 if (qproc->has_alt_reset) {
1349 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1350 "pdc_reset");
1351 if (IS_ERR(qproc->pdc_reset)) {
1352 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1353 return PTR_ERR(qproc->pdc_reset);
1354 }
1355 }
1356
1357 return 0;
1358 }
1359
1360 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1361 {
1362 struct device_node *child;
1363 struct device_node *node;
1364 struct resource r;
1365 int ret;
1366
1367 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1368 node = of_parse_phandle(child, "memory-region", 0);
1369 ret = of_address_to_resource(node, 0, &r);
1370 if (ret) {
1371 dev_err(qproc->dev, "unable to resolve mba region\n");
1372 return ret;
1373 }
1374 of_node_put(node);
1375
1376 qproc->mba_phys = r.start;
1377 qproc->mba_size = resource_size(&r);
1378 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1379 if (!qproc->mba_region) {
1380 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1381 &r.start, qproc->mba_size);
1382 return -EBUSY;
1383 }
1384
1385 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1386 node = of_parse_phandle(child, "memory-region", 0);
1387 ret = of_address_to_resource(node, 0, &r);
1388 if (ret) {
1389 dev_err(qproc->dev, "unable to resolve mpss region\n");
1390 return ret;
1391 }
1392 of_node_put(node);
1393
1394 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1395 qproc->mpss_size = resource_size(&r);
1396 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
1397 if (!qproc->mpss_region) {
1398 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1399 &r.start, qproc->mpss_size);
1400 return -EBUSY;
1401 }
1402
1403 return 0;
1404 }
1405
1406 static int q6v5_probe(struct platform_device *pdev)
1407 {
1408 const struct rproc_hexagon_res *desc;
1409 struct q6v5 *qproc;
1410 struct rproc *rproc;
1411 const char *mba_image;
1412 int ret;
1413
1414 desc = of_device_get_match_data(&pdev->dev);
1415 if (!desc)
1416 return -EINVAL;
1417
1418 if (desc->need_mem_protection && !qcom_scm_is_available())
1419 return -EPROBE_DEFER;
1420
1421 mba_image = desc->hexagon_mba_image;
1422 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1423 0, &mba_image);
1424 if (ret < 0 && ret != -EINVAL)
1425 return ret;
1426
1427 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1428 mba_image, sizeof(*qproc));
1429 if (!rproc) {
1430 dev_err(&pdev->dev, "failed to allocate rproc\n");
1431 return -ENOMEM;
1432 }
1433
1434 rproc->auto_boot = false;
1435
1436 qproc = (struct q6v5 *)rproc->priv;
1437 qproc->dev = &pdev->dev;
1438 qproc->rproc = rproc;
1439 qproc->hexagon_mdt_image = "modem.mdt";
1440 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1441 1, &qproc->hexagon_mdt_image);
1442 if (ret < 0 && ret != -EINVAL)
1443 goto free_rproc;
1444
1445 platform_set_drvdata(pdev, qproc);
1446
1447 ret = q6v5_init_mem(qproc, pdev);
1448 if (ret)
1449 goto free_rproc;
1450
1451 ret = q6v5_alloc_memory_region(qproc);
1452 if (ret)
1453 goto free_rproc;
1454
1455 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1456 desc->proxy_clk_names);
1457 if (ret < 0) {
1458 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1459 goto free_rproc;
1460 }
1461 qproc->proxy_clk_count = ret;
1462
1463 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1464 desc->reset_clk_names);
1465 if (ret < 0) {
1466 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1467 goto free_rproc;
1468 }
1469 qproc->reset_clk_count = ret;
1470
1471 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1472 desc->active_clk_names);
1473 if (ret < 0) {
1474 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1475 goto free_rproc;
1476 }
1477 qproc->active_clk_count = ret;
1478
1479 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1480 desc->proxy_supply);
1481 if (ret < 0) {
1482 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1483 goto free_rproc;
1484 }
1485 qproc->proxy_reg_count = ret;
1486
1487 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1488 desc->active_supply);
1489 if (ret < 0) {
1490 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1491 goto free_rproc;
1492 }
1493 qproc->active_reg_count = ret;
1494
1495 ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1496 desc->active_pd_names);
1497 if (ret < 0) {
1498 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1499 goto free_rproc;
1500 }
1501 qproc->active_pd_count = ret;
1502
1503 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1504 desc->proxy_pd_names);
1505 if (ret < 0) {
1506 dev_err(&pdev->dev, "Failed to init power domains\n");
1507 goto detach_active_pds;
1508 }
1509 qproc->proxy_pd_count = ret;
1510
1511 qproc->has_alt_reset = desc->has_alt_reset;
1512 ret = q6v5_init_reset(qproc);
1513 if (ret)
1514 goto detach_proxy_pds;
1515
1516 qproc->version = desc->version;
1517 qproc->need_mem_protection = desc->need_mem_protection;
1518
1519 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1520 qcom_msa_handover);
1521 if (ret)
1522 goto detach_proxy_pds;
1523
1524 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1525 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1526 qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
1527 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1528 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1529 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1530 if (IS_ERR(qproc->sysmon)) {
1531 ret = PTR_ERR(qproc->sysmon);
1532 goto detach_proxy_pds;
1533 }
1534
1535 ret = rproc_add(rproc);
1536 if (ret)
1537 goto detach_proxy_pds;
1538
1539 return 0;
1540
1541 detach_proxy_pds:
1542 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1543 detach_active_pds:
1544 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1545 free_rproc:
1546 rproc_free(rproc);
1547
1548 return ret;
1549 }
1550
1551 static int q6v5_remove(struct platform_device *pdev)
1552 {
1553 struct q6v5 *qproc = platform_get_drvdata(pdev);
1554
1555 rproc_del(qproc->rproc);
1556
1557 qcom_remove_sysmon_subdev(qproc->sysmon);
1558 qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
1559 qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1560 qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
1561
1562 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1563 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1564
1565 rproc_free(qproc->rproc);
1566
1567 return 0;
1568 }
1569
1570 static const struct rproc_hexagon_res sdm845_mss = {
1571 .hexagon_mba_image = "mba.mbn",
1572 .proxy_clk_names = (char*[]){
1573 "xo",
1574 "prng",
1575 NULL
1576 },
1577 .reset_clk_names = (char*[]){
1578 "iface",
1579 "snoc_axi",
1580 NULL
1581 },
1582 .active_clk_names = (char*[]){
1583 "bus",
1584 "mem",
1585 "gpll0_mss",
1586 "mnoc_axi",
1587 NULL
1588 },
1589 .active_pd_names = (char*[]){
1590 "load_state",
1591 NULL
1592 },
1593 .proxy_pd_names = (char*[]){
1594 "cx",
1595 "mx",
1596 "mss",
1597 NULL
1598 },
1599 .need_mem_protection = true,
1600 .has_alt_reset = true,
1601 .version = MSS_SDM845,
1602 };
1603
1604 static const struct rproc_hexagon_res msm8996_mss = {
1605 .hexagon_mba_image = "mba.mbn",
1606 .proxy_supply = (struct qcom_mss_reg_res[]) {
1607 {
1608 .supply = "pll",
1609 .uA = 100000,
1610 },
1611 {}
1612 },
1613 .proxy_clk_names = (char*[]){
1614 "xo",
1615 "pnoc",
1616 "qdss",
1617 NULL
1618 },
1619 .active_clk_names = (char*[]){
1620 "iface",
1621 "bus",
1622 "mem",
1623 "gpll0_mss",
1624 "snoc_axi",
1625 "mnoc_axi",
1626 NULL
1627 },
1628 .need_mem_protection = true,
1629 .has_alt_reset = false,
1630 .version = MSS_MSM8996,
1631 };
1632
1633 static const struct rproc_hexagon_res msm8916_mss = {
1634 .hexagon_mba_image = "mba.mbn",
1635 .proxy_supply = (struct qcom_mss_reg_res[]) {
1636 {
1637 .supply = "mx",
1638 .uV = 1050000,
1639 },
1640 {
1641 .supply = "cx",
1642 .uA = 100000,
1643 },
1644 {
1645 .supply = "pll",
1646 .uA = 100000,
1647 },
1648 {}
1649 },
1650 .proxy_clk_names = (char*[]){
1651 "xo",
1652 NULL
1653 },
1654 .active_clk_names = (char*[]){
1655 "iface",
1656 "bus",
1657 "mem",
1658 NULL
1659 },
1660 .need_mem_protection = false,
1661 .has_alt_reset = false,
1662 .version = MSS_MSM8916,
1663 };
1664
1665 static const struct rproc_hexagon_res msm8974_mss = {
1666 .hexagon_mba_image = "mba.b00",
1667 .proxy_supply = (struct qcom_mss_reg_res[]) {
1668 {
1669 .supply = "mx",
1670 .uV = 1050000,
1671 },
1672 {
1673 .supply = "cx",
1674 .uA = 100000,
1675 },
1676 {
1677 .supply = "pll",
1678 .uA = 100000,
1679 },
1680 {}
1681 },
1682 .active_supply = (struct qcom_mss_reg_res[]) {
1683 {
1684 .supply = "mss",
1685 .uV = 1050000,
1686 .uA = 100000,
1687 },
1688 {}
1689 },
1690 .proxy_clk_names = (char*[]){
1691 "xo",
1692 NULL
1693 },
1694 .active_clk_names = (char*[]){
1695 "iface",
1696 "bus",
1697 "mem",
1698 NULL
1699 },
1700 .need_mem_protection = false,
1701 .has_alt_reset = false,
1702 .version = MSS_MSM8974,
1703 };
1704
1705 static const struct of_device_id q6v5_of_match[] = {
1706 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1707 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1708 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1709 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1710 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1711 { },
1712 };
1713 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1714
1715 static struct platform_driver q6v5_driver = {
1716 .probe = q6v5_probe,
1717 .remove = q6v5_remove,
1718 .driver = {
1719 .name = "qcom-q6v5-mss",
1720 .of_match_table = q6v5_of_match,
1721 },
1722 };
1723 module_platform_driver(q6v5_driver);
1724
1725 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
1726 MODULE_LICENSE("GPL v2");