drivers/staging/fbtft/fb

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This source file includes following definitions.
read_devicecode
init_display
set_addr_win
set_var
set_gamma
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * FB driver for the ILI9320 LCD Controller
   4  *
   5  * Copyright (C) 2013 Noralf Tronnes
   6  */
   7 
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/delay.h>
  14 
  15 #include "fbtft.h"
  16 
  17 #define DRVNAME         "fb_ili9320"
  18 #define WIDTH           240
  19 #define HEIGHT          320
  20 #define DEFAULT_GAMMA   "07 07 6 0 0 0 5 5 4 0\n" \
  21                         "07 08 4 7 5 1 2 0 7 7"
  22 
  23 static unsigned int read_devicecode(struct fbtft_par *par)
  24 {
  25         int ret;
  26         u8 rxbuf[8] = {0, };
  27 
  28         write_reg(par, 0x0000);
  29         ret = par->fbtftops.read(par, rxbuf, 4);
  30         return (rxbuf[2] << 8) | rxbuf[3];
  31 }
  32 
  33 static int init_display(struct fbtft_par *par)
  34 {
  35         unsigned int devcode;
  36 
  37         par->fbtftops.reset(par);
  38 
  39         devcode = read_devicecode(par);
  40         fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
  41                       devcode);
  42         if ((devcode != 0x0000) && (devcode != 0x9320))
  43                 dev_warn(par->info->device,
  44                          "Unrecognized Device code: 0x%04X (expected 0x9320)\n",
  45                         devcode);
  46 
  47         /* Initialization sequence from ILI9320 Application Notes */
  48 
  49         /* *********** Start Initial Sequence ********* */
  50         /* Set the Vcore voltage and this setting is must. */
  51         write_reg(par, 0x00E5, 0x8000);
  52 
  53         /* Start internal OSC. */
  54         write_reg(par, 0x0000, 0x0001);
  55 
  56         /* set SS and SM bit */
  57         write_reg(par, 0x0001, 0x0100);
  58 
  59         /* set 1 line inversion */
  60         write_reg(par, 0x0002, 0x0700);
  61 
  62         /* Resize register */
  63         write_reg(par, 0x0004, 0x0000);
  64 
  65         /* set the back and front porch */
  66         write_reg(par, 0x0008, 0x0202);
  67 
  68         /* set non-display area refresh cycle */
  69         write_reg(par, 0x0009, 0x0000);
  70 
  71         /* FMARK function */
  72         write_reg(par, 0x000A, 0x0000);
  73 
  74         /* RGB interface setting */
  75         write_reg(par, 0x000C, 0x0000);
  76 
  77         /* Frame marker Position */
  78         write_reg(par, 0x000D, 0x0000);
  79 
  80         /* RGB interface polarity */
  81         write_reg(par, 0x000F, 0x0000);
  82 
  83         /* ***********Power On sequence *************** */
  84         /* SAP, BT[3:0], AP, DSTB, SLP, STB */
  85         write_reg(par, 0x0010, 0x0000);
  86 
  87         /* DC1[2:0], DC0[2:0], VC[2:0] */
  88         write_reg(par, 0x0011, 0x0007);
  89 
  90         /* VREG1OUT voltage */
  91         write_reg(par, 0x0012, 0x0000);
  92 
  93         /* VDV[4:0] for VCOM amplitude */
  94         write_reg(par, 0x0013, 0x0000);
  95 
  96         /* Dis-charge capacitor power voltage */
  97         mdelay(200);
  98 
  99         /* SAP, BT[3:0], AP, DSTB, SLP, STB */
 100         write_reg(par, 0x0010, 0x17B0);
 101 
 102         /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
 103         write_reg(par, 0x0011, 0x0031);
 104         mdelay(50);
 105 
 106         /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
 107         write_reg(par, 0x0012, 0x0138);
 108         mdelay(50);
 109 
 110         /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
 111         write_reg(par, 0x0013, 0x1800);
 112 
 113         /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
 114         write_reg(par, 0x0029, 0x0008);
 115         mdelay(50);
 116 
 117         /* GRAM horizontal Address */
 118         write_reg(par, 0x0020, 0x0000);
 119 
 120         /* GRAM Vertical Address */
 121         write_reg(par, 0x0021, 0x0000);
 122 
 123         /* ------------------ Set GRAM area --------------- */
 124         /* Horizontal GRAM Start Address */
 125         write_reg(par, 0x0050, 0x0000);
 126 
 127         /* Horizontal GRAM End Address */
 128         write_reg(par, 0x0051, 0x00EF);
 129 
 130         /* Vertical GRAM Start Address */
 131         write_reg(par, 0x0052, 0x0000);
 132 
 133         /* Vertical GRAM End Address */
 134         write_reg(par, 0x0053, 0x013F);
 135 
 136         /* Gate Scan Line */
 137         write_reg(par, 0x0060, 0x2700);
 138 
 139         /* NDL,VLE, REV */
 140         write_reg(par, 0x0061, 0x0001);
 141 
 142         /* set scrolling line */
 143         write_reg(par, 0x006A, 0x0000);
 144 
 145         /* -------------- Partial Display Control --------- */
 146         write_reg(par, 0x0080, 0x0000);
 147         write_reg(par, 0x0081, 0x0000);
 148         write_reg(par, 0x0082, 0x0000);
 149         write_reg(par, 0x0083, 0x0000);
 150         write_reg(par, 0x0084, 0x0000);
 151         write_reg(par, 0x0085, 0x0000);
 152 
 153         /* -------------- Panel Control ------------------- */
 154         write_reg(par, 0x0090, 0x0010);
 155         write_reg(par, 0x0092, 0x0000);
 156         write_reg(par, 0x0093, 0x0003);
 157         write_reg(par, 0x0095, 0x0110);
 158         write_reg(par, 0x0097, 0x0000);
 159         write_reg(par, 0x0098, 0x0000);
 160         write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
 161 
 162         return 0;
 163 }
 164 
 165 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 166 {
 167         switch (par->info->var.rotate) {
 168         /* R20h = Horizontal GRAM Start Address */
 169         /* R21h = Vertical GRAM Start Address */
 170         case 0:
 171                 write_reg(par, 0x0020, xs);
 172                 write_reg(par, 0x0021, ys);
 173                 break;
 174         case 180:
 175                 write_reg(par, 0x0020, WIDTH - 1 - xs);
 176                 write_reg(par, 0x0021, HEIGHT - 1 - ys);
 177                 break;
 178         case 270:
 179                 write_reg(par, 0x0020, WIDTH - 1 - ys);
 180                 write_reg(par, 0x0021, xs);
 181                 break;
 182         case 90:
 183                 write_reg(par, 0x0020, ys);
 184                 write_reg(par, 0x0021, HEIGHT - 1 - xs);
 185                 break;
 186         }
 187         write_reg(par, 0x0022); /* Write Data to GRAM */
 188 }
 189 
 190 static int set_var(struct fbtft_par *par)
 191 {
 192         switch (par->info->var.rotate) {
 193         case 0:
 194                 write_reg(par, 0x3, (par->bgr << 12) | 0x30);
 195                 break;
 196         case 270:
 197                 write_reg(par, 0x3, (par->bgr << 12) | 0x28);
 198                 break;
 199         case 180:
 200                 write_reg(par, 0x3, (par->bgr << 12) | 0x00);
 201                 break;
 202         case 90:
 203                 write_reg(par, 0x3, (par->bgr << 12) | 0x18);
 204                 break;
 205         }
 206         return 0;
 207 }
 208 
 209 /*
 210  * Gamma string format:
 211  *  VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
 212  *  VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
 213  */
 214 #define CURVE(num, idx)  curves[(num) * par->gamma.num_values + (idx)]
 215 static int set_gamma(struct fbtft_par *par, u32 *curves)
 216 {
 217         static const unsigned long mask[] = {
 218                 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 219                 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 220         };
 221         int i, j;
 222 
 223         /* apply mask */
 224         for (i = 0; i < 2; i++)
 225                 for (j = 0; j < 10; j++)
 226                         CURVE(i, j) &= mask[i * par->gamma.num_values + j];
 227 
 228         write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
 229         write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
 230         write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
 231         write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
 232         write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
 233 
 234         write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
 235         write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
 236         write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
 237         write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
 238         write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
 239 
 240         return 0;
 241 }
 242 
 243 #undef CURVE
 244 
 245 static struct fbtft_display display = {
 246         .regwidth = 16,
 247         .width = WIDTH,
 248         .height = HEIGHT,
 249         .gamma_num = 2,
 250         .gamma_len = 10,
 251         .gamma = DEFAULT_GAMMA,
 252         .fbtftops = {
 253                 .init_display = init_display,
 254                 .set_addr_win = set_addr_win,
 255                 .set_var = set_var,
 256                 .set_gamma = set_gamma,
 257         },
 258 };
 259 
 260 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
 261 
 262 MODULE_ALIAS("spi:" DRVNAME);
 263 MODULE_ALIAS("platform:" DRVNAME);
 264 MODULE_ALIAS("spi:ili9320");
 265 MODULE_ALIAS("platform:ili9320");
 266 
 267 MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
 268 MODULE_AUTHOR("Noralf Tronnes");
 269 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/staging/fbtft/fb_ili9320.c

DEFINITIONS
