root/drivers/staging/vt6655/desc.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * File: desc.h
   7  *
   8  * Purpose:The header file of descriptor
   9  *
  10  * Revision History:
  11  *
  12  * Author: Tevin Chen
  13  *
  14  * Date: May 21, 1996
  15  *
  16  */
  17 
  18 #ifndef __DESC_H__
  19 #define __DESC_H__
  20 
  21 #include <linux/types.h>
  22 #include <linux/mm.h>
  23 #include "linux/ieee80211.h"
  24 
  25 #define B_OWNED_BY_CHIP     1
  26 #define B_OWNED_BY_HOST     0
  27 
  28 /* Bits in the RSR register */
  29 #define RSR_ADDRBROAD       0x80
  30 #define RSR_ADDRMULTI       0x40
  31 #define RSR_ADDRUNI         0x00
  32 #define RSR_IVLDTYP         0x20
  33 #define RSR_IVLDLEN         0x10        /* invalid len (> 2312 byte) */
  34 #define RSR_BSSIDOK         0x08
  35 #define RSR_CRCOK           0x04
  36 #define RSR_BCNSSIDOK       0x02
  37 #define RSR_ADDROK          0x01
  38 
  39 /* Bits in the new RSR register */
  40 #define NEWRSR_DECRYPTOK    0x10
  41 #define NEWRSR_CFPIND       0x08
  42 #define NEWRSR_HWUTSF       0x04
  43 #define NEWRSR_BCNHITAID    0x02
  44 #define NEWRSR_BCNHITAID0   0x01
  45 
  46 /* Bits in the TSR0 register */
  47 #define TSR0_PWRSTS1_2      0xC0
  48 #define TSR0_PWRSTS7        0x20
  49 #define TSR0_NCR            0x1F
  50 
  51 /* Bits in the TSR1 register */
  52 #define TSR1_TERR           0x80
  53 #define TSR1_PWRSTS4_6      0x70
  54 #define TSR1_RETRYTMO       0x08
  55 #define TSR1_TMO            0x04
  56 #define TSR1_PWRSTS3        0x02
  57 #define ACK_DATA            0x01
  58 
  59 /* Bits in the TCR register */
  60 #define EDMSDU              0x04        /* end of sdu */
  61 #define TCR_EDP             0x02        /* end of packet */
  62 #define TCR_STP             0x01        /* start of packet */
  63 
  64 /* max transmit or receive buffer size */
  65 #define CB_MAX_BUF_SIZE     2900U
  66                                         /* NOTE: must be multiple of 4 */
  67 #define CB_MAX_TX_BUF_SIZE          CB_MAX_BUF_SIZE
  68 #define CB_MAX_RX_BUF_SIZE_NORMAL   CB_MAX_BUF_SIZE
  69 
  70 #define CB_BEACON_BUF_SIZE  512U
  71 
  72 #define CB_MAX_RX_DESC      128
  73 #define CB_MIN_RX_DESC      16
  74 #define CB_MAX_TX_DESC      64
  75 #define CB_MIN_TX_DESC      16
  76 
  77 #define CB_MAX_RECEIVED_PACKETS     16
  78                                 /*
  79                                  * limit our receive routine to indicating
  80                                  * this many at a time for 2 reasons:
  81                                  * 1. driver flow control to protocol layer
  82                                  * 2. limit the time used in ISR routine
  83                                  */
  84 
  85 #define CB_EXTRA_RD_NUM     32
  86 #define CB_RD_NUM           32
  87 #define CB_TD_NUM           32
  88 
  89 /*
  90  * max number of physical segments in a single NDIS packet. Above this
  91  * threshold, the packet is copied into a single physically contiguous buffer
  92  */
  93 #define CB_MAX_SEGMENT      4
  94 
  95 #define CB_MIN_MAP_REG_NUM  4
  96 #define CB_MAX_MAP_REG_NUM  CB_MAX_TX_DESC
  97 
  98 #define CB_PROTOCOL_RESERVED_SECTION    16
  99 
 100 /*
 101  * if retrys excess 15 times , tx will abort, and if tx fifo underflow,
 102  * tx will fail, we should try to resend it
 103  */
 104 #define CB_MAX_TX_ABORT_RETRY   3
 105 
 106 /* WMAC definition FIFO Control */
 107 #define FIFOCTL_AUTO_FB_1   0x1000
 108 #define FIFOCTL_AUTO_FB_0   0x0800
 109 #define FIFOCTL_GRPACK      0x0400
 110 #define FIFOCTL_11GA        0x0300
 111 #define FIFOCTL_11GB        0x0200
 112 #define FIFOCTL_11B         0x0100
 113 #define FIFOCTL_11A         0x0000
 114 #define FIFOCTL_RTS         0x0080
 115 #define FIFOCTL_ISDMA0      0x0040
 116 #define FIFOCTL_GENINT      0x0020
 117 #define FIFOCTL_TMOEN       0x0010
 118 #define FIFOCTL_LRETRY      0x0008
 119 #define FIFOCTL_CRCDIS      0x0004
 120 #define FIFOCTL_NEEDACK     0x0002
 121 #define FIFOCTL_LHEAD       0x0001
 122 
 123 /* WMAC definition Frag Control */
 124 #define FRAGCTL_AES         0x0300
 125 #define FRAGCTL_TKIP        0x0200
 126 #define FRAGCTL_LEGACY      0x0100
 127 #define FRAGCTL_NONENCRYPT  0x0000
 128 #define FRAGCTL_ENDFRAG     0x0003
 129 #define FRAGCTL_MIDFRAG     0x0002
 130 #define FRAGCTL_STAFRAG     0x0001
 131 #define FRAGCTL_NONFRAG     0x0000
 132 
 133 #define TYPE_TXDMA0     0
 134 #define TYPE_AC0DMA     1
 135 #define TYPE_ATIMDMA    2
 136 #define TYPE_SYNCDMA    3
 137 #define TYPE_MAXTD      2
 138 
 139 #define TYPE_BEACONDMA  4
 140 
 141 #define TYPE_RXDMA0     0
 142 #define TYPE_RXDMA1     1
 143 #define TYPE_MAXRD      2
 144 
 145 /* TD_INFO flags control bit */
 146 #define TD_FLAGS_NETIF_SKB      0x01    /* check if need release skb */
 147 /* check if called from private skb (hostap) */
 148 #define TD_FLAGS_PRIV_SKB       0x02
 149 #define TD_FLAGS_PS_RETRY       0x04    /* check if PS STA frame re-transmit */
 150 
 151 /*
 152  * ref_sk_buff is used for mapping the skb structure between pre-built
 153  * driver-obj & running kernel. Since different kernel version (2.4x) may
 154  * change skb structure, i.e. pre-built driver-obj may link to older skb that
 155  * leads error.
 156  */
 157 
 158 struct vnt_rd_info {
 159         struct sk_buff *skb;
 160         dma_addr_t  skb_dma;
 161 };
 162 
 163 struct vnt_rdes0 {
 164         volatile __le16 res_count;
 165 #ifdef __BIG_ENDIAN
 166         union {
 167                 volatile u16 f15_reserved;
 168                 struct {
 169                         volatile u8 f8_reserved1;
 170                         volatile u8 owner:1;
 171                         volatile u8 f7_reserved:7;
 172                 } __packed;
 173         } __packed;
 174 #else
 175         u16 f15_reserved:15;
 176         u16 owner:1;
 177 #endif
 178 } __packed;
 179 
 180 struct vnt_rdes1 {
 181         __le16 req_count;
 182         u16 reserved;
 183 } __packed;
 184 
 185 /* Rx descriptor*/
 186 struct vnt_rx_desc {
 187         volatile struct vnt_rdes0 rd0;
 188         volatile struct vnt_rdes1 rd1;
 189         volatile __le32 buff_addr;
 190         volatile __le32 next_desc;
 191         struct vnt_rx_desc *next __aligned(8);
 192         struct vnt_rd_info *rd_info __aligned(8);
 193 } __packed;
 194 
 195 struct vnt_tdes0 {
 196         volatile u8 tsr0;
 197         volatile u8 tsr1;
 198 #ifdef __BIG_ENDIAN
 199         union {
 200                 volatile u16 f15_txtime;
 201                 struct {
 202                         volatile u8 f8_reserved;
 203                         volatile u8 owner:1;
 204                         volatile u8 f7_reserved:7;
 205                 } __packed;
 206         } __packed;
 207 #else
 208         volatile u16 f15_txtime:15;
 209         volatile u16 owner:1;
 210 #endif
 211 } __packed;
 212 
 213 struct vnt_tdes1 {
 214         volatile __le16 req_count;
 215         volatile u8 tcr;
 216         volatile u8 reserved;
 217 } __packed;
 218 
 219 struct vnt_td_info {
 220         void *mic_hdr;
 221         struct sk_buff *skb;
 222         unsigned char *buf;
 223         dma_addr_t buf_dma;
 224         u16 req_count;
 225         u8 flags;
 226 };
 227 
 228 /* transmit descriptor */
 229 struct vnt_tx_desc {
 230         volatile struct vnt_tdes0 td0;
 231         volatile struct vnt_tdes1 td1;
 232         volatile __le32 buff_addr;
 233         volatile __le32 next_desc;
 234         struct vnt_tx_desc *next __aligned(8);
 235         struct vnt_td_info *td_info __aligned(8);
 236 } __packed;
 237 
 238 /* Length, Service, and Signal fields of Phy for Tx */
 239 struct vnt_phy_field {
 240         u8 signal;
 241         u8 service;
 242         __le16 len;
 243 } __packed;
 244 
 245 union vnt_phy_field_swap {
 246         struct vnt_phy_field field_read;
 247         u16 swap[2];
 248         u32 field_write;
 249 };
 250 
 251 #endif /* __DESC_H__ */