1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * comedi/drivers/s626.c
4 * Sensoray s626 Comedi driver
5 *
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 *
9 * Based on Sensoray Model 626 Linux driver Version 0.2
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
11 */
12
13 /*
14 * Driver: s626
15 * Description: Sensoray 626 driver
16 * Devices: [Sensoray] 626 (s626)
17 * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
18 * Updated: Fri, 15 Feb 2008 10:28:42 +0000
19 * Status: experimental
20
21 * Configuration options: not applicable, uses PCI auto config
22
23 * INSN_CONFIG instructions:
24 * analog input:
25 * none
26 *
27 * analog output:
28 * none
29 *
30 * digital channel:
31 * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
32 * supported configuration options:
33 * INSN_CONFIG_DIO_QUERY
34 * COMEDI_INPUT
35 * COMEDI_OUTPUT
36 *
37 * encoder:
38 * Every channel must be configured before reading.
39 *
40 * Example code
41 *
42 * insn.insn=INSN_CONFIG; //configuration instruction
43 * insn.n=1; //number of operation (must be 1)
44 * insn.data=&initialvalue; //initial value loaded into encoder
45 * //during configuration
46 * insn.subdev=5; //encoder subdevice
47 * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
48 * //to configure
49 *
50 * comedi_do_insn(cf,&insn); //executing configuration
51 */
52
53 #include <linux/module.h>
54 #include <linux/delay.h>
55 #include <linux/interrupt.h>
56 #include <linux/kernel.h>
57 #include <linux/types.h>
58
59 #include "../comedi_pci.h"
60
61 #include "s626.h"
62
63 struct s626_buffer_dma {
64 dma_addr_t physical_base;
65 void *logical_base;
66 };
67
68 /**
69 * struct s626_private - Working data for s626 driver.
70 * @ai_cmd_running: non-zero if ai_cmd is running.
71 * @ai_sample_timer: time between samples in units of the timer.
72 * @ai_convert_count: conversion counter.
73 * @ai_convert_timer: time between conversion in units of the timer.
74 * @counter_int_enabs: counter interrupt enable mask for MISC2 register.
75 * @adc_items: number of items in ADC poll list.
76 * @rps_buf: DMA buffer used to hold ADC (RPS1) program.
77 * @ana_buf: DMA buffer used to receive ADC data and hold DAC data.
78 * @dac_wbuf: pointer to logical adrs of DMA buffer used to hold DAC data.
79 * @dacpol: image of DAC polarity register.
80 * @trim_setpoint: images of TrimDAC setpoints.
81 * @i2c_adrs: I2C device address for onboard EEPROM (board rev dependent)
82 */
83 struct s626_private {
84 u8 ai_cmd_running;
85 unsigned int ai_sample_timer;
86 int ai_convert_count;
87 unsigned int ai_convert_timer;
88 u16 counter_int_enabs;
89 u8 adc_items;
90 struct s626_buffer_dma rps_buf;
91 struct s626_buffer_dma ana_buf;
92 u32 *dac_wbuf;
93 u16 dacpol;
94 u8 trim_setpoint[12];
95 u32 i2c_adrs;
96 };
97
98 /* Counter overflow/index event flag masks for RDMISC2. */
99 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
100 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
101
102 /*
103 * Enable/disable a function or test status bit(s) that are accessed
104 * through Main Control Registers 1 or 2.
105 */
106 static void s626_mc_enable(struct comedi_device *dev,
107 unsigned int cmd, unsigned int reg)
108 {
109 unsigned int val = (cmd << 16) | cmd;
110
111 writel(val, dev->mmio + reg);
112 }
113
114 static void s626_mc_disable(struct comedi_device *dev,
115 unsigned int cmd, unsigned int reg)
116 {
117 writel(cmd << 16, dev->mmio + reg);
118 }
119
120 static bool s626_mc_test(struct comedi_device *dev,
121 unsigned int cmd, unsigned int reg)
122 {
123 unsigned int val;
124
125 val = readl(dev->mmio + reg);
126
127 return (val & cmd) ? true : false;
128 }
129
130 #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
131
132 /* Write a time slot control record to TSL2. */
133 #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2))
134
135 static const struct comedi_lrange s626_range_table = {
136 2, {
137 BIP_RANGE(5),
138 BIP_RANGE(10)
139 }
140 };
141
142 /*
143 * Execute a DEBI transfer. This must be called from within a critical section.
144 */
145 static void s626_debi_transfer(struct comedi_device *dev)
146 {
147 static const int timeout = 10000;
148 int i;
149
150 /* Initiate upload of shadow RAM to DEBI control register */
151 s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
152
153 /*
154 * Wait for completion of upload from shadow RAM to
155 * DEBI control register.
156 */
157 for (i = 0; i < timeout; i++) {
158 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
159 break;
160 udelay(1);
161 }
162 if (i == timeout)
163 dev_err(dev->class_dev,
164 "Timeout while uploading to DEBI control register\n");
165
166 /* Wait until DEBI transfer is done */
167 for (i = 0; i < timeout; i++) {
168 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
169 break;
170 udelay(1);
171 }
172 if (i == timeout)
173 dev_err(dev->class_dev, "DEBI transfer timeout\n");
174 }
175
176 /*
177 * Read a value from a gate array register.
178 */
179 static u16 s626_debi_read(struct comedi_device *dev, u16 addr)
180 {
181 /* Set up DEBI control register value in shadow RAM */
182 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
183
184 /* Execute the DEBI transfer. */
185 s626_debi_transfer(dev);
186
187 return readl(dev->mmio + S626_P_DEBIAD);
188 }
189
190 /*
191 * Write a value to a gate array register.
192 */
193 static void s626_debi_write(struct comedi_device *dev, u16 addr,
194 u16 wdata)
195 {
196 /* Set up DEBI control register value in shadow RAM */
197 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
198 writel(wdata, dev->mmio + S626_P_DEBIAD);
199
200 /* Execute the DEBI transfer. */
201 s626_debi_transfer(dev);
202 }
203
204 /*
205 * Replace the specified bits in a gate array register. Imports: mask
206 * specifies bits that are to be preserved, wdata is new value to be
207 * or'd with the masked original.
208 */
209 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
210 unsigned int mask, unsigned int wdata)
211 {
212 unsigned int val;
213
214 addr &= 0xffff;
215 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
216 s626_debi_transfer(dev);
217
218 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
219 val = readl(dev->mmio + S626_P_DEBIAD);
220 val &= mask;
221 val |= wdata;
222 writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
223 s626_debi_transfer(dev);
224 }
225
226 /* ************** EEPROM ACCESS FUNCTIONS ************** */
227
228 static int s626_i2c_handshake_eoc(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 struct comedi_insn *insn,
231 unsigned long context)
232 {
233 bool status;
234
235 status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
236 if (status)
237 return 0;
238 return -EBUSY;
239 }
240
241 static int s626_i2c_handshake(struct comedi_device *dev, u32 val)
242 {
243 unsigned int ctrl;
244 int ret;
245
246 /* Write I2C command to I2C Transfer Control shadow register */
247 writel(val, dev->mmio + S626_P_I2CCTRL);
248
249 /*
250 * Upload I2C shadow registers into working registers and
251 * wait for upload confirmation.
252 */
253 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
254 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
255 if (ret)
256 return ret;
257
258 /* Wait until I2C bus transfer is finished or an error occurs */
259 do {
260 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
261 } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
262
263 /* Return non-zero if I2C error occurred */
264 return ctrl & S626_I2C_ERR;
265 }
266
267 /* Read u8 from EEPROM. */
268 static u8 s626_i2c_read(struct comedi_device *dev, u8 addr)
269 {
270 struct s626_private *devpriv = dev->private;
271
272 /*
273 * Send EEPROM target address:
274 * Byte2 = I2C command: write to I2C EEPROM device.
275 * Byte1 = EEPROM internal target address.
276 * Byte0 = Not sent.
277 */
278 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
279 devpriv->i2c_adrs) |
280 S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
281 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
282 /* Abort function and declare error if handshake failed. */
283 return 0;
284
285 /*
286 * Execute EEPROM read:
287 * Byte2 = I2C command: read from I2C EEPROM device.
288 * Byte1 receives uint8_t from EEPROM.
289 * Byte0 = Not sent.
290 */
291 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
292 (devpriv->i2c_adrs | 1)) |
293 S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
294 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
295 /* Abort function and declare error if handshake failed. */
296 return 0;
297
298 return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
299 }
300
301 /* *********** DAC FUNCTIONS *********** */
302
303 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
304 static const u8 s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
305
306 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
307 static const u8 s626_trimadrs[] = {
308 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
309 };
310
311 enum {
312 s626_send_dac_wait_not_mc1_a2out,
313 s626_send_dac_wait_ssr_af2_out,
314 s626_send_dac_wait_fb_buffer2_msb_00,
315 s626_send_dac_wait_fb_buffer2_msb_ff
316 };
317
318 static int s626_send_dac_eoc(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn,
321 unsigned long context)
322 {
323 unsigned int status;
324
325 switch (context) {
326 case s626_send_dac_wait_not_mc1_a2out:
327 status = readl(dev->mmio + S626_P_MC1);
328 if (!(status & S626_MC1_A2OUT))
329 return 0;
330 break;
331 case s626_send_dac_wait_ssr_af2_out:
332 status = readl(dev->mmio + S626_P_SSR);
333 if (status & S626_SSR_AF2_OUT)
334 return 0;
335 break;
336 case s626_send_dac_wait_fb_buffer2_msb_00:
337 status = readl(dev->mmio + S626_P_FB_BUFFER2);
338 if (!(status & 0xff000000))
339 return 0;
340 break;
341 case s626_send_dac_wait_fb_buffer2_msb_ff:
342 status = readl(dev->mmio + S626_P_FB_BUFFER2);
343 if (status & 0xff000000)
344 return 0;
345 break;
346 default:
347 return -EINVAL;
348 }
349 return -EBUSY;
350 }
351
352 /*
353 * Private helper function: Transmit serial data to DAC via Audio
354 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
355 * dacpol contains valid target image.
356 */
357 static int s626_send_dac(struct comedi_device *dev, u32 val)
358 {
359 struct s626_private *devpriv = dev->private;
360 int ret;
361
362 /* START THE SERIAL CLOCK RUNNING ------------- */
363
364 /*
365 * Assert DAC polarity control and enable gating of DAC serial clock
366 * and audio bit stream signals. At this point in time we must be
367 * assured of being in time slot 0. If we are not in slot 0, the
368 * serial clock and audio stream signals will be disabled; this is
369 * because the following s626_debi_write statement (which enables
370 * signals to be passed through the gate array) would execute before
371 * the trailing edge of WS1/WS3 (which turns off the signals), thus
372 * causing the signals to be inactive during the DAC write.
373 */
374 s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
375
376 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
377
378 /* Copy DAC setpoint value to DAC's output DMA buffer. */
379 /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
380 *devpriv->dac_wbuf = val;
381
382 /*
383 * Enable the output DMA transfer. This will cause the DMAC to copy
384 * the DAC's data value to A2's output FIFO. The DMA transfer will
385 * then immediately terminate because the protection address is
386 * reached upon transfer of the first DWORD value.
387 */
388 s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
389
390 /* While the DMA transfer is executing ... */
391
392 /*
393 * Reset Audio2 output FIFO's underflow flag (along with any
394 * other FIFO underflow/overflow flags). When set, this flag
395 * will indicate that we have emerged from slot 0.
396 */
397 writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
398
399 /*
400 * Wait for the DMA transfer to finish so that there will be data
401 * available in the FIFO when time slot 1 tries to transfer a DWORD
402 * from the FIFO to the output buffer register. We test for DMA
403 * Done by polling the DMAC enable flag; this flag is automatically
404 * cleared when the transfer has finished.
405 */
406 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
407 s626_send_dac_wait_not_mc1_a2out);
408 if (ret) {
409 dev_err(dev->class_dev, "DMA transfer timeout\n");
410 return ret;
411 }
412
413 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
414
415 /*
416 * FIFO data is now available, so we enable execution of time slots
417 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
418 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
419 * detection.
420 */
421 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
422 dev->mmio + S626_VECTPORT(0));
423
424 /*
425 * Wait for slot 1 to execute to ensure that the Packet will be
426 * transmitted. This is detected by polling the Audio2 output FIFO
427 * underflow flag, which will be set when slot 1 execution has
428 * finished transferring the DAC's data DWORD from the output FIFO
429 * to the output buffer register.
430 */
431 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
432 s626_send_dac_wait_ssr_af2_out);
433 if (ret) {
434 dev_err(dev->class_dev,
435 "TSL timeout waiting for slot 1 to execute\n");
436 return ret;
437 }
438
439 /*
440 * Set up to trap execution at slot 0 when the TSL sequencer cycles
441 * back to slot 0 after executing the EOS in slot 5. Also,
442 * simultaneously shift out and in the 0x00 that is ALWAYS the value
443 * stored in the last byte to be shifted out of the FIFO's DWORD
444 * buffer register.
445 */
446 writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
447 dev->mmio + S626_VECTPORT(0));
448
449 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
450
451 /*
452 * Wait for the TSL to finish executing all time slots before
453 * exiting this function. We must do this so that the next DAC
454 * write doesn't start, thereby enabling clock/chip select signals:
455 *
456 * 1. Before the TSL sequence cycles back to slot 0, which disables
457 * the clock/cs signal gating and traps slot // list execution.
458 * we have not yet finished slot 5 then the clock/cs signals are
459 * still gated and we have not finished transmitting the stream.
460 *
461 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
462 * this case, the slot sequence is currently repeating, but with
463 * clock/cs signals disabled. We must wait for slot 0 to trap
464 * execution before setting up the next DAC setpoint DMA transfer
465 * and enabling the clock/cs signals. To detect the end of slot 5,
466 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
467 * the TSL has not yet finished executing slot 5 ...
468 */
469 if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
470 /*
471 * The trap was set on time and we are still executing somewhere
472 * in slots 2-5, so we now wait for slot 0 to execute and trap
473 * TSL execution. This is detected when FB_BUFFER2 MSB changes
474 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
475 * out/in on SD2 the 0x00 that is always referenced by slot 5.
476 */
477 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
478 s626_send_dac_wait_fb_buffer2_msb_00);
479 if (ret) {
480 dev_err(dev->class_dev,
481 "TSL timeout waiting for slot 0 to execute\n");
482 return ret;
483 }
484 }
485 /*
486 * Either (1) we were too late setting the slot 0 trap; the TSL
487 * sequencer restarted slot 0 before we could set the EOS trap flag,
488 * or (2) we were not late and execution is now trapped at slot 0.
489 * In either case, we must now change slot 0 so that it will store
490 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
491 * In order to do this, we reprogram slot 0 so that it will shift in
492 * SD3, which is driven only by a pull-up resistor.
493 */
494 writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
495 dev->mmio + S626_VECTPORT(0));
496
497 /*
498 * Wait for slot 0 to execute, at which time the TSL is setup for
499 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
500 * from 0x00 to 0xFF.
501 */
502 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
503 s626_send_dac_wait_fb_buffer2_msb_ff);
504 if (ret) {
505 dev_err(dev->class_dev,
506 "TSL timeout waiting for slot 0 to execute\n");
507 return ret;
508 }
509 return 0;
510 }
511
512 /*
513 * Private helper function: Write setpoint to an application DAC channel.
514 */
515 static int s626_set_dac(struct comedi_device *dev,
516 u16 chan, int16_t dacdata)
517 {
518 struct s626_private *devpriv = dev->private;
519 u16 signmask;
520 u32 ws_image;
521 u32 val;
522
523 /*
524 * Adjust DAC data polarity and set up Polarity Control Register image.
525 */
526 signmask = 1 << chan;
527 if (dacdata < 0) {
528 dacdata = -dacdata;
529 devpriv->dacpol |= signmask;
530 } else {
531 devpriv->dacpol &= ~signmask;
532 }
533
534 /* Limit DAC setpoint value to valid range. */
535 if ((u16)dacdata > 0x1FFF)
536 dacdata = 0x1FFF;
537
538 /*
539 * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
540 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
541 * data to a non-existent TrimDac channel just to keep the clock
542 * running after sending data to the target DAC. This is necessary
543 * to eliminate the clock glitch that would otherwise occur at the
544 * end of the target DAC's serial data stream. When the sequence
545 * restarts at V0 (after executing V5), the gate array automatically
546 * disables gating for the DAC clock and all DAC chip selects.
547 */
548
549 /* Choose DAC chip select to be asserted */
550 ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
551 /* Slot 2: Transmit high data byte to target DAC */
552 writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
553 dev->mmio + S626_VECTPORT(2));
554 /* Slot 3: Transmit low data byte to target DAC */
555 writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
556 dev->mmio + S626_VECTPORT(3));
557 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
558 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
559 dev->mmio + S626_VECTPORT(4));
560 /* Slot 5: running after writing target DAC's low data byte */
561 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
562 dev->mmio + S626_VECTPORT(5));
563
564 /*
565 * Construct and transmit target DAC's serial packet:
566 * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
567 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
568 * to a non-existent TrimDac channel) that serves to keep the clock
569 * running after the packet has been sent to the target DAC.
570 */
571 val = 0x0F000000; /* Continue clock after target DAC data
572 * (write to non-existent trimdac).
573 */
574 val |= 0x00004000; /* Address the two main dual-DAC devices
575 * (TSL's chip select enables target device).
576 */
577 val |= ((u32)(chan & 1) << 15); /* Address the DAC channel
578 * within the device.
579 */
580 val |= (u32)dacdata; /* Include DAC setpoint data. */
581 return s626_send_dac(dev, val);
582 }
583
584 static int s626_write_trim_dac(struct comedi_device *dev,
585 u8 logical_chan, u8 dac_data)
586 {
587 struct s626_private *devpriv = dev->private;
588 u32 chan;
589
590 /*
591 * Save the new setpoint in case the application needs to read it back
592 * later.
593 */
594 devpriv->trim_setpoint[logical_chan] = dac_data;
595
596 /* Map logical channel number to physical channel number. */
597 chan = s626_trimchan[logical_chan];
598
599 /*
600 * Set up TSL2 records for TrimDac write operation. All slots shift
601 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
602 * can be detected.
603 */
604
605 /* Slot 2: Send high uint8_t to target TrimDac */
606 writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
607 dev->mmio + S626_VECTPORT(2));
608 /* Slot 3: Send low uint8_t to target TrimDac */
609 writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
610 dev->mmio + S626_VECTPORT(3));
611 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
612 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
613 dev->mmio + S626_VECTPORT(4));
614 /* Slot 5: Send NOP low uint8_t to DAC0 */
615 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
616 dev->mmio + S626_VECTPORT(5));
617
618 /*
619 * Construct and transmit target DAC's serial packet:
620 * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
621 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
622 * WORD value (that writes a channel 0 NOP command to a non-existent
623 * main DAC channel) that serves to keep the clock running after the
624 * packet has been sent to the target DAC.
625 */
626
627 /*
628 * Address the DAC channel within the trimdac device.
629 * Include DAC setpoint data.
630 */
631 return s626_send_dac(dev, (chan << 8) | dac_data);
632 }
633
634 static int s626_load_trim_dacs(struct comedi_device *dev)
635 {
636 u8 i;
637 int ret;
638
639 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
640 for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
641 ret = s626_write_trim_dac(dev, i,
642 s626_i2c_read(dev, s626_trimadrs[i]));
643 if (ret)
644 return ret;
645 }
646 return 0;
647 }
648
649 /* ****** COUNTER FUNCTIONS ******* */
650
651 /*
652 * All counter functions address a specific counter by means of the
653 * "Counter" argument, which is a logical counter number. The Counter
654 * argument may have any of the following legal values: 0=0A, 1=1A,
655 * 2=2A, 3=0B, 4=1B, 5=2B.
656 */
657
658 /*
659 * Return/set a counter pair's latch trigger source. 0: On read
660 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
661 * latches B.
662 */
663 static void s626_set_latch_source(struct comedi_device *dev,
664 unsigned int chan, u16 value)
665 {
666 s626_debi_replace(dev, S626_LP_CRB(chan),
667 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
668 S626_SET_CRB_LATCHSRC(value));
669 }
670
671 /*
672 * Write value into counter preload register.
673 */
674 static void s626_preload(struct comedi_device *dev,
675 unsigned int chan, u32 value)
676 {
677 s626_debi_write(dev, S626_LP_CNTR(chan), value);
678 s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
679 }
680
681 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
682
683 /*
684 * Reset a counter's index and overflow event capture flags.
685 */
686 static void s626_reset_cap_flags(struct comedi_device *dev,
687 unsigned int chan)
688 {
689 u16 set;
690
691 set = S626_SET_CRB_INTRESETCMD(1);
692 if (chan < 3)
693 set |= S626_SET_CRB_INTRESET_A(1);
694 else
695 set |= S626_SET_CRB_INTRESET_B(1);
696
697 s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
698 }
699
700 /*
701 * Set the operating mode for the specified counter. The setup
702 * parameter is treated as a COUNTER_SETUP data type. The following
703 * parameters are programmable (all other parms are ignored): ClkMult,
704 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
705 */
706 static void s626_set_mode_a(struct comedi_device *dev,
707 unsigned int chan, u16 setup,
708 u16 disable_int_src)
709 {
710 struct s626_private *devpriv = dev->private;
711 u16 cra;
712 u16 crb;
713 unsigned int cntsrc, clkmult, clkpol;
714
715 /* Initialize CRA and CRB images. */
716 /* Preload trigger is passed through. */
717 cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
718 /* IndexSrc is passed through. */
719 cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
720
721 /* Reset any pending CounterA event captures. */
722 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
723 /* Clock enable is passed through. */
724 crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
725
726 /* Force IntSrc to Disabled if disable_int_src is asserted. */
727 if (!disable_int_src)
728 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
729
730 /* Populate all mode-dependent attributes of CRA & CRB images. */
731 clkpol = S626_GET_STD_CLKPOL(setup);
732 switch (S626_GET_STD_ENCMODE(setup)) {
733 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
734 /* Force to Timer mode (Extender valid only for B counters). */
735 /* Fall through to case S626_ENCMODE_TIMER: */
736 case S626_ENCMODE_TIMER: /* Timer Mode: */
737 /* CntSrcA<1> selects system clock */
738 cntsrc = S626_CNTSRC_SYSCLK;
739 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
740 cntsrc |= clkpol;
741 /* ClkPolA behaves as always-on clock enable. */
742 clkpol = 1;
743 /* ClkMult must be 1x. */
744 clkmult = S626_CLKMULT_1X;
745 break;
746 default: /* Counter Mode: */
747 /* Select ENC_C and ENC_D as clock/direction inputs. */
748 cntsrc = S626_CNTSRC_ENCODER;
749 /* Clock polarity is passed through. */
750 /* Force multiplier to x1 if not legal, else pass through. */
751 clkmult = S626_GET_STD_CLKMULT(setup);
752 if (clkmult == S626_CLKMULT_SPECIAL)
753 clkmult = S626_CLKMULT_1X;
754 break;
755 }
756 cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
757 S626_SET_CRA_CLKMULT_A(clkmult);
758
759 /*
760 * Force positive index polarity if IndxSrc is software-driven only,
761 * otherwise pass it through.
762 */
763 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
764 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
765
766 /*
767 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
768 * enable mask to indicate the counter interrupt is disabled.
769 */
770 if (disable_int_src)
771 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
772 S626_INDXMASK(chan));
773
774 /*
775 * While retaining CounterB and LatchSrc configurations, program the
776 * new counter operating mode.
777 */
778 s626_debi_replace(dev, S626_LP_CRA(chan),
779 S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
780 s626_debi_replace(dev, S626_LP_CRB(chan),
781 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
782 }
783
784 static void s626_set_mode_b(struct comedi_device *dev,
785 unsigned int chan, u16 setup,
786 u16 disable_int_src)
787 {
788 struct s626_private *devpriv = dev->private;
789 u16 cra;
790 u16 crb;
791 unsigned int cntsrc, clkmult, clkpol;
792
793 /* Initialize CRA and CRB images. */
794 /* IndexSrc is passed through. */
795 cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
796
797 /* Reset event captures and disable interrupts. */
798 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
799 /* Clock enable is passed through. */
800 crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
801 /* Preload trigger source is passed through. */
802 crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
803
804 /* Force IntSrc to Disabled if disable_int_src is asserted. */
805 if (!disable_int_src)
806 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
807
808 /* Populate all mode-dependent attributes of CRA & CRB images. */
809 clkpol = S626_GET_STD_CLKPOL(setup);
810 switch (S626_GET_STD_ENCMODE(setup)) {
811 case S626_ENCMODE_TIMER: /* Timer Mode: */
812 /* CntSrcB<1> selects system clock */
813 cntsrc = S626_CNTSRC_SYSCLK;
814 /* with direction (CntSrcB<0>) obtained from ClkPol. */
815 cntsrc |= clkpol;
816 /* ClkPolB behaves as always-on clock enable. */
817 clkpol = 1;
818 /* ClkMultB must be 1x. */
819 clkmult = S626_CLKMULT_1X;
820 break;
821 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
822 /* CntSrcB source is OverflowA (same as "timer") */
823 cntsrc = S626_CNTSRC_SYSCLK;
824 /* with direction obtained from ClkPol. */
825 cntsrc |= clkpol;
826 /* ClkPolB controls IndexB -- always set to active. */
827 clkpol = 1;
828 /* ClkMultB selects OverflowA as the clock source. */
829 clkmult = S626_CLKMULT_SPECIAL;
830 break;
831 default: /* Counter Mode: */
832 /* Select ENC_C and ENC_D as clock/direction inputs. */
833 cntsrc = S626_CNTSRC_ENCODER;
834 /* ClkPol is passed through. */
835 /* Force ClkMult to x1 if not legal, otherwise pass through. */
836 clkmult = S626_GET_STD_CLKMULT(setup);
837 if (clkmult == S626_CLKMULT_SPECIAL)
838 clkmult = S626_CLKMULT_1X;
839 break;
840 }
841 cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
842 crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
843
844 /*
845 * Force positive index polarity if IndxSrc is software-driven only,
846 * otherwise pass it through.
847 */
848 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
849 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
850
851 /*
852 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
853 * enable mask to indicate the counter interrupt is disabled.
854 */
855 if (disable_int_src)
856 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
857 S626_INDXMASK(chan));
858
859 /*
860 * While retaining CounterA and LatchSrc configurations, program the
861 * new counter operating mode.
862 */
863 s626_debi_replace(dev, S626_LP_CRA(chan),
864 ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
865 s626_debi_replace(dev, S626_LP_CRB(chan),
866 S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
867 }
868
869 static void s626_set_mode(struct comedi_device *dev,
870 unsigned int chan,
871 u16 setup, u16 disable_int_src)
872 {
873 if (chan < 3)
874 s626_set_mode_a(dev, chan, setup, disable_int_src);
875 else
876 s626_set_mode_b(dev, chan, setup, disable_int_src);
877 }
878
879 /*
880 * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index.
881 */
882 static void s626_set_enable(struct comedi_device *dev,
883 unsigned int chan, u16 enab)
884 {
885 unsigned int mask = S626_CRBMSK_INTCTRL;
886 unsigned int set;
887
888 if (chan < 3) {
889 mask |= S626_CRBMSK_CLKENAB_A;
890 set = S626_SET_CRB_CLKENAB_A(enab);
891 } else {
892 mask |= S626_CRBMSK_CLKENAB_B;
893 set = S626_SET_CRB_CLKENAB_B(enab);
894 }
895 s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
896 }
897
898 /*
899 * Return/set the event that will trigger transfer of the preload
900 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
901 * 2=OverflowA (B counters only), 3=disabled.
902 */
903 static void s626_set_load_trig(struct comedi_device *dev,
904 unsigned int chan, u16 trig)
905 {
906 u16 reg;
907 u16 mask;
908 u16 set;
909
910 if (chan < 3) {
911 reg = S626_LP_CRA(chan);
912 mask = S626_CRAMSK_LOADSRC_A;
913 set = S626_SET_CRA_LOADSRC_A(trig);
914 } else {
915 reg = S626_LP_CRB(chan);
916 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
917 set = S626_SET_CRB_LOADSRC_B(trig);
918 }
919 s626_debi_replace(dev, reg, ~mask, set);
920 }
921
922 /*
923 * Return/set counter interrupt source and clear any captured
924 * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly,
925 * 2=IndexOnly, 3=IndexAndOverflow.
926 */
927 static void s626_set_int_src(struct comedi_device *dev,
928 unsigned int chan, u16 int_source)
929 {
930 struct s626_private *devpriv = dev->private;
931 u16 cra_reg = S626_LP_CRA(chan);
932 u16 crb_reg = S626_LP_CRB(chan);
933
934 if (chan < 3) {
935 /* Reset any pending counter overflow or index captures */
936 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
937 S626_SET_CRB_INTRESETCMD(1) |
938 S626_SET_CRB_INTRESET_A(1));
939
940 /* Program counter interrupt source */
941 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
942 S626_SET_CRA_INTSRC_A(int_source));
943 } else {
944 u16 crb;
945
946 /* Cache writeable CRB register image */
947 crb = s626_debi_read(dev, crb_reg);
948 crb &= ~S626_CRBMSK_INTCTRL;
949
950 /* Reset any pending counter overflow or index captures */
951 s626_debi_write(dev, crb_reg,
952 crb | S626_SET_CRB_INTRESETCMD(1) |
953 S626_SET_CRB_INTRESET_B(1));
954
955 /* Program counter interrupt source */
956 s626_debi_write(dev, crb_reg,
957 (crb & ~S626_CRBMSK_INTSRC_B) |
958 S626_SET_CRB_INTSRC_B(int_source));
959 }
960
961 /* Update MISC2 interrupt enable mask. */
962 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
963 S626_INDXMASK(chan));
964 switch (int_source) {
965 case 0:
966 default:
967 break;
968 case 1:
969 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
970 break;
971 case 2:
972 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
973 break;
974 case 3:
975 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
976 S626_INDXMASK(chan));
977 break;
978 }
979 }
980
981 /*
982 * Generate an index pulse.
983 */
984 static void s626_pulse_index(struct comedi_device *dev,
985 unsigned int chan)
986 {
987 if (chan < 3) {
988 u16 cra;
989
990 cra = s626_debi_read(dev, S626_LP_CRA(chan));
991
992 /* Pulse index */
993 s626_debi_write(dev, S626_LP_CRA(chan),
994 (cra ^ S626_CRAMSK_INDXPOL_A));
995 s626_debi_write(dev, S626_LP_CRA(chan), cra);
996 } else {
997 u16 crb;
998
999 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1000 crb &= ~S626_CRBMSK_INTCTRL;
1001
1002 /* Pulse index */
1003 s626_debi_write(dev, S626_LP_CRB(chan),
1004 (crb ^ S626_CRBMSK_INDXPOL_B));
1005 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1006 }
1007 }
1008
1009 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1010 {
1011 return ((data >> 18) & 0x3fff) ^ 0x2000;
1012 }
1013
1014 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1015 {
1016 unsigned int group = chan / 16;
1017 unsigned int mask = 1 << (chan - (16 * group));
1018 unsigned int status;
1019
1020 /* set channel to capture positive edge */
1021 status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1022 s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1023
1024 /* enable interrupt on selected channel */
1025 status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1026 s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1027
1028 /* enable edge capture write command */
1029 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1030
1031 /* enable edge capture on selected channel */
1032 status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1033 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1034
1035 return 0;
1036 }
1037
1038 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1039 unsigned int mask)
1040 {
1041 /* disable edge capture write command */
1042 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1043
1044 /* enable edge capture on selected channel */
1045 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1046
1047 return 0;
1048 }
1049
1050 static int s626_dio_clear_irq(struct comedi_device *dev)
1051 {
1052 unsigned int group;
1053
1054 /* disable edge capture write command */
1055 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1056
1057 /* clear all dio pending events and interrupt */
1058 for (group = 0; group < S626_DIO_BANKS; group++)
1059 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1060
1061 return 0;
1062 }
1063
1064 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1065 u16 irqbit, u8 group)
1066 {
1067 struct s626_private *devpriv = dev->private;
1068 struct comedi_subdevice *s = dev->read_subdev;
1069 struct comedi_cmd *cmd = &s->async->cmd;
1070
1071 s626_dio_reset_irq(dev, group, irqbit);
1072
1073 if (devpriv->ai_cmd_running) {
1074 /* check if interrupt is an ai acquisition start trigger */
1075 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1076 cmd->start_src == TRIG_EXT) {
1077 /* Start executing the RPS program */
1078 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1079
1080 if (cmd->scan_begin_src == TRIG_EXT)
1081 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1082 }
1083 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1084 cmd->scan_begin_src == TRIG_EXT) {
1085 /* Trigger ADC scan loop start */
1086 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1087
1088 if (cmd->convert_src == TRIG_EXT) {
1089 devpriv->ai_convert_count = cmd->chanlist_len;
1090
1091 s626_dio_set_irq(dev, cmd->convert_arg);
1092 }
1093
1094 if (cmd->convert_src == TRIG_TIMER) {
1095 devpriv->ai_convert_count = cmd->chanlist_len;
1096 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1097 }
1098 }
1099 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1100 cmd->convert_src == TRIG_EXT) {
1101 /* Trigger ADC scan loop start */
1102 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1103
1104 devpriv->ai_convert_count--;
1105 if (devpriv->ai_convert_count > 0)
1106 s626_dio_set_irq(dev, cmd->convert_arg);
1107 }
1108 }
1109 }
1110
1111 static void s626_check_dio_interrupts(struct comedi_device *dev)
1112 {
1113 u16 irqbit;
1114 u8 group;
1115
1116 for (group = 0; group < S626_DIO_BANKS; group++) {
1117 /* read interrupt type */
1118 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1119
1120 /* check if interrupt is generated from dio channels */
1121 if (irqbit) {
1122 s626_handle_dio_interrupt(dev, irqbit, group);
1123 return;
1124 }
1125 }
1126 }
1127
1128 static void s626_check_counter_interrupts(struct comedi_device *dev)
1129 {
1130 struct s626_private *devpriv = dev->private;
1131 struct comedi_subdevice *s = dev->read_subdev;
1132 struct comedi_async *async = s->async;
1133 struct comedi_cmd *cmd = &async->cmd;
1134 u16 irqbit;
1135
1136 /* read interrupt type */
1137 irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1138
1139 /* check interrupt on counters */
1140 if (irqbit & S626_IRQ_COINT1A) {
1141 /* clear interrupt capture flag */
1142 s626_reset_cap_flags(dev, 0);
1143 }
1144 if (irqbit & S626_IRQ_COINT2A) {
1145 /* clear interrupt capture flag */
1146 s626_reset_cap_flags(dev, 1);
1147 }
1148 if (irqbit & S626_IRQ_COINT3A) {
1149 /* clear interrupt capture flag */
1150 s626_reset_cap_flags(dev, 2);
1151 }
1152 if (irqbit & S626_IRQ_COINT1B) {
1153 /* clear interrupt capture flag */
1154 s626_reset_cap_flags(dev, 3);
1155 }
1156 if (irqbit & S626_IRQ_COINT2B) {
1157 /* clear interrupt capture flag */
1158 s626_reset_cap_flags(dev, 4);
1159
1160 if (devpriv->ai_convert_count > 0) {
1161 devpriv->ai_convert_count--;
1162 if (devpriv->ai_convert_count == 0)
1163 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1164
1165 if (cmd->convert_src == TRIG_TIMER) {
1166 /* Trigger ADC scan loop start */
1167 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1168 S626_P_MC2);
1169 }
1170 }
1171 }
1172 if (irqbit & S626_IRQ_COINT3B) {
1173 /* clear interrupt capture flag */
1174 s626_reset_cap_flags(dev, 5);
1175
1176 if (cmd->scan_begin_src == TRIG_TIMER) {
1177 /* Trigger ADC scan loop start */
1178 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1179 }
1180
1181 if (cmd->convert_src == TRIG_TIMER) {
1182 devpriv->ai_convert_count = cmd->chanlist_len;
1183 s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1184 }
1185 }
1186 }
1187
1188 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1189 {
1190 struct s626_private *devpriv = dev->private;
1191 struct comedi_subdevice *s = dev->read_subdev;
1192 struct comedi_async *async = s->async;
1193 struct comedi_cmd *cmd = &async->cmd;
1194 /*
1195 * Init ptr to DMA buffer that holds new ADC data. We skip the
1196 * first uint16_t in the buffer because it contains junk data
1197 * from the final ADC of the previous poll list scan.
1198 */
1199 u32 *readaddr = (u32 *)devpriv->ana_buf.logical_base + 1;
1200 int i;
1201
1202 /* get the data and hand it over to comedi */
1203 for (i = 0; i < cmd->chanlist_len; i++) {
1204 unsigned short tempdata;
1205
1206 /*
1207 * Convert ADC data to 16-bit integer values and copy
1208 * to application buffer.
1209 */
1210 tempdata = s626_ai_reg_to_uint(*readaddr);
1211 readaddr++;
1212
1213 comedi_buf_write_samples(s, &tempdata, 1);
1214 }
1215
1216 if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg)
1217 async->events |= COMEDI_CB_EOA;
1218
1219 if (async->events & COMEDI_CB_CANCEL_MASK)
1220 devpriv->ai_cmd_running = 0;
1221
1222 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1223 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1224
1225 comedi_handle_events(dev, s);
1226
1227 return !devpriv->ai_cmd_running;
1228 }
1229
1230 static irqreturn_t s626_irq_handler(int irq, void *d)
1231 {
1232 struct comedi_device *dev = d;
1233 unsigned long flags;
1234 u32 irqtype, irqstatus;
1235
1236 if (!dev->attached)
1237 return IRQ_NONE;
1238 /* lock to avoid race with comedi_poll */
1239 spin_lock_irqsave(&dev->spinlock, flags);
1240
1241 /* save interrupt enable register state */
1242 irqstatus = readl(dev->mmio + S626_P_IER);
1243
1244 /* read interrupt type */
1245 irqtype = readl(dev->mmio + S626_P_ISR);
1246
1247 /* disable master interrupt */
1248 writel(0, dev->mmio + S626_P_IER);
1249
1250 /* clear interrupt */
1251 writel(irqtype, dev->mmio + S626_P_ISR);
1252
1253 switch (irqtype) {
1254 case S626_IRQ_RPS1: /* end_of_scan occurs */
1255 if (s626_handle_eos_interrupt(dev))
1256 irqstatus = 0;
1257 break;
1258 case S626_IRQ_GPIO3: /* check dio and counter interrupt */
1259 /* s626_dio_clear_irq(dev); */
1260 s626_check_dio_interrupts(dev);
1261 s626_check_counter_interrupts(dev);
1262 break;
1263 }
1264
1265 /* enable interrupt */
1266 writel(irqstatus, dev->mmio + S626_P_IER);
1267
1268 spin_unlock_irqrestore(&dev->spinlock, flags);
1269 return IRQ_HANDLED;
1270 }
1271
1272 /*
1273 * This function builds the RPS program for hardware driven acquisition.
1274 */
1275 static void s626_reset_adc(struct comedi_device *dev, u8 *ppl)
1276 {
1277 struct s626_private *devpriv = dev->private;
1278 struct comedi_subdevice *s = dev->read_subdev;
1279 struct comedi_cmd *cmd = &s->async->cmd;
1280 u32 *rps;
1281 u32 jmp_adrs;
1282 u16 i;
1283 u16 n;
1284 u32 local_ppl;
1285
1286 /* Stop RPS program in case it is currently running */
1287 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1288
1289 /* Set starting logical address to write RPS commands. */
1290 rps = (u32 *)devpriv->rps_buf.logical_base;
1291
1292 /* Initialize RPS instruction pointer */
1293 writel((u32)devpriv->rps_buf.physical_base,
1294 dev->mmio + S626_P_RPSADDR1);
1295
1296 /* Construct RPS program in rps_buf DMA buffer */
1297 if (cmd->scan_begin_src != TRIG_FOLLOW) {
1298 /* Wait for Start trigger. */
1299 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1300 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1301 }
1302
1303 /*
1304 * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1305 * because the first RPS DEBI Write following a non-RPS DEBI write
1306 * seems to always fail. If we don't do this dummy write, the ADC
1307 * gain might not be set to the value required for the first slot in
1308 * the poll list; the ADC gain would instead remain unchanged from
1309 * the previously programmed value.
1310 */
1311 /* Write DEBI Write command and address to shadow RAM. */
1312 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1313 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1314 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1315 /* Write DEBI immediate data to shadow RAM: */
1316 *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */
1317 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1318 /* Reset "shadow RAM uploaded" flag. */
1319 /* Invoke shadow RAM upload. */
1320 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1321 /* Wait for shadow upload to finish. */
1322 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1323
1324 /*
1325 * Digitize all slots in the poll list. This is implemented as a
1326 * for loop to limit the slot count to 16 in case the application
1327 * forgot to set the S626_EOPL flag in the final slot.
1328 */
1329 for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1330 devpriv->adc_items++) {
1331 /*
1332 * Convert application's poll list item to private board class
1333 * format. Each app poll list item is an uint8_t with form
1334 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1335 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1336 */
1337 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1338 S626_GSEL_BIPOLAR10V);
1339
1340 /* Switch ADC analog gain. */
1341 /* Write DEBI command and address to shadow RAM. */
1342 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1343 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1344 /* Write DEBI immediate data to shadow RAM. */
1345 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1346 *rps++ = local_ppl;
1347 /* Reset "shadow RAM uploaded" flag. */
1348 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1349 /* Invoke shadow RAM upload. */
1350 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1351 /* Wait for shadow upload to finish. */
1352 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1353 /* Select ADC analog input channel. */
1354 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1355 /* Write DEBI command and address to shadow RAM. */
1356 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1357 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1358 /* Write DEBI immediate data to shadow RAM. */
1359 *rps++ = local_ppl;
1360 /* Reset "shadow RAM uploaded" flag. */
1361 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1362 /* Invoke shadow RAM upload. */
1363 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1364 /* Wait for shadow upload to finish. */
1365 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1366
1367 /*
1368 * Delay at least 10 microseconds for analog input settling.
1369 * Instead of padding with NOPs, we use S626_RPS_JUMP
1370 * instructions here; this allows us to produce a longer delay
1371 * than is possible with NOPs because each S626_RPS_JUMP
1372 * flushes the RPS' instruction prefetch pipeline.
1373 */
1374 jmp_adrs =
1375 (u32)devpriv->rps_buf.physical_base +
1376 (u32)((unsigned long)rps -
1377 (unsigned long)devpriv->rps_buf.logical_base);
1378 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1379 jmp_adrs += 8; /* Repeat to implement time delay: */
1380 /* Jump to next RPS instruction. */
1381 *rps++ = S626_RPS_JUMP;
1382 *rps++ = jmp_adrs;
1383 }
1384
1385 if (cmd->convert_src != TRIG_NOW) {
1386 /* Wait for Start trigger. */
1387 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1388 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1389 }
1390 /* Start ADC by pulsing GPIO1. */
1391 /* Begin ADC Start pulse. */
1392 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1393 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1394 *rps++ = S626_RPS_NOP;
1395 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1396 /* End ADC Start pulse. */
1397 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1398 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1399 /*
1400 * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1401 * busy) and for data from previous conversion to shift into FB
1402 * BUFFER 1 register.
1403 */
1404 /* Wait for ADC done. */
1405 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1406
1407 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1408 *rps++ = S626_RPS_STREG |
1409 (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1410 *rps++ = (u32)devpriv->ana_buf.physical_base +
1411 (devpriv->adc_items << 2);
1412
1413 /*
1414 * If this slot's EndOfPollList flag is set, all channels have
1415 * now been processed.
1416 */
1417 if (*ppl++ & S626_EOPL) {
1418 devpriv->adc_items++; /* Adjust poll list item count. */
1419 break; /* Exit poll list processing loop. */
1420 }
1421 }
1422
1423 /*
1424 * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1425 * ADC to stabilize for 2 microseconds before starting the final
1426 * (dummy) conversion. This delay is necessary to allow sufficient
1427 * time between last conversion finished and the start of the dummy
1428 * conversion. Without this delay, the last conversion's data value
1429 * is sometimes set to the previous conversion's data value.
1430 */
1431 for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1432 *rps++ = S626_RPS_NOP;
1433
1434 /*
1435 * Start a dummy conversion to cause the data from the last
1436 * conversion of interest to be shifted in.
1437 */
1438 /* Begin ADC Start pulse. */
1439 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1440 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1441 *rps++ = S626_RPS_NOP;
1442 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1443 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1444 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1445
1446 /*
1447 * Wait for the data from the last conversion of interest to arrive
1448 * in FB BUFFER 1 register.
1449 */
1450 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */
1451
1452 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1453 *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1454 *rps++ = (u32)devpriv->ana_buf.physical_base +
1455 (devpriv->adc_items << 2);
1456
1457 /* Indicate ADC scan loop is finished. */
1458 /* Signal ReadADC() that scan is done. */
1459 /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1460
1461 /* invoke interrupt */
1462 if (devpriv->ai_cmd_running == 1)
1463 *rps++ = S626_RPS_IRQ;
1464
1465 /* Restart RPS program at its beginning. */
1466 *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1467 *rps++ = (u32)devpriv->rps_buf.physical_base;
1468
1469 /* End of RPS program build */
1470 }
1471
1472 static int s626_ai_eoc(struct comedi_device *dev,
1473 struct comedi_subdevice *s,
1474 struct comedi_insn *insn,
1475 unsigned long context)
1476 {
1477 unsigned int status;
1478
1479 status = readl(dev->mmio + S626_P_PSR);
1480 if (status & S626_PSR_GPIO2)
1481 return 0;
1482 return -EBUSY;
1483 }
1484
1485 static int s626_ai_insn_read(struct comedi_device *dev,
1486 struct comedi_subdevice *s,
1487 struct comedi_insn *insn,
1488 unsigned int *data)
1489 {
1490 u16 chan = CR_CHAN(insn->chanspec);
1491 u16 range = CR_RANGE(insn->chanspec);
1492 u16 adc_spec = 0;
1493 u32 gpio_image;
1494 u32 tmp;
1495 int ret;
1496 int n;
1497
1498 /*
1499 * Convert application's ADC specification into form
1500 * appropriate for register programming.
1501 */
1502 if (range == 0)
1503 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1504 else
1505 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1506
1507 /* Switch ADC analog gain. */
1508 s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */
1509
1510 /* Select ADC analog input channel. */
1511 s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */
1512
1513 for (n = 0; n < insn->n; n++) {
1514 /* Delay 10 microseconds for analog input settling. */
1515 usleep_range(10, 20);
1516
1517 /* Start ADC by pulsing GPIO1 low */
1518 gpio_image = readl(dev->mmio + S626_P_GPIO);
1519 /* Assert ADC Start command */
1520 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1521 /* and stretch it out */
1522 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1523 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1524 /* Negate ADC Start command */
1525 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1526
1527 /*
1528 * Wait for ADC to complete (GPIO2 is asserted high when
1529 * ADC not busy) and for data from previous conversion to
1530 * shift into FB BUFFER 1 register.
1531 */
1532
1533 /* Wait for ADC done */
1534 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1535 if (ret)
1536 return ret;
1537
1538 /* Fetch ADC data */
1539 if (n != 0) {
1540 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1541 data[n - 1] = s626_ai_reg_to_uint(tmp);
1542 }
1543
1544 /*
1545 * Allow the ADC to stabilize for 4 microseconds before
1546 * starting the next (final) conversion. This delay is
1547 * necessary to allow sufficient time between last
1548 * conversion finished and the start of the next
1549 * conversion. Without this delay, the last conversion's
1550 * data value is sometimes set to the previous
1551 * conversion's data value.
1552 */
1553 udelay(4);
1554 }
1555
1556 /*
1557 * Start a dummy conversion to cause the data from the
1558 * previous conversion to be shifted in.
1559 */
1560 gpio_image = readl(dev->mmio + S626_P_GPIO);
1561 /* Assert ADC Start command */
1562 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1563 /* and stretch it out */
1564 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1565 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1566 /* Negate ADC Start command */
1567 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1568
1569 /* Wait for the data to arrive in FB BUFFER 1 register. */
1570
1571 /* Wait for ADC done */
1572 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1573 if (ret)
1574 return ret;
1575
1576 /* Fetch ADC data from audio interface's input shift register. */
1577
1578 /* Fetch ADC data */
1579 if (n != 0) {
1580 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1581 data[n - 1] = s626_ai_reg_to_uint(tmp);
1582 }
1583
1584 return n;
1585 }
1586
1587 static int s626_ai_load_polllist(u8 *ppl, struct comedi_cmd *cmd)
1588 {
1589 int n;
1590
1591 for (n = 0; n < cmd->chanlist_len; n++) {
1592 if (CR_RANGE(cmd->chanlist[n]) == 0)
1593 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1594 else
1595 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1596 }
1597 if (n != 0)
1598 ppl[n - 1] |= S626_EOPL;
1599
1600 return n;
1601 }
1602
1603 static int s626_ai_inttrig(struct comedi_device *dev,
1604 struct comedi_subdevice *s,
1605 unsigned int trig_num)
1606 {
1607 struct comedi_cmd *cmd = &s->async->cmd;
1608
1609 if (trig_num != cmd->start_arg)
1610 return -EINVAL;
1611
1612 /* Start executing the RPS program */
1613 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1614
1615 s->async->inttrig = NULL;
1616
1617 return 1;
1618 }
1619
1620 /*
1621 * This function doesn't require a particular form, this is just what
1622 * happens to be used in some of the drivers. It should convert ns
1623 * nanoseconds to a counter value suitable for programming the device.
1624 * Also, it should adjust ns so that it cooresponds to the actual time
1625 * that the device will use.
1626 */
1627 static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1628 {
1629 int divider, base;
1630
1631 base = 500; /* 2MHz internal clock */
1632
1633 switch (flags & CMDF_ROUND_MASK) {
1634 case CMDF_ROUND_NEAREST:
1635 default:
1636 divider = DIV_ROUND_CLOSEST(*nanosec, base);
1637 break;
1638 case CMDF_ROUND_DOWN:
1639 divider = (*nanosec) / base;
1640 break;
1641 case CMDF_ROUND_UP:
1642 divider = DIV_ROUND_UP(*nanosec, base);
1643 break;
1644 }
1645
1646 *nanosec = base * divider;
1647 return divider - 1;
1648 }
1649
1650 static void s626_timer_load(struct comedi_device *dev,
1651 unsigned int chan, int tick)
1652 {
1653 u16 setup =
1654 /* Preload upon index. */
1655 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1656 /* Disable hardware index. */
1657 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1658 /* Operating mode is Timer. */
1659 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1660 /* Count direction is Down. */
1661 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1662 /* Clock multiplier is 1x. */
1663 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
1664 /* Enabled by index */
1665 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
1666 u16 value_latchsrc = S626_LATCHSRC_A_INDXA;
1667 /* uint16_t enab = S626_CLKENAB_ALWAYS; */
1668
1669 s626_set_mode(dev, chan, setup, false);
1670
1671 /* Set the preload register */
1672 s626_preload(dev, chan, tick);
1673
1674 /*
1675 * Software index pulse forces the preload register to load
1676 * into the counter
1677 */
1678 s626_set_load_trig(dev, chan, 0);
1679 s626_pulse_index(dev, chan);
1680
1681 /* set reload on counter overflow */
1682 s626_set_load_trig(dev, chan, 1);
1683
1684 /* set interrupt on overflow */
1685 s626_set_int_src(dev, chan, S626_INTSRC_OVER);
1686
1687 s626_set_latch_source(dev, chan, value_latchsrc);
1688 /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
1689 }
1690
1691 /* TO COMPLETE */
1692 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1693 {
1694 struct s626_private *devpriv = dev->private;
1695 u8 ppl[16];
1696 struct comedi_cmd *cmd = &s->async->cmd;
1697 int tick;
1698
1699 if (devpriv->ai_cmd_running) {
1700 dev_err(dev->class_dev,
1701 "%s: Another ai_cmd is running\n", __func__);
1702 return -EBUSY;
1703 }
1704 /* disable interrupt */
1705 writel(0, dev->mmio + S626_P_IER);
1706
1707 /* clear interrupt request */
1708 writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
1709
1710 /* clear any pending interrupt */
1711 s626_dio_clear_irq(dev);
1712 /* s626_enc_clear_irq(dev); */
1713
1714 /* reset ai_cmd_running flag */
1715 devpriv->ai_cmd_running = 0;
1716
1717 s626_ai_load_polllist(ppl, cmd);
1718 devpriv->ai_cmd_running = 1;
1719 devpriv->ai_convert_count = 0;
1720
1721 switch (cmd->scan_begin_src) {
1722 case TRIG_FOLLOW:
1723 break;
1724 case TRIG_TIMER:
1725 /*
1726 * set a counter to generate adc trigger at scan_begin_arg
1727 * interval
1728 */
1729 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
1730
1731 /* load timer value and enable interrupt */
1732 s626_timer_load(dev, 5, tick);
1733 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1734 break;
1735 case TRIG_EXT:
1736 /* set the digital line and interrupt for scan trigger */
1737 if (cmd->start_src != TRIG_EXT)
1738 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1739 break;
1740 }
1741
1742 switch (cmd->convert_src) {
1743 case TRIG_NOW:
1744 break;
1745 case TRIG_TIMER:
1746 /*
1747 * set a counter to generate adc trigger at convert_arg
1748 * interval
1749 */
1750 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
1751
1752 /* load timer value and enable interrupt */
1753 s626_timer_load(dev, 4, tick);
1754 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1755 break;
1756 case TRIG_EXT:
1757 /* set the digital line and interrupt for convert trigger */
1758 if (cmd->scan_begin_src != TRIG_EXT &&
1759 cmd->start_src == TRIG_EXT)
1760 s626_dio_set_irq(dev, cmd->convert_arg);
1761 break;
1762 }
1763
1764 s626_reset_adc(dev, ppl);
1765
1766 switch (cmd->start_src) {
1767 case TRIG_NOW:
1768 /* Trigger ADC scan loop start */
1769 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
1770
1771 /* Start executing the RPS program */
1772 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1773 s->async->inttrig = NULL;
1774 break;
1775 case TRIG_EXT:
1776 /* configure DIO channel for acquisition trigger */
1777 s626_dio_set_irq(dev, cmd->start_arg);
1778 s->async->inttrig = NULL;
1779 break;
1780 case TRIG_INT:
1781 s->async->inttrig = s626_ai_inttrig;
1782 break;
1783 }
1784
1785 /* enable interrupt */
1786 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
1787
1788 return 0;
1789 }
1790
1791 static int s626_ai_cmdtest(struct comedi_device *dev,
1792 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1793 {
1794 int err = 0;
1795 unsigned int arg;
1796
1797 /* Step 1 : check if triggers are trivially valid */
1798
1799 err |= comedi_check_trigger_src(&cmd->start_src,
1800 TRIG_NOW | TRIG_INT | TRIG_EXT);
1801 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
1802 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
1803 err |= comedi_check_trigger_src(&cmd->convert_src,
1804 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
1805 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1806 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1807
1808 if (err)
1809 return 1;
1810
1811 /* Step 2a : make sure trigger sources are unique */
1812
1813 err |= comedi_check_trigger_is_unique(cmd->start_src);
1814 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
1815 err |= comedi_check_trigger_is_unique(cmd->convert_src);
1816 err |= comedi_check_trigger_is_unique(cmd->stop_src);
1817
1818 /* Step 2b : and mutually compatible */
1819
1820 if (err)
1821 return 2;
1822
1823 /* Step 3: check if arguments are trivially valid */
1824
1825 switch (cmd->start_src) {
1826 case TRIG_NOW:
1827 case TRIG_INT:
1828 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
1829 break;
1830 case TRIG_EXT:
1831 err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39);
1832 break;
1833 }
1834
1835 if (cmd->scan_begin_src == TRIG_EXT)
1836 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
1837 if (cmd->convert_src == TRIG_EXT)
1838 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39);
1839
1840 #define S626_MAX_SPEED 200000 /* in nanoseconds */
1841 #define S626_MIN_SPEED 2000000000 /* in nanoseconds */
1842
1843 if (cmd->scan_begin_src == TRIG_TIMER) {
1844 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
1845 S626_MAX_SPEED);
1846 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
1847 S626_MIN_SPEED);
1848 } else {
1849 /*
1850 * external trigger
1851 * should be level/edge, hi/lo specification here
1852 * should specify multiple external triggers
1853 * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
1854 */
1855 }
1856 if (cmd->convert_src == TRIG_TIMER) {
1857 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
1858 S626_MAX_SPEED);
1859 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
1860 S626_MIN_SPEED);
1861 } else {
1862 /*
1863 * external trigger - see above
1864 * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
1865 */
1866 }
1867
1868 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
1869 cmd->chanlist_len);
1870
1871 if (cmd->stop_src == TRIG_COUNT)
1872 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
1873 else /* TRIG_NONE */
1874 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
1875
1876 if (err)
1877 return 3;
1878
1879 /* step 4: fix up any arguments */
1880
1881 if (cmd->scan_begin_src == TRIG_TIMER) {
1882 arg = cmd->scan_begin_arg;
1883 s626_ns_to_timer(&arg, cmd->flags);
1884 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
1885 }
1886
1887 if (cmd->convert_src == TRIG_TIMER) {
1888 arg = cmd->convert_arg;
1889 s626_ns_to_timer(&arg, cmd->flags);
1890 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
1891
1892 if (cmd->scan_begin_src == TRIG_TIMER) {
1893 arg = cmd->convert_arg * cmd->scan_end_arg;
1894 err |= comedi_check_trigger_arg_min(
1895 &cmd->scan_begin_arg,
1896 arg);
1897 }
1898 }
1899
1900 if (err)
1901 return 4;
1902
1903 return 0;
1904 }
1905
1906 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1907 {
1908 struct s626_private *devpriv = dev->private;
1909
1910 /* Stop RPS program in case it is currently running */
1911 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1912
1913 /* disable master interrupt */
1914 writel(0, dev->mmio + S626_P_IER);
1915
1916 devpriv->ai_cmd_running = 0;
1917
1918 return 0;
1919 }
1920
1921 static int s626_ao_insn_write(struct comedi_device *dev,
1922 struct comedi_subdevice *s,
1923 struct comedi_insn *insn,
1924 unsigned int *data)
1925 {
1926 unsigned int chan = CR_CHAN(insn->chanspec);
1927 int i;
1928
1929 for (i = 0; i < insn->n; i++) {
1930 s16 dacdata = (s16)data[i];
1931 int ret;
1932
1933 dacdata -= (0x1fff);
1934
1935 ret = s626_set_dac(dev, chan, dacdata);
1936 if (ret)
1937 return ret;
1938
1939 s->readback[chan] = data[i];
1940 }
1941
1942 return insn->n;
1943 }
1944
1945 /* *************** DIGITAL I/O FUNCTIONS *************** */
1946
1947 /*
1948 * All DIO functions address a group of DIO channels by means of
1949 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
1950 * ports A, B and C, respectively.
1951 */
1952
1953 static void s626_dio_init(struct comedi_device *dev)
1954 {
1955 u16 group;
1956
1957 /* Prepare to treat writes to WRCapSel as capture disables. */
1958 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1959
1960 /* For each group of sixteen channels ... */
1961 for (group = 0; group < S626_DIO_BANKS; group++) {
1962 /* Disable all interrupts */
1963 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
1964 /* Disable all event captures */
1965 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1966 /* Init all DIOs to default edge polarity */
1967 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
1968 /* Program all outputs to inactive state */
1969 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
1970 }
1971 }
1972
1973 static int s626_dio_insn_bits(struct comedi_device *dev,
1974 struct comedi_subdevice *s,
1975 struct comedi_insn *insn,
1976 unsigned int *data)
1977 {
1978 unsigned long group = (unsigned long)s->private;
1979
1980 if (comedi_dio_update_state(s, data))
1981 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
1982
1983 data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
1984
1985 return insn->n;
1986 }
1987
1988 static int s626_dio_insn_config(struct comedi_device *dev,
1989 struct comedi_subdevice *s,
1990 struct comedi_insn *insn,
1991 unsigned int *data)
1992 {
1993 unsigned long group = (unsigned long)s->private;
1994 int ret;
1995
1996 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1997 if (ret)
1998 return ret;
1999
2000 s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2001
2002 return insn->n;
2003 }
2004
2005 /*
2006 * Now this function initializes the value of the counter (data[0])
2007 * and set the subdevice. To complete with trigger and interrupt
2008 * configuration.
2009 *
2010 * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2011 * what is being configured, but this function appears to be using data[0]
2012 * as a variable.
2013 */
2014 static int s626_enc_insn_config(struct comedi_device *dev,
2015 struct comedi_subdevice *s,
2016 struct comedi_insn *insn, unsigned int *data)
2017 {
2018 unsigned int chan = CR_CHAN(insn->chanspec);
2019 u16 setup =
2020 /* Preload upon index. */
2021 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2022 /* Disable hardware index. */
2023 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2024 /* Operating mode is Counter. */
2025 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2026 /* Active high clock. */
2027 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2028 /* Clock multiplier is 1x. */
2029 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2030 /* Enabled by index */
2031 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2032 /* uint16_t disable_int_src = true; */
2033 /* uint32_t Preloadvalue; //Counter initial value */
2034 u16 value_latchsrc = S626_LATCHSRC_AB_READ;
2035 u16 enab = S626_CLKENAB_ALWAYS;
2036
2037 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2038
2039 s626_set_mode(dev, chan, setup, true);
2040 s626_preload(dev, chan, data[0]);
2041 s626_pulse_index(dev, chan);
2042 s626_set_latch_source(dev, chan, value_latchsrc);
2043 s626_set_enable(dev, chan, (enab != 0));
2044
2045 return insn->n;
2046 }
2047
2048 static int s626_enc_insn_read(struct comedi_device *dev,
2049 struct comedi_subdevice *s,
2050 struct comedi_insn *insn,
2051 unsigned int *data)
2052 {
2053 unsigned int chan = CR_CHAN(insn->chanspec);
2054 u16 cntr_latch_reg = S626_LP_CNTR(chan);
2055 int i;
2056
2057 for (i = 0; i < insn->n; i++) {
2058 unsigned int val;
2059
2060 /*
2061 * Read the counter's output latch LSW/MSW.
2062 * Latches on LSW read.
2063 */
2064 val = s626_debi_read(dev, cntr_latch_reg);
2065 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2066 data[i] = val;
2067 }
2068
2069 return insn->n;
2070 }
2071
2072 static int s626_enc_insn_write(struct comedi_device *dev,
2073 struct comedi_subdevice *s,
2074 struct comedi_insn *insn, unsigned int *data)
2075 {
2076 unsigned int chan = CR_CHAN(insn->chanspec);
2077
2078 /* Set the preload register */
2079 s626_preload(dev, chan, data[0]);
2080
2081 /*
2082 * Software index pulse forces the preload register to load
2083 * into the counter
2084 */
2085 s626_set_load_trig(dev, chan, 0);
2086 s626_pulse_index(dev, chan);
2087 s626_set_load_trig(dev, chan, 2);
2088
2089 return 1;
2090 }
2091
2092 static void s626_write_misc2(struct comedi_device *dev, u16 new_image)
2093 {
2094 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2095 s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2096 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2097 }
2098
2099 static void s626_counters_init(struct comedi_device *dev)
2100 {
2101 int chan;
2102 u16 setup =
2103 /* Preload upon index. */
2104 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2105 /* Disable hardware index. */
2106 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2107 /* Operating mode is counter. */
2108 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2109 /* Active high clock. */
2110 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2111 /* Clock multiplier is 1x. */
2112 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2113 /* Enabled by index */
2114 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2115
2116 /*
2117 * Disable all counter interrupts and clear any captured counter events.
2118 */
2119 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2120 s626_set_mode(dev, chan, setup, true);
2121 s626_set_int_src(dev, chan, 0);
2122 s626_reset_cap_flags(dev, chan);
2123 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2124 }
2125 }
2126
2127 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2128 {
2129 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2130 struct s626_private *devpriv = dev->private;
2131 void *addr;
2132 dma_addr_t appdma;
2133
2134 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2135 if (!addr)
2136 return -ENOMEM;
2137 devpriv->ana_buf.logical_base = addr;
2138 devpriv->ana_buf.physical_base = appdma;
2139
2140 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2141 if (!addr)
2142 return -ENOMEM;
2143 devpriv->rps_buf.logical_base = addr;
2144 devpriv->rps_buf.physical_base = appdma;
2145
2146 return 0;
2147 }
2148
2149 static void s626_free_dma_buffers(struct comedi_device *dev)
2150 {
2151 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2152 struct s626_private *devpriv = dev->private;
2153
2154 if (!devpriv)
2155 return;
2156
2157 if (devpriv->rps_buf.logical_base)
2158 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2159 devpriv->rps_buf.logical_base,
2160 devpriv->rps_buf.physical_base);
2161 if (devpriv->ana_buf.logical_base)
2162 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2163 devpriv->ana_buf.logical_base,
2164 devpriv->ana_buf.physical_base);
2165 }
2166
2167 static int s626_initialize(struct comedi_device *dev)
2168 {
2169 struct s626_private *devpriv = dev->private;
2170 dma_addr_t phys_buf;
2171 u16 chan;
2172 int i;
2173 int ret;
2174
2175 /* Enable DEBI and audio pins, enable I2C interface */
2176 s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2177 S626_P_MC1);
2178
2179 /*
2180 * Configure DEBI operating mode
2181 *
2182 * Local bus is 16 bits wide
2183 * Declare DEBI transfer timeout interval
2184 * Set up byte lane steering
2185 * Intel-compatible local bus (DEBI never times out)
2186 */
2187 writel(S626_DEBI_CFG_SLAVE16 |
2188 (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2189 S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2190
2191 /* Disable MMU paging */
2192 writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2193
2194 /* Init GPIO so that ADC Start* is negated */
2195 writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2196
2197 /* I2C device address for onboard eeprom (revb) */
2198 devpriv->i2c_adrs = 0xA0;
2199
2200 /*
2201 * Issue an I2C ABORT command to halt any I2C
2202 * operation in progress and reset BUSY flag.
2203 */
2204 writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2205 dev->mmio + S626_P_I2CSTAT);
2206 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2207 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2208 if (ret)
2209 return ret;
2210
2211 /*
2212 * Per SAA7146 data sheet, write to STATUS
2213 * reg twice to reset all I2C error flags.
2214 */
2215 for (i = 0; i < 2; i++) {
2216 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2217 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2218 ret = comedi_timeout(dev, NULL,
2219 NULL, s626_i2c_handshake_eoc, 0);
2220 if (ret)
2221 return ret;
2222 }
2223
2224 /*
2225 * Init audio interface functional attributes: set DAC/ADC
2226 * serial clock rates, invert DAC serial clock so that
2227 * DAC data setup times are satisfied, enable DAC serial
2228 * clock out.
2229 */
2230 writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2231
2232 /*
2233 * Set up TSL1 slot list, which is used to control the
2234 * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2235 * S626_SIB_A1 = store data uint8_t at next available location
2236 * in FB BUFFER1 register.
2237 */
2238 writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2239 writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2240 dev->mmio + S626_P_TSL1 + 4);
2241
2242 /* Enable TSL1 slot list so that it executes all the time */
2243 writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2244
2245 /*
2246 * Initialize RPS registers used for ADC
2247 */
2248
2249 /* Physical start of RPS program */
2250 writel((u32)devpriv->rps_buf.physical_base,
2251 dev->mmio + S626_P_RPSADDR1);
2252 /* RPS program performs no explicit mem writes */
2253 writel(0, dev->mmio + S626_P_RPSPAGE1);
2254 /* Disable RPS timeouts */
2255 writel(0, dev->mmio + S626_P_RPS1_TOUT);
2256
2257 #if 0
2258 /*
2259 * SAA7146 BUG WORKAROUND
2260 *
2261 * Initialize SAA7146 ADC interface to a known state by
2262 * invoking ADCs until FB BUFFER 1 register shows that it
2263 * is correctly receiving ADC data. This is necessary
2264 * because the SAA7146 ADC interface does not start up in
2265 * a defined state after a PCI reset.
2266 */
2267 {
2268 struct comedi_subdevice *s = dev->read_subdev;
2269 u8 poll_list;
2270 u16 adc_data;
2271 u16 start_val;
2272 u16 index;
2273 unsigned int data[16];
2274
2275 /* Create a simple polling list for analog input channel 0 */
2276 poll_list = S626_EOPL;
2277 s626_reset_adc(dev, &poll_list);
2278
2279 /* Get initial ADC value */
2280 s626_ai_rinsn(dev, s, NULL, data);
2281 start_val = data[0];
2282
2283 /*
2284 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2285 * EXECUTION.
2286 *
2287 * Invoke ADCs until the new ADC value differs from the initial
2288 * value or a timeout occurs. The timeout protects against the
2289 * possibility that the driver is restarting and the ADC data is
2290 * a fixed value resulting from the applied ADC analog input
2291 * being unusually quiet or at the rail.
2292 */
2293 for (index = 0; index < 500; index++) {
2294 s626_ai_rinsn(dev, s, NULL, data);
2295 adc_data = data[0];
2296 if (adc_data != start_val)
2297 break;
2298 }
2299 }
2300 #endif /* SAA7146 BUG WORKAROUND */
2301
2302 /*
2303 * Initialize the DAC interface
2304 */
2305
2306 /*
2307 * Init Audio2's output DMAC attributes:
2308 * burst length = 1 DWORD
2309 * threshold = 1 DWORD.
2310 */
2311 writel(0, dev->mmio + S626_P_PCI_BT_A);
2312
2313 /*
2314 * Init Audio2's output DMA physical addresses. The protection
2315 * address is set to 1 DWORD past the base address so that a
2316 * single DWORD will be transferred each time a DMA transfer is
2317 * enabled.
2318 */
2319 phys_buf = devpriv->ana_buf.physical_base +
2320 (S626_DAC_WDMABUF_OS * sizeof(u32));
2321 writel((u32)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2322 writel((u32)(phys_buf + sizeof(u32)),
2323 dev->mmio + S626_P_PROTA2_OUT);
2324
2325 /*
2326 * Cache Audio2's output DMA buffer logical address. This is
2327 * where DAC data is buffered for A2 output DMA transfers.
2328 */
2329 devpriv->dac_wbuf = (u32 *)devpriv->ana_buf.logical_base +
2330 S626_DAC_WDMABUF_OS;
2331
2332 /*
2333 * Audio2's output channels does not use paging. The
2334 * protection violation handling bit is set so that the
2335 * DMAC will automatically halt and its PCI address pointer
2336 * will be reset when the protection address is reached.
2337 */
2338 writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2339
2340 /*
2341 * Initialize time slot list 2 (TSL2), which is used to control
2342 * the clock generation for and serialization of data to be sent
2343 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2344 * execution; this permits other slots to be safely modified
2345 * without first turning off the TSL sequencer (which is
2346 * apparently impossible to do). Also, SD3 (which is driven by a
2347 * pull-up resistor) is shifted in and stored to the MSB of
2348 * FB_BUFFER2 to be used as evidence that the slot sequence has
2349 * not yet finished executing.
2350 */
2351
2352 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2353 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2354 dev->mmio + S626_VECTPORT(0));
2355
2356 /*
2357 * Initialize slot 1, which is constant. Slot 1 causes a
2358 * DWORD to be transferred from audio channel 2's output FIFO
2359 * to the FIFO's output buffer so that it can be serialized
2360 * and sent to the DAC during subsequent slots. All remaining
2361 * slots are dynamically populated as required by the target
2362 * DAC device.
2363 */
2364
2365 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2366 writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2367
2368 /* Start DAC's audio interface (TSL2) running */
2369 writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2370
2371 /*
2372 * Init Trim DACs to calibrated values. Do it twice because the
2373 * SAA7146 audio channel does not always reset properly and
2374 * sometimes causes the first few TrimDAC writes to malfunction.
2375 */
2376 s626_load_trim_dacs(dev);
2377 ret = s626_load_trim_dacs(dev);
2378 if (ret)
2379 return ret;
2380
2381 /*
2382 * Manually init all gate array hardware in case this is a soft
2383 * reset (we have no way of determining whether this is a warm
2384 * or cold start). This is necessary because the gate array will
2385 * reset only in response to a PCI hard reset; there is no soft
2386 * reset function.
2387 */
2388
2389 /*
2390 * Init all DAC outputs to 0V and init all DAC setpoint and
2391 * polarity images.
2392 */
2393 for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2394 ret = s626_set_dac(dev, chan, 0);
2395 if (ret)
2396 return ret;
2397 }
2398
2399 /* Init counters */
2400 s626_counters_init(dev);
2401
2402 /*
2403 * Without modifying the state of the Battery Backup enab, disable
2404 * the watchdog timer, set DIO channels 0-5 to operate in the
2405 * standard DIO (vs. counter overflow) mode, disable the battery
2406 * charger, and reset the watchdog interval selector to zero.
2407 */
2408 s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2409 S626_MISC2_BATT_ENABLE));
2410
2411 /* Initialize the digital I/O subsystem */
2412 s626_dio_init(dev);
2413
2414 return 0;
2415 }
2416
2417 static int s626_auto_attach(struct comedi_device *dev,
2418 unsigned long context_unused)
2419 {
2420 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2421 struct s626_private *devpriv;
2422 struct comedi_subdevice *s;
2423 int ret;
2424
2425 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2426 if (!devpriv)
2427 return -ENOMEM;
2428
2429 ret = comedi_pci_enable(dev);
2430 if (ret)
2431 return ret;
2432
2433 dev->mmio = pci_ioremap_bar(pcidev, 0);
2434 if (!dev->mmio)
2435 return -ENOMEM;
2436
2437 /* disable master interrupt */
2438 writel(0, dev->mmio + S626_P_IER);
2439
2440 /* soft reset */
2441 writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2442
2443 /* DMA FIXME DMA// */
2444
2445 ret = s626_allocate_dma_buffers(dev);
2446 if (ret)
2447 return ret;
2448
2449 if (pcidev->irq) {
2450 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2451 dev->board_name, dev);
2452
2453 if (ret == 0)
2454 dev->irq = pcidev->irq;
2455 }
2456
2457 ret = comedi_alloc_subdevices(dev, 6);
2458 if (ret)
2459 return ret;
2460
2461 s = &dev->subdevices[0];
2462 /* analog input subdevice */
2463 s->type = COMEDI_SUBD_AI;
2464 s->subdev_flags = SDF_READABLE | SDF_DIFF;
2465 s->n_chan = S626_ADC_CHANNELS;
2466 s->maxdata = 0x3fff;
2467 s->range_table = &s626_range_table;
2468 s->len_chanlist = S626_ADC_CHANNELS;
2469 s->insn_read = s626_ai_insn_read;
2470 if (dev->irq) {
2471 dev->read_subdev = s;
2472 s->subdev_flags |= SDF_CMD_READ;
2473 s->do_cmd = s626_ai_cmd;
2474 s->do_cmdtest = s626_ai_cmdtest;
2475 s->cancel = s626_ai_cancel;
2476 }
2477
2478 s = &dev->subdevices[1];
2479 /* analog output subdevice */
2480 s->type = COMEDI_SUBD_AO;
2481 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2482 s->n_chan = S626_DAC_CHANNELS;
2483 s->maxdata = 0x3fff;
2484 s->range_table = &range_bipolar10;
2485 s->insn_write = s626_ao_insn_write;
2486
2487 ret = comedi_alloc_subdev_readback(s);
2488 if (ret)
2489 return ret;
2490
2491 s = &dev->subdevices[2];
2492 /* digital I/O subdevice */
2493 s->type = COMEDI_SUBD_DIO;
2494 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2495 s->n_chan = 16;
2496 s->maxdata = 1;
2497 s->io_bits = 0xffff;
2498 s->private = (void *)0; /* DIO group 0 */
2499 s->range_table = &range_digital;
2500 s->insn_config = s626_dio_insn_config;
2501 s->insn_bits = s626_dio_insn_bits;
2502
2503 s = &dev->subdevices[3];
2504 /* digital I/O subdevice */
2505 s->type = COMEDI_SUBD_DIO;
2506 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2507 s->n_chan = 16;
2508 s->maxdata = 1;
2509 s->io_bits = 0xffff;
2510 s->private = (void *)1; /* DIO group 1 */
2511 s->range_table = &range_digital;
2512 s->insn_config = s626_dio_insn_config;
2513 s->insn_bits = s626_dio_insn_bits;
2514
2515 s = &dev->subdevices[4];
2516 /* digital I/O subdevice */
2517 s->type = COMEDI_SUBD_DIO;
2518 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2519 s->n_chan = 16;
2520 s->maxdata = 1;
2521 s->io_bits = 0xffff;
2522 s->private = (void *)2; /* DIO group 2 */
2523 s->range_table = &range_digital;
2524 s->insn_config = s626_dio_insn_config;
2525 s->insn_bits = s626_dio_insn_bits;
2526
2527 s = &dev->subdevices[5];
2528 /* encoder (counter) subdevice */
2529 s->type = COMEDI_SUBD_COUNTER;
2530 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2531 s->n_chan = S626_ENCODER_CHANNELS;
2532 s->maxdata = 0xffffff;
2533 s->range_table = &range_unknown;
2534 s->insn_config = s626_enc_insn_config;
2535 s->insn_read = s626_enc_insn_read;
2536 s->insn_write = s626_enc_insn_write;
2537
2538 return s626_initialize(dev);
2539 }
2540
2541 static void s626_detach(struct comedi_device *dev)
2542 {
2543 struct s626_private *devpriv = dev->private;
2544
2545 if (devpriv) {
2546 /* stop ai_command */
2547 devpriv->ai_cmd_running = 0;
2548
2549 if (dev->mmio) {
2550 /* interrupt mask */
2551 /* Disable master interrupt */
2552 writel(0, dev->mmio + S626_P_IER);
2553 /* Clear board's IRQ status flag */
2554 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2555 dev->mmio + S626_P_ISR);
2556
2557 /* Disable the watchdog timer and battery charger. */
2558 s626_write_misc2(dev, 0);
2559
2560 /* Close all interfaces on 7146 device */
2561 writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2562 writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2563 }
2564 }
2565 comedi_pci_detach(dev);
2566 s626_free_dma_buffers(dev);
2567 }
2568
2569 static struct comedi_driver s626_driver = {
2570 .driver_name = "s626",
2571 .module = THIS_MODULE,
2572 .auto_attach = s626_auto_attach,
2573 .detach = s626_detach,
2574 };
2575
2576 static int s626_pci_probe(struct pci_dev *dev,
2577 const struct pci_device_id *id)
2578 {
2579 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2580 }
2581
2582 /*
2583 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2584 * also subvendor:subdevice ids, because otherwise it will conflict with
2585 * Philips SAA7146 media/dvb based cards.
2586 */
2587 static const struct pci_device_id s626_pci_table[] = {
2588 { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2589 0x6000, 0x0272) },
2590 { 0 }
2591 };
2592 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2593
2594 static struct pci_driver s626_pci_driver = {
2595 .name = "s626",
2596 .id_table = s626_pci_table,
2597 .probe = s626_pci_probe,
2598 .remove = comedi_pci_auto_unconfig,
2599 };
2600 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2601
2602 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2603 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2604 MODULE_LICENSE("GPL");