root/drivers/staging/rtl8712/rtl871x_mp.c

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DEFINITIONS

This source file includes following definitions.
  1. _init_mp_priv_
  2. init_mp_priv
  3. free_mp_priv
  4. mp871xinit
  5. mp871xdeinit
  6. fw_iocmd_read
  7. fw_iocmd_write
  8. r8712_bb_reg_read
  9. r8712_bb_reg_write
  10. r8712_rf_reg_read
  11. r8712_rf_reg_write
  12. bitshift
  13. get_bb_reg
  14. set_bb_reg
  15. get_rf_reg
  16. set_rf_reg
  17. r8712_SetChannel
  18. SetCCKTxPower
  19. SetOFDMTxPower
  20. r8712_SetTxPower
  21. r8712_SetTxAGCOffset
  22. r8712_SetDataRate
  23. r8712_SwitchBandwidth
  24. r8712_SwitchAntenna
  25. TriggerRFThermalMeter
  26. ReadRFThermalMeter
  27. r8712_GetThermalMeter
  28. r8712_SetSingleCarrierTx
  29. r8712_SetSingleToneTx
  30. r8712_SetCarrierSuppressionTx
  31. SetCCKContinuousTx
  32. SetOFDMContinuousTx
  33. r8712_SetContinuousTx
  34. r8712_ResetPhyRxPktCount
  35. GetPhyRxPktCounts
  36. r8712_GetPhyRxPktReceived
  37. r8712_GetPhyRxPktCRC32Error
   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
   5  *
   6  * Modifications for inclusion into the Linux staging tree are
   7  * Copyright(c) 2010 Larry Finger. All rights reserved.
   8  *
   9  * Contact information:
  10  * WLAN FAE <wlanfae@realtek.com>
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  ******************************************************************************/
  14 #define _RTL871X_MP_C_
  15 
  16 #include "osdep_service.h"
  17 #include "drv_types.h"
  18 #include "rtl871x_mp_phy_regdef.h"
  19 #include "rtl8712_cmd.h"
  20 
  21 static void _init_mp_priv_(struct mp_priv *pmp_priv)
  22 {
  23         pmp_priv->mode = _LOOPBOOK_MODE_;
  24         pmp_priv->curr_ch = 1;
  25         pmp_priv->curr_modem = MIXED_PHY;
  26         pmp_priv->curr_rateidx = 0;
  27         pmp_priv->curr_txpoweridx = 0x14;
  28         pmp_priv->antenna_tx = ANTENNA_A;
  29         pmp_priv->antenna_rx = ANTENNA_AB;
  30         pmp_priv->check_mp_pkt = 0;
  31         pmp_priv->tx_pktcount = 0;
  32         pmp_priv->rx_pktcount = 0;
  33         pmp_priv->rx_crcerrpktcount = 0;
  34 }
  35 
  36 static int init_mp_priv(struct mp_priv *pmp_priv)
  37 {
  38         int i;
  39         struct mp_xmit_frame *pmp_xmitframe;
  40 
  41         _init_mp_priv_(pmp_priv);
  42         _init_queue(&pmp_priv->free_mp_xmitqueue);
  43         pmp_priv->pallocated_mp_xmitframe_buf = NULL;
  44         pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
  45                                 sizeof(struct mp_xmit_frame) + 4,
  46                                 GFP_ATOMIC);
  47         if (!pmp_priv->pallocated_mp_xmitframe_buf) {
  48                 return -ENOMEM;
  49         }
  50         pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
  51                          4 -
  52                          ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
  53         pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
  54         for (i = 0; i < NR_MP_XMITFRAME; i++) {
  55                 INIT_LIST_HEAD(&(pmp_xmitframe->list));
  56                 list_add_tail(&(pmp_xmitframe->list),
  57                                  &(pmp_priv->free_mp_xmitqueue.queue));
  58                 pmp_xmitframe->pkt = NULL;
  59                 pmp_xmitframe->frame_tag = MP_FRAMETAG;
  60                 pmp_xmitframe->padapter = pmp_priv->papdater;
  61                 pmp_xmitframe++;
  62         }
  63         pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
  64         return 0;
  65 }
  66 
  67 static int free_mp_priv(struct mp_priv *pmp_priv)
  68 {
  69         kfree(pmp_priv->pallocated_mp_xmitframe_buf);
  70         return 0;
  71 }
  72 
  73 void mp871xinit(struct _adapter *padapter)
  74 {
  75         struct mp_priv *pmppriv = &padapter->mppriv;
  76 
  77         pmppriv->papdater = padapter;
  78         init_mp_priv(pmppriv);
  79 }
  80 
  81 void mp871xdeinit(struct _adapter *padapter)
  82 {
  83         struct mp_priv *pmppriv = &padapter->mppriv;
  84 
  85         free_mp_priv(pmppriv);
  86 }
  87 
  88 /*
  89  * Special for bb and rf reg read/write
  90  */
  91 static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
  92 {
  93         u32 cmd32 = 0, val32 = 0;
  94         u8 iocmd_class  = iocmd.cmdclass;
  95         u16 iocmd_value = iocmd.value;
  96         u8 iocmd_idx    = iocmd.index;
  97 
  98         cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
  99         if (r8712_fw_cmd(pAdapter, cmd32))
 100                 r8712_fw_cmd_data(pAdapter, &val32, 1);
 101         else
 102                 val32 = 0;
 103         return val32;
 104 }
 105 
 106 static u8 fw_iocmd_write(struct _adapter *pAdapter,
 107                          struct IOCMD_STRUCT iocmd, u32 value)
 108 {
 109         u32 cmd32 = 0;
 110         u8 iocmd_class  = iocmd.cmdclass;
 111         u32 iocmd_value = iocmd.value;
 112         u8 iocmd_idx    = iocmd.index;
 113 
 114         r8712_fw_cmd_data(pAdapter, &value, 0);
 115         msleep(100);
 116         cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
 117         return r8712_fw_cmd(pAdapter, cmd32);
 118 }
 119 
 120 /* offset : 0X800~0XFFF */
 121 u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
 122 {
 123         u8 shift = offset & 0x0003;     /* 4 byte access */
 124         u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 125         u32 bb_val = 0;
 126         struct IOCMD_STRUCT iocmd;
 127 
 128         iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 129         iocmd.value     = bb_addr;
 130         iocmd.index     = IOCMD_BB_READ_IDX;
 131         bb_val = fw_iocmd_read(pAdapter, iocmd);
 132         if (shift != 0) {
 133                 u32 bb_val2 = 0;
 134 
 135                 bb_val >>= (shift * 8);
 136                 iocmd.value += 4;
 137                 bb_val2 = fw_iocmd_read(pAdapter, iocmd);
 138                 bb_val2 <<= ((4 - shift) * 8);
 139                 bb_val |= bb_val2;
 140         }
 141         return bb_val;
 142 }
 143 
 144 /* offset : 0X800~0XFFF */
 145 u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
 146 {
 147         u8 shift = offset & 0x0003;     /* 4 byte access */
 148         u16 bb_addr = offset & 0x0FFC;  /* 4 byte access */
 149         struct IOCMD_STRUCT iocmd;
 150 
 151         iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 152         iocmd.value     = bb_addr;
 153         iocmd.index     = IOCMD_BB_WRITE_IDX;
 154         if (shift != 0) {
 155                 u32 oldValue = 0;
 156                 u32 newValue = value;
 157 
 158                 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 159                 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
 160                 value = oldValue | (newValue << (shift * 8));
 161                 if (!fw_iocmd_write(pAdapter, iocmd, value))
 162                         return false;
 163                 iocmd.value += 4;
 164                 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
 165                 oldValue &= (0xFFFFFFFF << (shift * 8));
 166                 value = oldValue | (newValue >> ((4 - shift) * 8));
 167         }
 168         return fw_iocmd_write(pAdapter, iocmd, value);
 169 }
 170 
 171 /* offset : 0x00 ~ 0xFF */
 172 u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
 173 {
 174         u16 rf_addr = (path << 8) | offset;
 175         struct IOCMD_STRUCT iocmd;
 176 
 177         iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 178         iocmd.value     = rf_addr;
 179         iocmd.index     = IOCMD_RF_READ_IDX;
 180         return fw_iocmd_read(pAdapter, iocmd);
 181 }
 182 
 183 u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
 184 {
 185         u16 rf_addr = (path << 8) | offset;
 186         struct IOCMD_STRUCT iocmd;
 187 
 188         iocmd.cmdclass  = IOCMD_CLASS_BB_RF;
 189         iocmd.value     = rf_addr;
 190         iocmd.index     = IOCMD_RF_WRIT_IDX;
 191         return fw_iocmd_write(pAdapter, iocmd, value);
 192 }
 193 
 194 static u32 bitshift(u32 bitmask)
 195 {
 196         u32 i;
 197 
 198         for (i = 0; i <= 31; i++)
 199                 if (((bitmask >> i) &  0x1) == 1)
 200                         break;
 201         return i;
 202 }
 203 
 204 static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
 205 {
 206         u32 org_value, bit_shift;
 207 
 208         org_value = r8712_bb_reg_read(pAdapter, offset);
 209         bit_shift = bitshift(bitmask);
 210         return (org_value & bitmask) >> bit_shift;
 211 }
 212 
 213 static u8 set_bb_reg(struct _adapter *pAdapter,
 214                      u16 offset,
 215                      u32 bitmask,
 216                      u32 value)
 217 {
 218         u32 org_value, bit_shift, new_value;
 219 
 220         if (bitmask != bMaskDWord) {
 221                 org_value = r8712_bb_reg_read(pAdapter, offset);
 222                 bit_shift = bitshift(bitmask);
 223                 new_value = (org_value & (~bitmask)) | (value << bit_shift);
 224         } else {
 225                 new_value = value;
 226         }
 227         return r8712_bb_reg_write(pAdapter, offset, new_value);
 228 }
 229 
 230 static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
 231                       u32 bitmask)
 232 {
 233         u32 org_value, bit_shift;
 234 
 235         org_value = r8712_rf_reg_read(pAdapter, path, offset);
 236         bit_shift = bitshift(bitmask);
 237         return (org_value & bitmask) >> bit_shift;
 238 }
 239 
 240 static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
 241               u32 value)
 242 {
 243         u32 org_value, bit_shift, new_value;
 244 
 245         if (bitmask != bMaskDWord) {
 246                 org_value = r8712_rf_reg_read(pAdapter, path, offset);
 247                 bit_shift = bitshift(bitmask);
 248                 new_value = (org_value & (~bitmask)) | (value << bit_shift);
 249         } else {
 250                 new_value = value;
 251         }
 252         return r8712_rf_reg_write(pAdapter, path, offset, new_value);
 253 }
 254 
 255 /*
 256  * SetChannel
 257  * Description
 258  *      Use H2C command to change channel,
 259  *      not only modify rf register, but also other setting need to be done.
 260  */
 261 void r8712_SetChannel(struct _adapter *pAdapter)
 262 {
 263         struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
 264         struct cmd_obj *pcmd = NULL;
 265         struct SetChannel_parm *pparm = NULL;
 266         u16 code = GEN_CMD_CODE(_SetChannel);
 267 
 268         pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
 269         if (!pcmd)
 270                 return;
 271         pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
 272         if (!pparm) {
 273                 kfree(pcmd);
 274                 return;
 275         }
 276         pparm->curr_ch = pAdapter->mppriv.curr_ch;
 277         init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
 278         r8712_enqueue_cmd(pcmdpriv, pcmd);
 279 }
 280 
 281 static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
 282 {
 283         u16 TxAGC = 0;
 284 
 285         TxAGC = TxPower;
 286         set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 287 }
 288 
 289 static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
 290 {
 291         u32 TxAGC = 0;
 292 
 293         TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
 294                   TxPower);
 295         set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
 296         set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
 297         set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
 298         set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
 299         set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
 300         set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
 301 }
 302 
 303 void r8712_SetTxPower(struct _adapter *pAdapter)
 304 {
 305         u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
 306 
 307         SetCCKTxPower(pAdapter, TxPower);
 308         SetOFDMTxPower(pAdapter, TxPower);
 309 }
 310 
 311 void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
 312 {
 313         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
 314 
 315         TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
 316         TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
 317         TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
 318         tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
 319         set_bb_reg(pAdapter, rFPGA0_TxGainStage,
 320                         (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
 321 }
 322 
 323 void r8712_SetDataRate(struct _adapter *pAdapter)
 324 {
 325         u8 path = RF_PATH_A;
 326         u8 offset = RF_SYN_G2;
 327         u32 value;
 328 
 329         value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
 330         r8712_rf_reg_write(pAdapter, path, offset, value);
 331 }
 332 
 333 void r8712_SwitchBandwidth(struct _adapter *pAdapter)
 334 {
 335         /* 3 1.Set MAC register : BWOPMODE  bit2:1 20MhzBW */
 336         u8 regBwOpMode = 0;
 337         u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
 338 
 339         regBwOpMode = r8712_read8(pAdapter, 0x10250203);
 340         if (Bandwidth == HT_CHANNEL_WIDTH_20)
 341                 regBwOpMode |= BIT(2);
 342         else
 343                 regBwOpMode &= ~(BIT(2));
 344         r8712_write8(pAdapter, 0x10250203, regBwOpMode);
 345         /* 3 2.Set PHY related register */
 346         switch (Bandwidth) {
 347         /* 20 MHz channel*/
 348         case HT_CHANNEL_WIDTH_20:
 349                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 350                 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 351                 /* Use PHY_REG.txt default value. Do not need to change.
 352                  * Correct the tx power for CCK rate in 40M.
 353                  * It is set in Tx descriptor for 8192x series
 354                  */
 355                 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
 356                 break;
 357         /* 40 MHz channel*/
 358         case HT_CHANNEL_WIDTH_40:
 359                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 360                 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 361                 /* Use PHY_REG.txt default value. Do not need to change.
 362                  * Correct the tx power for CCK rate in 40M.
 363                  * Set Control channel to upper or lower. These settings are
 364                  * required only for 40MHz
 365                  */
 366                 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
 367                            (HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
 368                 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
 369                            HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 370                 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
 371                 break;
 372         default:
 373                 break;
 374         }
 375 
 376         /* 3 3.Set RF related register */
 377         switch (Bandwidth) {
 378         case HT_CHANNEL_WIDTH_20:
 379                 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 380                            BIT(10) | BIT(11), 0x01);
 381                 break;
 382         case HT_CHANNEL_WIDTH_40:
 383                 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
 384                            BIT(10) | BIT(11), 0x00);
 385                 break;
 386         default:
 387                 break;
 388         }
 389 }
 390 /*------------------------------Define structure----------------------------*/
 391 struct R_ANTENNA_SELECT_OFDM {
 392         u32     r_tx_antenna:4;
 393         u32     r_ant_l:4;
 394         u32     r_ant_non_ht:4;
 395         u32     r_ant_ht1:4;
 396         u32     r_ant_ht2:4;
 397         u32     r_ant_ht_s1:4;
 398         u32     r_ant_non_ht_s1:4;
 399         u32     OFDM_TXSC:2;
 400         u32     Reserved:2;
 401 };
 402 
 403 struct R_ANTENNA_SELECT_CCK {
 404         u8      r_cckrx_enable_2:2;
 405         u8      r_cckrx_enable:2;
 406         u8      r_ccktx_enable:4;
 407 };
 408 
 409 void r8712_SwitchAntenna(struct _adapter *pAdapter)
 410 {
 411         u32     ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
 412         u8      ofdm_rx_ant_sel_val = 0;
 413         u8      cck_ant_select_val = 0;
 414         u32     cck_ant_sel_val = 0;
 415         struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
 416 
 417         p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
 418 
 419         switch (pAdapter->mppriv.antenna_tx) {
 420         case ANTENNA_A:
 421                 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
 422                 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 423                 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 424                 ofdm_tx_en_val = 0x3;
 425                 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
 426                 p_cck_txrx->r_ccktx_enable = 0x8;
 427                 break;
 428         case ANTENNA_B:
 429                 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 430                 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 431                 ofdm_tx_en_val = 0x3;
 432                 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
 433                 p_cck_txrx->r_ccktx_enable = 0x4;
 434                 break;
 435         case ANTENNA_AB:        /* For 8192S */
 436                 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 437                 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 438                 ofdm_tx_en_val = 0x3;
 439                 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
 440                 p_cck_txrx->r_ccktx_enable = 0xC;
 441                 break;
 442         default:
 443                 break;
 444         }
 445         /*OFDM Tx*/
 446         set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
 447         /*OFDM Tx*/
 448         set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
 449         switch (pAdapter->mppriv.antenna_rx) {
 450         case ANTENNA_A:
 451                 ofdm_rx_ant_sel_val = 0x1;      /* A */
 452                 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
 453                 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
 454                 break;
 455         case ANTENNA_B:
 456                 ofdm_rx_ant_sel_val = 0x2;      /* B */
 457                 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
 458                 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
 459                 break;
 460         case ANTENNA_AB:
 461                 ofdm_rx_ant_sel_val = 0x3; /* AB */
 462                 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
 463                 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
 464                 break;
 465         default:
 466                 break;
 467         }
 468         /*OFDM Rx*/
 469         set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
 470                    ofdm_rx_ant_sel_val);
 471         /*OFDM Rx*/
 472         set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
 473                    ofdm_rx_ant_sel_val);
 474 
 475         cck_ant_sel_val = cck_ant_select_val;
 476         /*CCK TxRx*/
 477         set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
 478 }
 479 
 480 static void TriggerRFThermalMeter(struct _adapter *pAdapter)
 481 {
 482         /* 0x24: RF Reg[6:5] */
 483         set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
 484 }
 485 
 486 static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
 487 {
 488         /* 0x24: RF Reg[4:0] */
 489         return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
 490 }
 491 
 492 void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
 493 {
 494         TriggerRFThermalMeter(pAdapter);
 495         msleep(1000);
 496         *value = ReadRFThermalMeter(pAdapter);
 497 }
 498 
 499 void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
 500 {
 501         if (bStart) { /* Start Single Carrier. */
 502                 /* 1. if OFDM block on? */
 503                 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 504                         /*set OFDM block on*/
 505                         set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 506                 /* 2. set CCK test mode off, set to CCK normal mode */
 507                 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 508                 /* 3. turn on scramble setting */
 509                 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 510                 /* 4. Turn On Single Carrier Tx and off the other test modes. */
 511                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 512                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 513                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 514         } else { /* Stop Single Carrier.*/
 515                 /* Turn off all test modes.*/
 516                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 517                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 518                            bDisable);
 519                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 520                 msleep(20);
 521                 /*BB Reset*/
 522                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 523                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 524         }
 525 }
 526 
 527 void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
 528 {
 529         u8 rfPath;
 530 
 531         switch (pAdapter->mppriv.antenna_tx) {
 532         case ANTENNA_B:
 533                 rfPath = RF_PATH_B;
 534                 break;
 535         case ANTENNA_A:
 536         default:
 537                 rfPath = RF_PATH_A;
 538                 break;
 539         }
 540         if (bStart) { /* Start Single Tone.*/
 541                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
 542                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
 543                 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 544                            0xd4000);
 545                 msleep(100);
 546                 /* PAD all on.*/
 547                 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
 548                 msleep(100);
 549         } else { /* Stop Single Tone.*/
 550                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 551                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 552                 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
 553                            0x54000);
 554                 msleep(100);
 555                 /* PAD all on.*/
 556                 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
 557                 msleep(100);
 558         }
 559 }
 560 
 561 void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
 562 {
 563         if (bStart) { /* Start Carrier Suppression.*/
 564                 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 565                         /* 1. if CCK block on? */
 566                         if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 567                                 /*set CCK block on*/
 568                                 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
 569                                            bEnable);
 570                         }
 571                         /* Turn Off All Test Mode */
 572                         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
 573                                    bDisable);
 574                         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 575                                    bDisable);
 576                         set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
 577                                    bDisable);
 578                         /*transmit mode*/
 579                         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 580                         /*turn off scramble setting*/
 581                         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 582                                    bDisable);
 583                         /*Set CCK Tx Test Rate*/
 584                         /*Set FTxRate to 1Mbps*/
 585                         set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
 586                 }
 587         } else { /* Stop Carrier Suppression. */
 588                 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
 589                         /*normal mode*/
 590                         set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 591                         /*turn on scramble setting*/
 592                         set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
 593                                    bEnable);
 594                         /*BB Reset*/
 595                         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 596                         set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 597                 }
 598         }
 599 }
 600 
 601 static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
 602 {
 603         u32 cckrate;
 604 
 605         if (bStart) {
 606                 /* 1. if CCK block on? */
 607                 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
 608                         /*set CCK block on*/
 609                         set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
 610                 }
 611                 /* Turn Off All Test Mode */
 612                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 613                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 614                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 615                 /*Set CCK Tx Test Rate*/
 616                 cckrate  = pAdapter->mppriv.curr_rateidx;
 617                 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 618                 /*transmit mode*/
 619                 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
 620                 /*turn on scramble setting*/
 621                 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 622         } else {
 623                 /*normal mode*/
 624                 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
 625                 /*turn on scramble setting*/
 626                 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 627                 /*BB Reset*/
 628                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 629                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 630         }
 631 } /* mpt_StartCckContTx */
 632 
 633 static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
 634 {
 635         if (bStart) {
 636                 /* 1. if OFDM block on? */
 637                 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
 638                         /*set OFDM block on*/
 639                         set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
 640                 }
 641                 /* 2. set CCK test mode off, set to CCK normal mode*/
 642                 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 643                 /* 3. turn on scramble setting */
 644                 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 645                 /* 4. Turn On Continue Tx and turn off the other test modes.*/
 646                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 647                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 648                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 649         } else {
 650                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 651                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
 652                            bDisable);
 653                 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 654                 msleep(20);
 655                 /*BB Reset*/
 656                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 657                 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 658         }
 659 } /* mpt_StartOfdmContTx */
 660 
 661 void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
 662 {
 663         /* ADC turn off [bit24-21] adc port0 ~ port1 */
 664         if (bStart) {
 665                 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 666                                    r8712_bb_reg_read(pAdapter,
 667                                    rRx_Wait_CCCA) & 0xFE1FFFFF);
 668                 msleep(100);
 669         }
 670         if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
 671                 SetCCKContinuousTx(pAdapter, bStart);
 672         else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
 673                  (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
 674                 SetOFDMContinuousTx(pAdapter, bStart);
 675         /* ADC turn on [bit24-21] adc port0 ~ port1 */
 676         if (!bStart)
 677                 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
 678                                    r8712_bb_reg_read(pAdapter,
 679                                    rRx_Wait_CCCA) | 0x01E00000);
 680 }
 681 
 682 void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
 683 {
 684         u32 i, phyrx_set = 0;
 685 
 686         for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
 687                 phyrx_set = 0;
 688                 phyrx_set |= (i << 28);         /*select*/
 689                 phyrx_set |= 0x08000000;        /* set counter to zero*/
 690                 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 691         }
 692 }
 693 
 694 static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
 695 {
 696         /*selection*/
 697         u32 phyrx_set = 0;
 698         u32 SelectBit;
 699 
 700         SelectBit = selbit << 28;
 701         phyrx_set |= (SelectBit & 0xF0000000);
 702         r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
 703         /*Read packet count*/
 704         return r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
 705 }
 706 
 707 u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
 708 {
 709         u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
 710         u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
 711         u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
 712 
 713         return OFDM_cnt + CCK_cnt + HT_cnt;
 714 }
 715 
 716 u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
 717 {
 718         u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
 719         u32 CCK_cnt  = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
 720         u32 HT_cnt   = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
 721 
 722         return OFDM_cnt + CCK_cnt + HT_cnt;
 723 }
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