root/drivers/ata/pata_ns87415.c

DEFINITIONS

1. ns87415_set_mode
2. ns87415_set_piomode
3. ns87415_bmdma_setup
4. ns87415_bmdma_start
5. ns87415_bmdma_stop
6. ns87415_irq_clear
7. ns87415_check_atapi_dma
8. ns87560_read_buggy
9. ns87560_check_status
10. ns87560_tf_read
11. ns87560_bmdma_status
12. ns87415_fixup
13. ns87415_init_one
14. ns87415_reinit_one

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *    pata_ns87415.c - NS87415 (non PARISC) PATA
   4  *
   5  *      (C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
   6  *
   7  *    This is a fairly generic MWDMA controller. It has some limitations
   8  *    as it requires timing reloads on PIO/DMA transitions but it is otherwise
   9  *    fairly well designed.
  10  *
  11  *    This driver assumes the firmware has left the chip in a valid ST506
  12  *    compliant state, either legacy IRQ 14/15 or native INTA shared. You
  13  *    may need to add platform code if your system fails to do this.
  14  *
  15  *    The same cell appears in the 87560 controller used by some PARISC
  16  *    systems. This has its own special mountain of errata.
  17  *
  18  *    TODO:
  19  *      Test PARISC SuperIO
  20  *      Get someone to test on SPARC
  21  *      Implement lazy pio/dma switching for better performance
  22  *      8bit shared timing.
  23  *      See if we need to kill the FIFO for ATAPI
  24  */
  25 
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/blkdev.h>
  30 #include <linux/delay.h>
  31 #include <linux/device.h>
  32 #include <scsi/scsi_host.h>
  33 #include <linux/libata.h>
  34 #include <linux/ata.h>
  35 
  36 #define DRV_NAME        "pata_ns87415"
  37 #define DRV_VERSION     "0.0.1"
  38 
  39 /**
  40  *      ns87415_set_mode - Initialize host controller mode timings
  41  *      @ap: Port whose timings we are configuring
  42  *      @adev: Device whose timings we are configuring
  43  *      @mode: Mode to set
  44  *
  45  *      Program the mode registers for this controller, channel and
  46  *      device. Because the chip is quite an old design we have to do this
  47  *      for PIO/DMA switches.
  48  *
  49  *      LOCKING:
  50  *      None (inherited from caller).
  51  */
  52 
  53 static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
  54 {
  55         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
  56         int unit                = 2 * ap->port_no + adev->devno;
  57         int timing              = 0x44 + 2 * unit;
  58         unsigned long T         = 1000000000 / 33333;   /* PCI clocks */
  59         struct ata_timing t;
  60         u16 clocking;
  61         u8 iordy;
  62         u8 status;
  63 
  64         /* Timing register format is 17 - low nybble read timing with
  65            the high nybble being 16 - x for recovery time in PCI clocks */
  66 
  67         ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
  68 
  69         clocking = 17 - clamp_val(t.active, 2, 17);
  70         clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
  71         /* Use the same timing for read and write bytes */
  72         clocking |= (clocking << 8);
  73         pci_write_config_word(dev, timing, clocking);
  74 
  75         /* Set the IORDY enable versus DMA enable on or off properly */
  76         pci_read_config_byte(dev, 0x42, &iordy);
  77         iordy &= ~(1 << (4 + unit));
  78         if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev))
  79                 iordy |= (1 << (4 + unit));
  80 
  81         /* Paranoia: We shouldn't ever get here with busy write buffers
  82            but if so wait */
  83 
  84         pci_read_config_byte(dev, 0x43, &status);
  85         while (status & 0x03) {
  86                 udelay(1);
  87                 pci_read_config_byte(dev, 0x43, &status);
  88         }
  89         /* Flip the IORDY/DMA bits now we are sure the write buffers are
  90            clear */
  91         pci_write_config_byte(dev, 0x42, iordy);
  92 
  93         /* TODO: Set byte 54 command timing to the best 8bit
  94            mode shared by all four devices */
  95 }
  96 
  97 /**
  98  *      ns87415_set_piomode - Initialize host controller PATA PIO timings
  99  *      @ap: Port whose timings we are configuring
 100  *      @adev: Device to program
 101  *
 102  *      Set PIO mode for device, in host controller PCI config space.
 103  *
 104  *      LOCKING:
 105  *      None (inherited from caller).
 106  */
 107 
 108 static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
 109 {
 110         ns87415_set_mode(ap, adev, adev->pio_mode);
 111 }
 112 
 113 /**
 114  *      ns87415_bmdma_setup             -       Set up DMA
 115  *      @qc: Command block
 116  *
 117  *      Set up for bus masterng DMA. We have to do this ourselves
 118  *      rather than use the helper due to a chip erratum
 119  */
 120 
 121 static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
 122 {
 123         struct ata_port *ap = qc->ap;
 124         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 125         u8 dmactl;
 126 
 127         /* load PRD table addr. */
 128         mb();   /* make sure PRD table writes are visible to controller */
 129         iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
 130 
 131         /* specify data direction, triple-check start bit is clear */
 132         dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 133         dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 134         /* Due to an erratum we need to write these bits to the wrong
 135            place - which does save us an I/O bizarrely */
 136         dmactl |= ATA_DMA_INTR | ATA_DMA_ERR;
 137         if (!rw)
 138                 dmactl |= ATA_DMA_WR;
 139         iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 140         /* issue r/w command */
 141         ap->ops->sff_exec_command(ap, &qc->tf);
 142 }
 143 
 144 /**
 145  *      ns87415_bmdma_start             -       Begin DMA transfer
 146  *      @qc: Command block
 147  *
 148  *      Switch the timings for the chip and set up for a DMA transfer
 149  *      before the DMA burst begins.
 150  *
 151  *      FIXME: We should do lazy switching on bmdma_start versus
 152  *      ata_pio_data_xfer for better performance.
 153  */
 154 
 155 static void ns87415_bmdma_start(struct ata_queued_cmd *qc)
 156 {
 157         ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode);
 158         ata_bmdma_start(qc);
 159 }
 160 
 161 /**
 162  *      ns87415_bmdma_stop              -       End DMA transfer
 163  *      @qc: Command block
 164  *
 165  *      End DMA mode and switch the controller back into PIO mode
 166  */
 167 
 168 static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
 169 {
 170         ata_bmdma_stop(qc);
 171         ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode);
 172 }
 173 
 174 /**
 175  *      ns87415_irq_clear               -       Clear interrupt
 176  *      @ap: Channel to clear
 177  *
 178  *      Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the
 179  *      error bits) are reset by writing to register 00 or 08.
 180  */
 181 
 182 static void ns87415_irq_clear(struct ata_port *ap)
 183 {
 184         void __iomem *mmio = ap->ioaddr.bmdma_addr;
 185 
 186         if (!mmio)
 187                 return;
 188         iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR),
 189                         mmio + ATA_DMA_CMD);
 190 }
 191 
 192 /**
 193  *      ns87415_check_atapi_dma         -       ATAPI DMA filter
 194  *      @qc: Command block
 195  *
 196  *      Disable ATAPI DMA (for now). We may be able to do DMA if we
 197  *      kill the prefetching. This isn't clear.
 198  */
 199 
 200 static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc)
 201 {
 202         return -EOPNOTSUPP;
 203 }
 204 
 205 #if defined(CONFIG_SUPERIO)
 206 
 207 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 208  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 209  * which use the integrated NS87514 cell for CD-ROM support.
 210  * i.e we have to support for CD-ROM installs.
 211  * See drivers/parisc/superio.c for more gory details.
 212  *
 213  * Workarounds taken from drivers/ide/pci/ns87415.c
 214  */
 215 
 216 #include <asm/superio.h>
 217 
 218 #define SUPERIO_IDE_MAX_RETRIES 25
 219 
 220 /**
 221  *      ns87560_read_buggy      -       workaround buggy Super I/O chip
 222  *      @port: Port to read
 223  *
 224  *      Work around chipset problems in the 87560 SuperIO chip
 225  */
 226 
 227 static u8 ns87560_read_buggy(void __iomem *port)
 228 {
 229         u8 tmp;
 230         int retries = SUPERIO_IDE_MAX_RETRIES;
 231         do {
 232                 tmp = ioread8(port);
 233                 if (tmp != 0)
 234                         return tmp;
 235                 udelay(50);
 236         } while(retries-- > 0);
 237         return tmp;
 238 }
 239 
 240 /**
 241  *      ns87560_check_status
 242  *      @ap: channel to check
 243  *
 244  *      Return the status of the channel working around the
 245  *      87560 flaws.
 246  */
 247 
 248 static u8 ns87560_check_status(struct ata_port *ap)
 249 {
 250         return ns87560_read_buggy(ap->ioaddr.status_addr);
 251 }
 252 
 253 /**
 254  *      ns87560_tf_read - input device's ATA taskfile shadow registers
 255  *      @ap: Port from which input is read
 256  *      @tf: ATA taskfile register set for storing input
 257  *
 258  *      Reads ATA taskfile registers for currently-selected device
 259  *      into @tf. Work around the 87560 bugs.
 260  *
 261  *      LOCKING:
 262  *      Inherited from caller.
 263  */
 264 void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 265 {
 266         struct ata_ioports *ioaddr = &ap->ioaddr;
 267 
 268         tf->command = ns87560_check_status(ap);
 269         tf->feature = ioread8(ioaddr->error_addr);
 270         tf->nsect = ioread8(ioaddr->nsect_addr);
 271         tf->lbal = ioread8(ioaddr->lbal_addr);
 272         tf->lbam = ioread8(ioaddr->lbam_addr);
 273         tf->lbah = ioread8(ioaddr->lbah_addr);
 274         tf->device = ns87560_read_buggy(ioaddr->device_addr);
 275 
 276         if (tf->flags & ATA_TFLAG_LBA48) {
 277                 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
 278                 tf->hob_feature = ioread8(ioaddr->error_addr);
 279                 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
 280                 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
 281                 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
 282                 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
 283                 iowrite8(tf->ctl, ioaddr->ctl_addr);
 284                 ap->last_ctl = tf->ctl;
 285         }
 286 }
 287 
 288 /**
 289  *      ns87560_bmdma_status
 290  *      @ap: channel to check
 291  *
 292  *      Return the DMA status of the channel working around the
 293  *      87560 flaws.
 294  */
 295 
 296 static u8 ns87560_bmdma_status(struct ata_port *ap)
 297 {
 298         return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
 299 }
 300 #endif          /* 87560 SuperIO Support */
 301 
 302 static struct ata_port_operations ns87415_pata_ops = {
 303         .inherits               = &ata_bmdma_port_ops,
 304 
 305         .check_atapi_dma        = ns87415_check_atapi_dma,
 306         .bmdma_setup            = ns87415_bmdma_setup,
 307         .bmdma_start            = ns87415_bmdma_start,
 308         .bmdma_stop             = ns87415_bmdma_stop,
 309         .sff_irq_clear          = ns87415_irq_clear,
 310 
 311         .cable_detect           = ata_cable_40wire,
 312         .set_piomode            = ns87415_set_piomode,
 313 };
 314 
 315 #if defined(CONFIG_SUPERIO)
 316 static struct ata_port_operations ns87560_pata_ops = {
 317         .inherits               = &ns87415_pata_ops,
 318         .sff_tf_read            = ns87560_tf_read,
 319         .sff_check_status       = ns87560_check_status,
 320         .bmdma_status           = ns87560_bmdma_status,
 321 };
 322 #endif
 323 
 324 static struct scsi_host_template ns87415_sht = {
 325         ATA_BMDMA_SHT(DRV_NAME),
 326 };
 327 
 328 static void ns87415_fixup(struct pci_dev *pdev)
 329 {
 330         /* Select 512 byte sectors */
 331         pci_write_config_byte(pdev, 0x55, 0xEE);
 332         /* Select PIO0 8bit clocking */
 333         pci_write_config_byte(pdev, 0x54, 0xB7);
 334 }
 335 
 336 /**
 337  *      ns87415_init_one - Register 87415 ATA PCI device with kernel services
 338  *      @pdev: PCI device to register
 339  *      @ent: Entry in ns87415_pci_tbl matching with @pdev
 340  *
 341  *      Called from kernel PCI layer.  We probe for combined mode (sigh),
 342  *      and then hand over control to libata, for it to do the rest.
 343  *
 344  *      LOCKING:
 345  *      Inherited from PCI layer (may sleep).
 346  *
 347  *      RETURNS:
 348  *      Zero on success, or -ERRNO value.
 349  */
 350 
 351 static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 352 {
 353         static const struct ata_port_info info = {
 354                 .flags          = ATA_FLAG_SLAVE_POSS,
 355                 .pio_mask       = ATA_PIO4,
 356                 .mwdma_mask     = ATA_MWDMA2,
 357                 .port_ops       = &ns87415_pata_ops,
 358         };
 359         const struct ata_port_info *ppi[] = { &info, NULL };
 360         int rc;
 361 #if defined(CONFIG_SUPERIO)
 362         static const struct ata_port_info info87560 = {
 363                 .flags          = ATA_FLAG_SLAVE_POSS,
 364                 .pio_mask       = ATA_PIO4,
 365                 .mwdma_mask     = ATA_MWDMA2,
 366                 .port_ops       = &ns87560_pata_ops,
 367         };
 368 
 369         if (PCI_SLOT(pdev->devfn) == 0x0E)
 370                 ppi[0] = &info87560;
 371 #endif
 372         ata_print_version_once(&pdev->dev, DRV_VERSION);
 373 
 374         rc = pcim_enable_device(pdev);
 375         if (rc)
 376                 return rc;
 377 
 378         ns87415_fixup(pdev);
 379 
 380         return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
 381 }
 382 
 383 static const struct pci_device_id ns87415_pci_tbl[] = {
 384         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), },
 385 
 386         { }     /* terminate list */
 387 };
 388 
 389 #ifdef CONFIG_PM_SLEEP
 390 static int ns87415_reinit_one(struct pci_dev *pdev)
 391 {
 392         struct ata_host *host = pci_get_drvdata(pdev);
 393         int rc;
 394 
 395         rc = ata_pci_device_do_resume(pdev);
 396         if (rc)
 397                 return rc;
 398 
 399         ns87415_fixup(pdev);
 400 
 401         ata_host_resume(host);
 402         return 0;
 403 }
 404 #endif
 405 
 406 static struct pci_driver ns87415_pci_driver = {
 407         .name                   = DRV_NAME,
 408         .id_table               = ns87415_pci_tbl,
 409         .probe                  = ns87415_init_one,
 410         .remove                 = ata_pci_remove_one,
 411 #ifdef CONFIG_PM_SLEEP
 412         .suspend                = ata_pci_device_suspend,
 413         .resume                 = ns87415_reinit_one,
 414 #endif
 415 };
 416 
 417 module_pci_driver(ns87415_pci_driver);
 418 
 419 MODULE_AUTHOR("Alan Cox");
 420 MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
 421 MODULE_LICENSE("GPL");
 422 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
 423 MODULE_VERSION(DRV_VERSION);