This source file includes following definitions.
- hisi_spi_nor_wait_op_finish
- hisi_spi_nor_get_if_type
- hisi_spi_nor_init
- hisi_spi_nor_prep
- hisi_spi_nor_unprep
- hisi_spi_nor_op_reg
- hisi_spi_nor_read_reg
- hisi_spi_nor_write_reg
- hisi_spi_nor_dma_transfer
- hisi_spi_nor_read
- hisi_spi_nor_write
- hisi_spi_nor_register
- hisi_spi_nor_unregister_all
- hisi_spi_nor_register_all
- hisi_spi_nor_probe
- hisi_spi_nor_remove
1
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5
6
7 #include <linux/bitops.h>
8 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/spi-nor.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17
18
19 #define FMC_CFG 0x00
20 #define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
21 #define FMC_CFG_OP_MODE_BOOT 0
22 #define FMC_CFG_OP_MODE_NORMAL 1
23 #define FMC_CFG_FLASH_SEL(type) (((type) & 0x3) << 1)
24 #define FMC_CFG_FLASH_SEL_MASK 0x6
25 #define FMC_ECC_TYPE(type) (((type) & 0x7) << 5)
26 #define FMC_ECC_TYPE_MASK GENMASK(7, 5)
27 #define SPI_NOR_ADDR_MODE_MASK BIT_MASK(10)
28 #define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10)
29 #define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10)
30 #define FMC_GLOBAL_CFG 0x04
31 #define FMC_GLOBAL_CFG_WP_ENABLE BIT(6)
32 #define FMC_SPI_TIMING_CFG 0x08
33 #define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8)
34 #define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4)
35 #define TIMING_CFG_TSHSL(nr) ((nr) & 0xf)
36 #define CS_HOLD_TIME 0x6
37 #define CS_SETUP_TIME 0x6
38 #define CS_DESELECT_TIME 0xf
39 #define FMC_INT 0x18
40 #define FMC_INT_OP_DONE BIT(0)
41 #define FMC_INT_CLR 0x20
42 #define FMC_CMD 0x24
43 #define FMC_CMD_CMD1(cmd) ((cmd) & 0xff)
44 #define FMC_ADDRL 0x2c
45 #define FMC_OP_CFG 0x30
46 #define OP_CFG_FM_CS(cs) ((cs) << 11)
47 #define OP_CFG_MEM_IF_TYPE(type) (((type) & 0x7) << 7)
48 #define OP_CFG_ADDR_NUM(addr) (((addr) & 0x7) << 4)
49 #define OP_CFG_DUMMY_NUM(dummy) ((dummy) & 0xf)
50 #define FMC_DATA_NUM 0x38
51 #define FMC_DATA_NUM_CNT(cnt) ((cnt) & GENMASK(13, 0))
52 #define FMC_OP 0x3c
53 #define FMC_OP_DUMMY_EN BIT(8)
54 #define FMC_OP_CMD1_EN BIT(7)
55 #define FMC_OP_ADDR_EN BIT(6)
56 #define FMC_OP_WRITE_DATA_EN BIT(5)
57 #define FMC_OP_READ_DATA_EN BIT(2)
58 #define FMC_OP_READ_STATUS_EN BIT(1)
59 #define FMC_OP_REG_OP_START BIT(0)
60 #define FMC_DMA_LEN 0x40
61 #define FMC_DMA_LEN_SET(len) ((len) & GENMASK(27, 0))
62 #define FMC_DMA_SADDR_D0 0x4c
63 #define HIFMC_DMA_MAX_LEN (4096)
64 #define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
65 #define FMC_OP_DMA 0x68
66 #define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16)
67 #define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8)
68 #define OP_CTRL_RW_OP(op) ((op) << 1)
69 #define OP_CTRL_DMA_OP_READY BIT(0)
70 #define FMC_OP_READ 0x0
71 #define FMC_OP_WRITE 0x1
72 #define FMC_WAIT_TIMEOUT 1000000
73
74 enum hifmc_iftype {
75 IF_TYPE_STD,
76 IF_TYPE_DUAL,
77 IF_TYPE_DIO,
78 IF_TYPE_QUAD,
79 IF_TYPE_QIO,
80 };
81
82 struct hifmc_priv {
83 u32 chipselect;
84 u32 clkrate;
85 struct hifmc_host *host;
86 };
87
88 #define HIFMC_MAX_CHIP_NUM 2
89 struct hifmc_host {
90 struct device *dev;
91 struct mutex lock;
92
93 void __iomem *regbase;
94 void __iomem *iobase;
95 struct clk *clk;
96 void *buffer;
97 dma_addr_t dma_buffer;
98
99 struct spi_nor *nor[HIFMC_MAX_CHIP_NUM];
100 u32 num_chip;
101 };
102
103 static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
104 {
105 u32 reg;
106
107 return readl_poll_timeout(host->regbase + FMC_INT, reg,
108 (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
109 }
110
111 static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
112 {
113 enum hifmc_iftype if_type;
114
115 switch (proto) {
116 case SNOR_PROTO_1_1_2:
117 if_type = IF_TYPE_DUAL;
118 break;
119 case SNOR_PROTO_1_2_2:
120 if_type = IF_TYPE_DIO;
121 break;
122 case SNOR_PROTO_1_1_4:
123 if_type = IF_TYPE_QUAD;
124 break;
125 case SNOR_PROTO_1_4_4:
126 if_type = IF_TYPE_QIO;
127 break;
128 case SNOR_PROTO_1_1_1:
129 default:
130 if_type = IF_TYPE_STD;
131 break;
132 }
133
134 return if_type;
135 }
136
137 static void hisi_spi_nor_init(struct hifmc_host *host)
138 {
139 u32 reg;
140
141 reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
142 | TIMING_CFG_TCSS(CS_SETUP_TIME)
143 | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
145 }
146
147 static int hisi_spi_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops)
148 {
149 struct hifmc_priv *priv = nor->priv;
150 struct hifmc_host *host = priv->host;
151 int ret;
152
153 mutex_lock(&host->lock);
154
155 ret = clk_set_rate(host->clk, priv->clkrate);
156 if (ret)
157 goto out;
158
159 ret = clk_prepare_enable(host->clk);
160 if (ret)
161 goto out;
162
163 return 0;
164
165 out:
166 mutex_unlock(&host->lock);
167 return ret;
168 }
169
170 static void hisi_spi_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
171 {
172 struct hifmc_priv *priv = nor->priv;
173 struct hifmc_host *host = priv->host;
174
175 clk_disable_unprepare(host->clk);
176 mutex_unlock(&host->lock);
177 }
178
179 static int hisi_spi_nor_op_reg(struct spi_nor *nor,
180 u8 opcode, int len, u8 optype)
181 {
182 struct hifmc_priv *priv = nor->priv;
183 struct hifmc_host *host = priv->host;
184 u32 reg;
185
186 reg = FMC_CMD_CMD1(opcode);
187 writel(reg, host->regbase + FMC_CMD);
188
189 reg = FMC_DATA_NUM_CNT(len);
190 writel(reg, host->regbase + FMC_DATA_NUM);
191
192 reg = OP_CFG_FM_CS(priv->chipselect);
193 writel(reg, host->regbase + FMC_OP_CFG);
194
195 writel(0xff, host->regbase + FMC_INT_CLR);
196 reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
197 writel(reg, host->regbase + FMC_OP);
198
199 return hisi_spi_nor_wait_op_finish(host);
200 }
201
202 static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
203 int len)
204 {
205 struct hifmc_priv *priv = nor->priv;
206 struct hifmc_host *host = priv->host;
207 int ret;
208
209 ret = hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN);
210 if (ret)
211 return ret;
212
213 memcpy_fromio(buf, host->iobase, len);
214 return 0;
215 }
216
217 static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
218 u8 *buf, int len)
219 {
220 struct hifmc_priv *priv = nor->priv;
221 struct hifmc_host *host = priv->host;
222
223 if (len)
224 memcpy_toio(host->iobase, buf, len);
225
226 return hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN);
227 }
228
229 static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
230 dma_addr_t dma_buf, size_t len, u8 op_type)
231 {
232 struct hifmc_priv *priv = nor->priv;
233 struct hifmc_host *host = priv->host;
234 u8 if_type = 0;
235 u32 reg;
236
237 reg = readl(host->regbase + FMC_CFG);
238 reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
239 reg |= FMC_CFG_OP_MODE_NORMAL;
240 reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES
241 : SPI_NOR_ADDR_MODE_3BYTES;
242 writel(reg, host->regbase + FMC_CFG);
243
244 writel(start_off, host->regbase + FMC_ADDRL);
245 writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
246 writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
247
248 reg = OP_CFG_FM_CS(priv->chipselect);
249 if (op_type == FMC_OP_READ)
250 if_type = hisi_spi_nor_get_if_type(nor->read_proto);
251 else
252 if_type = hisi_spi_nor_get_if_type(nor->write_proto);
253 reg |= OP_CFG_MEM_IF_TYPE(if_type);
254 if (op_type == FMC_OP_READ)
255 reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
256 writel(reg, host->regbase + FMC_OP_CFG);
257
258 writel(0xff, host->regbase + FMC_INT_CLR);
259 reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
260 reg |= (op_type == FMC_OP_READ)
261 ? OP_CTRL_RD_OPCODE(nor->read_opcode)
262 : OP_CTRL_WR_OPCODE(nor->program_opcode);
263 writel(reg, host->regbase + FMC_OP_DMA);
264
265 return hisi_spi_nor_wait_op_finish(host);
266 }
267
268 static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
269 u_char *read_buf)
270 {
271 struct hifmc_priv *priv = nor->priv;
272 struct hifmc_host *host = priv->host;
273 size_t offset;
274 int ret;
275
276 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
277 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
278
279 ret = hisi_spi_nor_dma_transfer(nor,
280 from + offset, host->dma_buffer, trans, FMC_OP_READ);
281 if (ret) {
282 dev_warn(nor->dev, "DMA read timeout\n");
283 return ret;
284 }
285 memcpy(read_buf + offset, host->buffer, trans);
286 }
287
288 return len;
289 }
290
291 static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
292 size_t len, const u_char *write_buf)
293 {
294 struct hifmc_priv *priv = nor->priv;
295 struct hifmc_host *host = priv->host;
296 size_t offset;
297 int ret;
298
299 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
300 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
301
302 memcpy(host->buffer, write_buf + offset, trans);
303 ret = hisi_spi_nor_dma_transfer(nor,
304 to + offset, host->dma_buffer, trans, FMC_OP_WRITE);
305 if (ret) {
306 dev_warn(nor->dev, "DMA write timeout\n");
307 return ret;
308 }
309 }
310
311 return len;
312 }
313
314
315
316
317 static int hisi_spi_nor_register(struct device_node *np,
318 struct hifmc_host *host)
319 {
320 const struct spi_nor_hwcaps hwcaps = {
321 .mask = SNOR_HWCAPS_READ |
322 SNOR_HWCAPS_READ_FAST |
323 SNOR_HWCAPS_READ_1_1_2 |
324 SNOR_HWCAPS_READ_1_1_4 |
325 SNOR_HWCAPS_PP,
326 };
327 struct device *dev = host->dev;
328 struct spi_nor *nor;
329 struct hifmc_priv *priv;
330 struct mtd_info *mtd;
331 int ret;
332
333 nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
334 if (!nor)
335 return -ENOMEM;
336
337 nor->dev = dev;
338 spi_nor_set_flash_node(nor, np);
339
340 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
341 if (!priv)
342 return -ENOMEM;
343
344 ret = of_property_read_u32(np, "reg", &priv->chipselect);
345 if (ret) {
346 dev_err(dev, "There's no reg property for %pOF\n",
347 np);
348 return ret;
349 }
350
351 ret = of_property_read_u32(np, "spi-max-frequency",
352 &priv->clkrate);
353 if (ret) {
354 dev_err(dev, "There's no spi-max-frequency property for %pOF\n",
355 np);
356 return ret;
357 }
358 priv->host = host;
359 nor->priv = priv;
360
361 nor->prepare = hisi_spi_nor_prep;
362 nor->unprepare = hisi_spi_nor_unprep;
363 nor->read_reg = hisi_spi_nor_read_reg;
364 nor->write_reg = hisi_spi_nor_write_reg;
365 nor->read = hisi_spi_nor_read;
366 nor->write = hisi_spi_nor_write;
367 nor->erase = NULL;
368 ret = spi_nor_scan(nor, NULL, &hwcaps);
369 if (ret)
370 return ret;
371
372 mtd = &nor->mtd;
373 mtd->name = np->name;
374 ret = mtd_device_register(mtd, NULL, 0);
375 if (ret)
376 return ret;
377
378 host->nor[host->num_chip] = nor;
379 host->num_chip++;
380 return 0;
381 }
382
383 static void hisi_spi_nor_unregister_all(struct hifmc_host *host)
384 {
385 int i;
386
387 for (i = 0; i < host->num_chip; i++)
388 mtd_device_unregister(&host->nor[i]->mtd);
389 }
390
391 static int hisi_spi_nor_register_all(struct hifmc_host *host)
392 {
393 struct device *dev = host->dev;
394 struct device_node *np;
395 int ret;
396
397 for_each_available_child_of_node(dev->of_node, np) {
398 ret = hisi_spi_nor_register(np, host);
399 if (ret)
400 goto fail;
401
402 if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
403 dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n");
404 of_node_put(np);
405 break;
406 }
407 }
408
409 return 0;
410
411 fail:
412 hisi_spi_nor_unregister_all(host);
413 return ret;
414 }
415
416 static int hisi_spi_nor_probe(struct platform_device *pdev)
417 {
418 struct device *dev = &pdev->dev;
419 struct resource *res;
420 struct hifmc_host *host;
421 int ret;
422
423 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
424 if (!host)
425 return -ENOMEM;
426
427 platform_set_drvdata(pdev, host);
428 host->dev = dev;
429
430 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
431 host->regbase = devm_ioremap_resource(dev, res);
432 if (IS_ERR(host->regbase))
433 return PTR_ERR(host->regbase);
434
435 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
436 host->iobase = devm_ioremap_resource(dev, res);
437 if (IS_ERR(host->iobase))
438 return PTR_ERR(host->iobase);
439
440 host->clk = devm_clk_get(dev, NULL);
441 if (IS_ERR(host->clk))
442 return PTR_ERR(host->clk);
443
444 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
445 if (ret) {
446 dev_warn(dev, "Unable to set dma mask\n");
447 return ret;
448 }
449
450 host->buffer = dmam_alloc_coherent(dev, HIFMC_DMA_MAX_LEN,
451 &host->dma_buffer, GFP_KERNEL);
452 if (!host->buffer)
453 return -ENOMEM;
454
455 ret = clk_prepare_enable(host->clk);
456 if (ret)
457 return ret;
458
459 mutex_init(&host->lock);
460 hisi_spi_nor_init(host);
461 ret = hisi_spi_nor_register_all(host);
462 if (ret)
463 mutex_destroy(&host->lock);
464
465 clk_disable_unprepare(host->clk);
466 return ret;
467 }
468
469 static int hisi_spi_nor_remove(struct platform_device *pdev)
470 {
471 struct hifmc_host *host = platform_get_drvdata(pdev);
472
473 hisi_spi_nor_unregister_all(host);
474 mutex_destroy(&host->lock);
475 clk_disable_unprepare(host->clk);
476 return 0;
477 }
478
479 static const struct of_device_id hisi_spi_nor_dt_ids[] = {
480 { .compatible = "hisilicon,fmc-spi-nor"},
481 { }
482 };
483 MODULE_DEVICE_TABLE(of, hisi_spi_nor_dt_ids);
484
485 static struct platform_driver hisi_spi_nor_driver = {
486 .driver = {
487 .name = "hisi-sfc",
488 .of_match_table = hisi_spi_nor_dt_ids,
489 },
490 .probe = hisi_spi_nor_probe,
491 .remove = hisi_spi_nor_remove,
492 };
493 module_platform_driver(hisi_spi_nor_driver);
494
495 MODULE_LICENSE("GPL v2");
496 MODULE_DESCRIPTION("HiSilicon SPI Nor Flash Controller Driver");