drivers/mtd/nand/raw/gpio.c

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This source file includes following definitions.
gpio_nand_getpriv
gpio_nand_dosync
gpio_nand_dosync
gpio_nand_cmd_ctrl
gpio_nand_devready
gpio_nand_get_config_of
gpio_nand_get_io_sync_of
gpio_nand_get_config_of
gpio_nand_get_io_sync_of
gpio_nand_get_config
gpio_nand_get_io_sync
gpio_nand_remove
gpio_nand_probe
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Updated, and converted to generic GPIO based driver by Russell King.
   4  *
   5  * Written by Ben Dooks <ben@simtec.co.uk>
   6  *   Based on 2.4 version by Mark Whittaker
   7  *
   8  * © 2004 Simtec Electronics
   9  *
  10  * Device driver for NAND flash that uses a memory mapped interface to
  11  * read/write the NAND commands and data, and GPIO pins for control signals
  12  * (the DT binding refers to this as "GPIO assisted NAND flash")
  13  */
  14 
  15 #include <linux/kernel.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/io.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/rawnand.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/mtd/nand-gpio.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 
  29 struct gpiomtd {
  30         void __iomem            *io_sync;
  31         struct nand_chip        nand_chip;
  32         struct gpio_nand_platdata plat;
  33         struct gpio_desc *nce; /* Optional chip enable */
  34         struct gpio_desc *cle;
  35         struct gpio_desc *ale;
  36         struct gpio_desc *rdy;
  37         struct gpio_desc *nwp; /* Optional write protection */
  38 };
  39 
  40 static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd)
  41 {
  42         return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
  43 }
  44 
  45 
  46 #ifdef CONFIG_ARM
  47 /* gpio_nand_dosync()
  48  *
  49  * Make sure the GPIO state changes occur in-order with writes to NAND
  50  * memory region.
  51  * Needed on PXA due to bus-reordering within the SoC itself (see section on
  52  * I/O ordering in PXA manual (section 2.3, p35)
  53  */
  54 static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
  55 {
  56         unsigned long tmp;
  57 
  58         if (gpiomtd->io_sync) {
  59                 /*
  60                  * Linux memory barriers don't cater for what's required here.
  61                  * What's required is what's here - a read from a separate
  62                  * region with a dependency on that read.
  63                  */
  64                 tmp = readl(gpiomtd->io_sync);
  65                 asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
  66         }
  67 }
  68 #else
  69 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
  70 #endif
  71 
  72 static void gpio_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
  73                                unsigned int ctrl)
  74 {
  75         struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
  76 
  77         gpio_nand_dosync(gpiomtd);
  78 
  79         if (ctrl & NAND_CTRL_CHANGE) {
  80                 if (gpiomtd->nce)
  81                         gpiod_set_value(gpiomtd->nce, !(ctrl & NAND_NCE));
  82                 gpiod_set_value(gpiomtd->cle, !!(ctrl & NAND_CLE));
  83                 gpiod_set_value(gpiomtd->ale, !!(ctrl & NAND_ALE));
  84                 gpio_nand_dosync(gpiomtd);
  85         }
  86         if (cmd == NAND_CMD_NONE)
  87                 return;
  88 
  89         writeb(cmd, gpiomtd->nand_chip.legacy.IO_ADDR_W);
  90         gpio_nand_dosync(gpiomtd);
  91 }
  92 
  93 static int gpio_nand_devready(struct nand_chip *chip)
  94 {
  95         struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
  96 
  97         return gpiod_get_value(gpiomtd->rdy);
  98 }
  99 
 100 #ifdef CONFIG_OF
 101 static const struct of_device_id gpio_nand_id_table[] = {
 102         { .compatible = "gpio-control-nand" },
 103         {}
 104 };
 105 MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
 106 
 107 static int gpio_nand_get_config_of(const struct device *dev,
 108                                    struct gpio_nand_platdata *plat)
 109 {
 110         u32 val;
 111 
 112         if (!dev->of_node)
 113                 return -ENODEV;
 114 
 115         if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
 116                 if (val == 2) {
 117                         plat->options |= NAND_BUSWIDTH_16;
 118                 } else if (val != 1) {
 119                         dev_err(dev, "invalid bank-width %u\n", val);
 120                         return -EINVAL;
 121                 }
 122         }
 123 
 124         if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
 125                 plat->chip_delay = val;
 126 
 127         return 0;
 128 }
 129 
 130 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
 131 {
 132         struct resource *r;
 133         u64 addr;
 134 
 135         if (of_property_read_u64(pdev->dev.of_node,
 136                                        "gpio-control-nand,io-sync-reg", &addr))
 137                 return NULL;
 138 
 139         r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
 140         if (!r)
 141                 return NULL;
 142 
 143         r->start = addr;
 144         r->end = r->start + 0x3;
 145         r->flags = IORESOURCE_MEM;
 146 
 147         return r;
 148 }
 149 #else /* CONFIG_OF */
 150 static inline int gpio_nand_get_config_of(const struct device *dev,
 151                                           struct gpio_nand_platdata *plat)
 152 {
 153         return -ENOSYS;
 154 }
 155 
 156 static inline struct resource *
 157 gpio_nand_get_io_sync_of(struct platform_device *pdev)
 158 {
 159         return NULL;
 160 }
 161 #endif /* CONFIG_OF */
 162 
 163 static inline int gpio_nand_get_config(const struct device *dev,
 164                                        struct gpio_nand_platdata *plat)
 165 {
 166         int ret = gpio_nand_get_config_of(dev, plat);
 167 
 168         if (!ret)
 169                 return ret;
 170 
 171         if (dev_get_platdata(dev)) {
 172                 memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
 173                 return 0;
 174         }
 175 
 176         return -EINVAL;
 177 }
 178 
 179 static inline struct resource *
 180 gpio_nand_get_io_sync(struct platform_device *pdev)
 181 {
 182         struct resource *r = gpio_nand_get_io_sync_of(pdev);
 183 
 184         if (r)
 185                 return r;
 186 
 187         return platform_get_resource(pdev, IORESOURCE_MEM, 1);
 188 }
 189 
 190 static int gpio_nand_remove(struct platform_device *pdev)
 191 {
 192         struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
 193 
 194         nand_release(&gpiomtd->nand_chip);
 195 
 196         /* Enable write protection and disable the chip */
 197         if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
 198                 gpiod_set_value(gpiomtd->nwp, 0);
 199         if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
 200                 gpiod_set_value(gpiomtd->nce, 0);
 201 
 202         return 0;
 203 }
 204 
 205 static int gpio_nand_probe(struct platform_device *pdev)
 206 {
 207         struct gpiomtd *gpiomtd;
 208         struct nand_chip *chip;
 209         struct mtd_info *mtd;
 210         struct resource *res;
 211         struct device *dev = &pdev->dev;
 212         int ret = 0;
 213 
 214         if (!dev->of_node && !dev_get_platdata(dev))
 215                 return -EINVAL;
 216 
 217         gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
 218         if (!gpiomtd)
 219                 return -ENOMEM;
 220 
 221         chip = &gpiomtd->nand_chip;
 222 
 223         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 224         chip->legacy.IO_ADDR_R = devm_ioremap_resource(dev, res);
 225         if (IS_ERR(chip->legacy.IO_ADDR_R))
 226                 return PTR_ERR(chip->legacy.IO_ADDR_R);
 227 
 228         res = gpio_nand_get_io_sync(pdev);
 229         if (res) {
 230                 gpiomtd->io_sync = devm_ioremap_resource(dev, res);
 231                 if (IS_ERR(gpiomtd->io_sync))
 232                         return PTR_ERR(gpiomtd->io_sync);
 233         }
 234 
 235         ret = gpio_nand_get_config(dev, &gpiomtd->plat);
 236         if (ret)
 237                 return ret;
 238 
 239         /* Just enable the chip */
 240         gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
 241         if (IS_ERR(gpiomtd->nce))
 242                 return PTR_ERR(gpiomtd->nce);
 243 
 244         /* We disable write protection once we know probe() will succeed */
 245         gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
 246         if (IS_ERR(gpiomtd->nwp)) {
 247                 ret = PTR_ERR(gpiomtd->nwp);
 248                 goto out_ce;
 249         }
 250 
 251         gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
 252         if (IS_ERR(gpiomtd->ale)) {
 253                 ret = PTR_ERR(gpiomtd->ale);
 254                 goto out_ce;
 255         }
 256 
 257         gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
 258         if (IS_ERR(gpiomtd->cle)) {
 259                 ret = PTR_ERR(gpiomtd->cle);
 260                 goto out_ce;
 261         }
 262 
 263         gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
 264         if (IS_ERR(gpiomtd->rdy)) {
 265                 ret = PTR_ERR(gpiomtd->rdy);
 266                 goto out_ce;
 267         }
 268         /* Using RDY pin */
 269         if (gpiomtd->rdy)
 270                 chip->legacy.dev_ready = gpio_nand_devready;
 271 
 272         nand_set_flash_node(chip, pdev->dev.of_node);
 273         chip->legacy.IO_ADDR_W  = chip->legacy.IO_ADDR_R;
 274         chip->ecc.mode          = NAND_ECC_SOFT;
 275         chip->ecc.algo          = NAND_ECC_HAMMING;
 276         chip->options           = gpiomtd->plat.options;
 277         chip->legacy.chip_delay = gpiomtd->plat.chip_delay;
 278         chip->legacy.cmd_ctrl   = gpio_nand_cmd_ctrl;
 279 
 280         mtd                     = nand_to_mtd(chip);
 281         mtd->dev.parent         = dev;
 282 
 283         platform_set_drvdata(pdev, gpiomtd);
 284 
 285         /* Disable write protection, if wired up */
 286         if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
 287                 gpiod_direction_output(gpiomtd->nwp, 1);
 288 
 289         ret = nand_scan(chip, 1);
 290         if (ret)
 291                 goto err_wp;
 292 
 293         if (gpiomtd->plat.adjust_parts)
 294                 gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
 295 
 296         ret = mtd_device_register(mtd, gpiomtd->plat.parts,
 297                                   gpiomtd->plat.num_parts);
 298         if (!ret)
 299                 return 0;
 300 
 301 err_wp:
 302         if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
 303                 gpiod_set_value(gpiomtd->nwp, 0);
 304 out_ce:
 305         if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
 306                 gpiod_set_value(gpiomtd->nce, 0);
 307 
 308         return ret;
 309 }
 310 
 311 static struct platform_driver gpio_nand_driver = {
 312         .probe          = gpio_nand_probe,
 313         .remove         = gpio_nand_remove,
 314         .driver         = {
 315                 .name   = "gpio-nand",
 316                 .of_match_table = of_match_ptr(gpio_nand_id_table),
 317         },
 318 };
 319 
 320 module_platform_driver(gpio_nand_driver);
 321 
 322 MODULE_LICENSE("GPL");
 323 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 324 MODULE_DESCRIPTION("GPIO NAND Driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mtd/nand/raw/gpio.c

DEFINITIONS
