This source file includes following definitions.
- ti_qspi_read
- ti_qspi_write
- ti_qspi_setup
- ti_qspi_restore_ctx
- qspi_is_busy
- ti_qspi_poll_wc
- qspi_write_msg
- qspi_read_msg
- qspi_transfer_msg
- ti_qspi_dma_callback
- ti_qspi_dma_xfer
- ti_qspi_dma_bounce_buffer
- ti_qspi_dma_xfer_sg
- ti_qspi_enable_memory_map
- ti_qspi_disable_memory_map
- ti_qspi_setup_mmap_read
- ti_qspi_exec_mem_op
- ti_qspi_start_transfer_one
- ti_qspi_runtime_resume
- ti_qspi_probe
- ti_qspi_remove
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8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/omap-dma.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <linux/sizes.h>
30
31 #include <linux/spi/spi.h>
32 #include <linux/spi/spi-mem.h>
33
34 struct ti_qspi_regs {
35 u32 clkctrl;
36 };
37
38 struct ti_qspi {
39 struct completion transfer_complete;
40
41
42 struct mutex list_lock;
43
44 struct spi_master *master;
45 void __iomem *base;
46 void __iomem *mmap_base;
47 size_t mmap_size;
48 struct regmap *ctrl_base;
49 unsigned int ctrl_reg;
50 struct clk *fclk;
51 struct device *dev;
52
53 struct ti_qspi_regs ctx_reg;
54
55 dma_addr_t mmap_phys_base;
56 dma_addr_t rx_bb_dma_addr;
57 void *rx_bb_addr;
58 struct dma_chan *rx_chan;
59
60 u32 spi_max_frequency;
61 u32 cmd;
62 u32 dc;
63
64 bool mmap_enabled;
65 int current_cs;
66 };
67
68 #define QSPI_PID (0x0)
69 #define QSPI_SYSCONFIG (0x10)
70 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
71 #define QSPI_SPI_DC_REG (0x44)
72 #define QSPI_SPI_CMD_REG (0x48)
73 #define QSPI_SPI_STATUS_REG (0x4c)
74 #define QSPI_SPI_DATA_REG (0x50)
75 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
76 #define QSPI_SPI_SWITCH_REG (0x64)
77 #define QSPI_SPI_DATA_REG_1 (0x68)
78 #define QSPI_SPI_DATA_REG_2 (0x6c)
79 #define QSPI_SPI_DATA_REG_3 (0x70)
80
81 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
82
83 #define QSPI_FCLK 192000000
84
85
86 #define QSPI_CLK_EN (1 << 31)
87 #define QSPI_CLK_DIV_MAX 0xffff
88
89
90 #define QSPI_EN_CS(n) (n << 28)
91 #define QSPI_WLEN(n) ((n - 1) << 19)
92 #define QSPI_3_PIN (1 << 18)
93 #define QSPI_RD_SNGL (1 << 16)
94 #define QSPI_WR_SNGL (2 << 16)
95 #define QSPI_RD_DUAL (3 << 16)
96 #define QSPI_RD_QUAD (7 << 16)
97 #define QSPI_INVAL (4 << 16)
98 #define QSPI_FLEN(n) ((n - 1) << 0)
99 #define QSPI_WLEN_MAX_BITS 128
100 #define QSPI_WLEN_MAX_BYTES 16
101 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
102
103
104 #define BUSY 0x01
105 #define WC 0x02
106
107
108 #define QSPI_DD(m, n) (m << (3 + n * 8))
109 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
110 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
111 #define QSPI_CKPOL(n) (1 << (n * 8))
112
113 #define QSPI_FRAME 4096
114
115 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
116
117 #define MEM_CS_EN(n) ((n + 1) << 8)
118 #define MEM_CS_MASK (7 << 8)
119
120 #define MM_SWITCH 0x1
121
122 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
123 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
124 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
125 #define QSPI_SETUP_ADDR_SHIFT 8
126 #define QSPI_SETUP_DUMMY_SHIFT 10
127
128 #define QSPI_DMA_BUFFER_SIZE SZ_64K
129
130 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
131 unsigned long reg)
132 {
133 return readl(qspi->base + reg);
134 }
135
136 static inline void ti_qspi_write(struct ti_qspi *qspi,
137 unsigned long val, unsigned long reg)
138 {
139 writel(val, qspi->base + reg);
140 }
141
142 static int ti_qspi_setup(struct spi_device *spi)
143 {
144 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
145 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
146 int clk_div = 0, ret;
147 u32 clk_ctrl_reg, clk_rate, clk_mask;
148
149 if (spi->master->busy) {
150 dev_dbg(qspi->dev, "master busy doing other transfers\n");
151 return -EBUSY;
152 }
153
154 if (!qspi->spi_max_frequency) {
155 dev_err(qspi->dev, "spi max frequency not defined\n");
156 return -EINVAL;
157 }
158
159 clk_rate = clk_get_rate(qspi->fclk);
160
161 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
162
163 if (clk_div < 0) {
164 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
165 return -EINVAL;
166 }
167
168 if (clk_div > QSPI_CLK_DIV_MAX) {
169 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
170 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
171 return -EINVAL;
172 }
173
174 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
175 qspi->spi_max_frequency, clk_div);
176
177 ret = pm_runtime_get_sync(qspi->dev);
178 if (ret < 0) {
179 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
180 return ret;
181 }
182
183 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
184
185 clk_ctrl_reg &= ~QSPI_CLK_EN;
186
187
188 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
189
190
191 clk_mask = QSPI_CLK_EN | clk_div;
192 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
193 ctx_reg->clkctrl = clk_mask;
194
195 pm_runtime_mark_last_busy(qspi->dev);
196 ret = pm_runtime_put_autosuspend(qspi->dev);
197 if (ret < 0) {
198 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
199 return ret;
200 }
201
202 return 0;
203 }
204
205 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
206 {
207 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
208
209 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
210 }
211
212 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
213 {
214 u32 stat;
215 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
216
217 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
218 while ((stat & BUSY) && time_after(timeout, jiffies)) {
219 cpu_relax();
220 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
221 }
222
223 WARN(stat & BUSY, "qspi busy\n");
224 return stat & BUSY;
225 }
226
227 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
228 {
229 u32 stat;
230 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
231
232 do {
233 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
234 if (stat & WC)
235 return 0;
236 cpu_relax();
237 } while (time_after(timeout, jiffies));
238
239 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
240 if (stat & WC)
241 return 0;
242 return -ETIMEDOUT;
243 }
244
245 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
246 int count)
247 {
248 int wlen, xfer_len;
249 unsigned int cmd;
250 const u8 *txbuf;
251 u32 data;
252
253 txbuf = t->tx_buf;
254 cmd = qspi->cmd | QSPI_WR_SNGL;
255 wlen = t->bits_per_word >> 3;
256 xfer_len = wlen;
257
258 while (count) {
259 if (qspi_is_busy(qspi))
260 return -EBUSY;
261
262 switch (wlen) {
263 case 1:
264 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
265 cmd, qspi->dc, *txbuf);
266 if (count >= QSPI_WLEN_MAX_BYTES) {
267 u32 *txp = (u32 *)txbuf;
268
269 data = cpu_to_be32(*txp++);
270 writel(data, qspi->base +
271 QSPI_SPI_DATA_REG_3);
272 data = cpu_to_be32(*txp++);
273 writel(data, qspi->base +
274 QSPI_SPI_DATA_REG_2);
275 data = cpu_to_be32(*txp++);
276 writel(data, qspi->base +
277 QSPI_SPI_DATA_REG_1);
278 data = cpu_to_be32(*txp++);
279 writel(data, qspi->base +
280 QSPI_SPI_DATA_REG);
281 xfer_len = QSPI_WLEN_MAX_BYTES;
282 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
283 } else {
284 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
285 cmd = qspi->cmd | QSPI_WR_SNGL;
286 xfer_len = wlen;
287 cmd |= QSPI_WLEN(wlen);
288 }
289 break;
290 case 2:
291 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
292 cmd, qspi->dc, *txbuf);
293 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
294 break;
295 case 4:
296 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
297 cmd, qspi->dc, *txbuf);
298 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
299 break;
300 }
301
302 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
303 if (ti_qspi_poll_wc(qspi)) {
304 dev_err(qspi->dev, "write timed out\n");
305 return -ETIMEDOUT;
306 }
307 txbuf += xfer_len;
308 count -= xfer_len;
309 }
310
311 return 0;
312 }
313
314 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
315 int count)
316 {
317 int wlen;
318 unsigned int cmd;
319 u8 *rxbuf;
320
321 rxbuf = t->rx_buf;
322 cmd = qspi->cmd;
323 switch (t->rx_nbits) {
324 case SPI_NBITS_DUAL:
325 cmd |= QSPI_RD_DUAL;
326 break;
327 case SPI_NBITS_QUAD:
328 cmd |= QSPI_RD_QUAD;
329 break;
330 default:
331 cmd |= QSPI_RD_SNGL;
332 break;
333 }
334 wlen = t->bits_per_word >> 3;
335
336 while (count) {
337 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
338 if (qspi_is_busy(qspi))
339 return -EBUSY;
340
341 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
342 if (ti_qspi_poll_wc(qspi)) {
343 dev_err(qspi->dev, "read timed out\n");
344 return -ETIMEDOUT;
345 }
346 switch (wlen) {
347 case 1:
348 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
349 break;
350 case 2:
351 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
352 break;
353 case 4:
354 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
355 break;
356 }
357 rxbuf += wlen;
358 count -= wlen;
359 }
360
361 return 0;
362 }
363
364 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
365 int count)
366 {
367 int ret;
368
369 if (t->tx_buf) {
370 ret = qspi_write_msg(qspi, t, count);
371 if (ret) {
372 dev_dbg(qspi->dev, "Error while writing\n");
373 return ret;
374 }
375 }
376
377 if (t->rx_buf) {
378 ret = qspi_read_msg(qspi, t, count);
379 if (ret) {
380 dev_dbg(qspi->dev, "Error while reading\n");
381 return ret;
382 }
383 }
384
385 return 0;
386 }
387
388 static void ti_qspi_dma_callback(void *param)
389 {
390 struct ti_qspi *qspi = param;
391
392 complete(&qspi->transfer_complete);
393 }
394
395 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
396 dma_addr_t dma_src, size_t len)
397 {
398 struct dma_chan *chan = qspi->rx_chan;
399 dma_cookie_t cookie;
400 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
401 struct dma_async_tx_descriptor *tx;
402 int ret;
403
404 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
405 if (!tx) {
406 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
407 return -EIO;
408 }
409
410 tx->callback = ti_qspi_dma_callback;
411 tx->callback_param = qspi;
412 cookie = tx->tx_submit(tx);
413 reinit_completion(&qspi->transfer_complete);
414
415 ret = dma_submit_error(cookie);
416 if (ret) {
417 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
418 return -EIO;
419 }
420
421 dma_async_issue_pending(chan);
422 ret = wait_for_completion_timeout(&qspi->transfer_complete,
423 msecs_to_jiffies(len));
424 if (ret <= 0) {
425 dmaengine_terminate_sync(chan);
426 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
427 return -ETIMEDOUT;
428 }
429
430 return 0;
431 }
432
433 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
434 void *to, size_t readsize)
435 {
436 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
437 int ret = 0;
438
439
440
441
442
443 while (readsize != 0) {
444 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
445 readsize);
446
447 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
448 dma_src, xfer_len);
449 if (ret != 0)
450 return ret;
451 memcpy(to, qspi->rx_bb_addr, xfer_len);
452 readsize -= xfer_len;
453 dma_src += xfer_len;
454 to += xfer_len;
455 }
456
457 return ret;
458 }
459
460 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
461 loff_t from)
462 {
463 struct scatterlist *sg;
464 dma_addr_t dma_src = qspi->mmap_phys_base + from;
465 dma_addr_t dma_dst;
466 int i, len, ret;
467
468 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
469 dma_dst = sg_dma_address(sg);
470 len = sg_dma_len(sg);
471 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
472 if (ret)
473 return ret;
474 dma_src += len;
475 }
476
477 return 0;
478 }
479
480 static void ti_qspi_enable_memory_map(struct spi_device *spi)
481 {
482 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
483
484 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
485 if (qspi->ctrl_base) {
486 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
487 MEM_CS_MASK,
488 MEM_CS_EN(spi->chip_select));
489 }
490 qspi->mmap_enabled = true;
491 qspi->current_cs = spi->chip_select;
492 }
493
494 static void ti_qspi_disable_memory_map(struct spi_device *spi)
495 {
496 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
497
498 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
499 if (qspi->ctrl_base)
500 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
501 MEM_CS_MASK, 0);
502 qspi->mmap_enabled = false;
503 qspi->current_cs = -1;
504 }
505
506 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
507 u8 data_nbits, u8 addr_width,
508 u8 dummy_bytes)
509 {
510 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
511 u32 memval = opcode;
512
513 switch (data_nbits) {
514 case SPI_NBITS_QUAD:
515 memval |= QSPI_SETUP_RD_QUAD;
516 break;
517 case SPI_NBITS_DUAL:
518 memval |= QSPI_SETUP_RD_DUAL;
519 break;
520 default:
521 memval |= QSPI_SETUP_RD_NORMAL;
522 break;
523 }
524 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
525 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
526 ti_qspi_write(qspi, memval,
527 QSPI_SPI_SETUP_REG(spi->chip_select));
528 }
529
530 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
531 const struct spi_mem_op *op)
532 {
533 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
534 u32 from = 0;
535 int ret = 0;
536
537
538 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
539 !op->addr.nbytes || op->addr.nbytes > 4)
540 return -ENOTSUPP;
541
542
543 from = op->addr.val;
544 if (from + op->data.nbytes > qspi->mmap_size)
545 return -ENOTSUPP;
546
547 mutex_lock(&qspi->list_lock);
548
549 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
550 ti_qspi_enable_memory_map(mem->spi);
551 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
552 op->addr.nbytes, op->dummy.nbytes);
553
554 if (qspi->rx_chan) {
555 struct sg_table sgt;
556
557 if (virt_addr_valid(op->data.buf.in) &&
558 !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
559 &sgt)) {
560 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
561 spi_controller_dma_unmap_mem_op_data(mem->spi->master,
562 op, &sgt);
563 } else {
564 ret = ti_qspi_dma_bounce_buffer(qspi, from,
565 op->data.buf.in,
566 op->data.nbytes);
567 }
568 } else {
569 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
570 op->data.nbytes);
571 }
572
573 mutex_unlock(&qspi->list_lock);
574
575 return ret;
576 }
577
578 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
579 .exec_op = ti_qspi_exec_mem_op,
580 };
581
582 static int ti_qspi_start_transfer_one(struct spi_master *master,
583 struct spi_message *m)
584 {
585 struct ti_qspi *qspi = spi_master_get_devdata(master);
586 struct spi_device *spi = m->spi;
587 struct spi_transfer *t;
588 int status = 0, ret;
589 unsigned int frame_len_words, transfer_len_words;
590 int wlen;
591
592
593 qspi->dc = 0;
594
595 if (spi->mode & SPI_CPHA)
596 qspi->dc |= QSPI_CKPHA(spi->chip_select);
597 if (spi->mode & SPI_CPOL)
598 qspi->dc |= QSPI_CKPOL(spi->chip_select);
599 if (spi->mode & SPI_CS_HIGH)
600 qspi->dc |= QSPI_CSPOL(spi->chip_select);
601
602 frame_len_words = 0;
603 list_for_each_entry(t, &m->transfers, transfer_list)
604 frame_len_words += t->len / (t->bits_per_word >> 3);
605 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
606
607
608 qspi->cmd = 0;
609 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
610 qspi->cmd |= QSPI_FLEN(frame_len_words);
611
612 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
613
614 mutex_lock(&qspi->list_lock);
615
616 if (qspi->mmap_enabled)
617 ti_qspi_disable_memory_map(spi);
618
619 list_for_each_entry(t, &m->transfers, transfer_list) {
620 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
621 QSPI_WLEN(t->bits_per_word));
622
623 wlen = t->bits_per_word >> 3;
624 transfer_len_words = min(t->len / wlen, frame_len_words);
625
626 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
627 if (ret) {
628 dev_dbg(qspi->dev, "transfer message failed\n");
629 mutex_unlock(&qspi->list_lock);
630 return -EINVAL;
631 }
632
633 m->actual_length += transfer_len_words * wlen;
634 frame_len_words -= transfer_len_words;
635 if (frame_len_words == 0)
636 break;
637 }
638
639 mutex_unlock(&qspi->list_lock);
640
641 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
642 m->status = status;
643 spi_finalize_current_message(master);
644
645 return status;
646 }
647
648 static int ti_qspi_runtime_resume(struct device *dev)
649 {
650 struct ti_qspi *qspi;
651
652 qspi = dev_get_drvdata(dev);
653 ti_qspi_restore_ctx(qspi);
654
655 return 0;
656 }
657
658 static const struct of_device_id ti_qspi_match[] = {
659 {.compatible = "ti,dra7xxx-qspi" },
660 {.compatible = "ti,am4372-qspi" },
661 {},
662 };
663 MODULE_DEVICE_TABLE(of, ti_qspi_match);
664
665 static int ti_qspi_probe(struct platform_device *pdev)
666 {
667 struct ti_qspi *qspi;
668 struct spi_master *master;
669 struct resource *r, *res_mmap;
670 struct device_node *np = pdev->dev.of_node;
671 u32 max_freq;
672 int ret = 0, num_cs, irq;
673 dma_cap_mask_t mask;
674
675 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
676 if (!master)
677 return -ENOMEM;
678
679 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
680
681 master->flags = SPI_MASTER_HALF_DUPLEX;
682 master->setup = ti_qspi_setup;
683 master->auto_runtime_pm = true;
684 master->transfer_one_message = ti_qspi_start_transfer_one;
685 master->dev.of_node = pdev->dev.of_node;
686 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
687 SPI_BPW_MASK(8);
688 master->mem_ops = &ti_qspi_mem_ops;
689
690 if (!of_property_read_u32(np, "num-cs", &num_cs))
691 master->num_chipselect = num_cs;
692
693 qspi = spi_master_get_devdata(master);
694 qspi->master = master;
695 qspi->dev = &pdev->dev;
696 platform_set_drvdata(pdev, qspi);
697
698 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
699 if (r == NULL) {
700 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 if (r == NULL) {
702 dev_err(&pdev->dev, "missing platform data\n");
703 ret = -ENODEV;
704 goto free_master;
705 }
706 }
707
708 res_mmap = platform_get_resource_byname(pdev,
709 IORESOURCE_MEM, "qspi_mmap");
710 if (res_mmap == NULL) {
711 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
712 if (res_mmap == NULL) {
713 dev_err(&pdev->dev,
714 "memory mapped resource not required\n");
715 }
716 }
717
718 if (res_mmap)
719 qspi->mmap_size = resource_size(res_mmap);
720
721 irq = platform_get_irq(pdev, 0);
722 if (irq < 0) {
723 ret = irq;
724 goto free_master;
725 }
726
727 mutex_init(&qspi->list_lock);
728
729 qspi->base = devm_ioremap_resource(&pdev->dev, r);
730 if (IS_ERR(qspi->base)) {
731 ret = PTR_ERR(qspi->base);
732 goto free_master;
733 }
734
735
736 if (of_property_read_bool(np, "syscon-chipselects")) {
737 qspi->ctrl_base =
738 syscon_regmap_lookup_by_phandle(np,
739 "syscon-chipselects");
740 if (IS_ERR(qspi->ctrl_base)) {
741 ret = PTR_ERR(qspi->ctrl_base);
742 goto free_master;
743 }
744 ret = of_property_read_u32_index(np,
745 "syscon-chipselects",
746 1, &qspi->ctrl_reg);
747 if (ret) {
748 dev_err(&pdev->dev,
749 "couldn't get ctrl_mod reg index\n");
750 goto free_master;
751 }
752 }
753
754 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
755 if (IS_ERR(qspi->fclk)) {
756 ret = PTR_ERR(qspi->fclk);
757 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
758 }
759
760 pm_runtime_use_autosuspend(&pdev->dev);
761 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
762 pm_runtime_enable(&pdev->dev);
763
764 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
765 qspi->spi_max_frequency = max_freq;
766
767 dma_cap_zero(mask);
768 dma_cap_set(DMA_MEMCPY, mask);
769
770 qspi->rx_chan = dma_request_chan_by_mask(&mask);
771 if (IS_ERR(qspi->rx_chan)) {
772 dev_err(qspi->dev,
773 "No Rx DMA available, trying mmap mode\n");
774 qspi->rx_chan = NULL;
775 ret = 0;
776 goto no_dma;
777 }
778 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
779 QSPI_DMA_BUFFER_SIZE,
780 &qspi->rx_bb_dma_addr,
781 GFP_KERNEL | GFP_DMA);
782 if (!qspi->rx_bb_addr) {
783 dev_err(qspi->dev,
784 "dma_alloc_coherent failed, using PIO mode\n");
785 dma_release_channel(qspi->rx_chan);
786 goto no_dma;
787 }
788 master->dma_rx = qspi->rx_chan;
789 init_completion(&qspi->transfer_complete);
790 if (res_mmap)
791 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
792
793 no_dma:
794 if (!qspi->rx_chan && res_mmap) {
795 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
796 if (IS_ERR(qspi->mmap_base)) {
797 dev_info(&pdev->dev,
798 "mmap failed with error %ld using PIO mode\n",
799 PTR_ERR(qspi->mmap_base));
800 qspi->mmap_base = NULL;
801 master->mem_ops = NULL;
802 }
803 }
804 qspi->mmap_enabled = false;
805 qspi->current_cs = -1;
806
807 ret = devm_spi_register_master(&pdev->dev, master);
808 if (!ret)
809 return 0;
810
811 pm_runtime_disable(&pdev->dev);
812 free_master:
813 spi_master_put(master);
814 return ret;
815 }
816
817 static int ti_qspi_remove(struct platform_device *pdev)
818 {
819 struct ti_qspi *qspi = platform_get_drvdata(pdev);
820 int rc;
821
822 rc = spi_master_suspend(qspi->master);
823 if (rc)
824 return rc;
825
826 pm_runtime_put_sync(&pdev->dev);
827 pm_runtime_disable(&pdev->dev);
828
829 if (qspi->rx_bb_addr)
830 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
831 qspi->rx_bb_addr,
832 qspi->rx_bb_dma_addr);
833 if (qspi->rx_chan)
834 dma_release_channel(qspi->rx_chan);
835
836 return 0;
837 }
838
839 static const struct dev_pm_ops ti_qspi_pm_ops = {
840 .runtime_resume = ti_qspi_runtime_resume,
841 };
842
843 static struct platform_driver ti_qspi_driver = {
844 .probe = ti_qspi_probe,
845 .remove = ti_qspi_remove,
846 .driver = {
847 .name = "ti-qspi",
848 .pm = &ti_qspi_pm_ops,
849 .of_match_table = ti_qspi_match,
850 }
851 };
852
853 module_platform_driver(ti_qspi_driver);
854
855 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
856 MODULE_LICENSE("GPL v2");
857 MODULE_DESCRIPTION("TI QSPI controller driver");
858 MODULE_ALIAS("platform:ti-qspi");